ISSI IS6MC256K-66, IS6MC256K-60, IS6MC256K-50 Datasheet
IS6MC256K
Integrated Silicon Solution, Inc.
SR004-1B-297
ISSI
®
IS6MC256K
256KB CMOS 3.1
COASt
CACHE MODULE PRELIMINARY
FOR THE INTEL PENTIUM™ CPU FEBRUARY 1997
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
FEATURES
• Low-cost, card-edge low-profile (CELP)
module with 160 leads
• For Intel Pentium CPU-based systems
• Operates with Pentium CPU clock speeds up
to 66 MHz
• Separate 5V and 3.3V power supplies
• Multiple GND pins and decoupling
capacitors for maximum noise immunity
• CMOS SRAMs for low power
• Conforms to Intel COASt specification
DESCRIPTION
The ISSI IS6MC256K is a secondary cache module designed for use with Intel Pentium CPUbased systems. This ISSI synchronous cache
module uses IS61C632 32K x 32 pipelined synchronous burst static RAMs which are mounted on
a multilayer board. In addition, this module uses a
single 5V 8-bit wide CMOS SRAM for the tag.
On-board logic, 3.3V data RAM, and a 5V tag RAM
provide an exact interface between the module
and the PC chipset. Five PD (presence detect)
input pins allow the system to determine the particular cache configuration.
ISSI's CELP 160-lead module provides space
savings that allows the customer to design additional functions into the system or to shrink the size
of the motherboard.
All inputs and outputs are TTL-compatible. Multiple GND pins and on-board decoupling capacitors provide maximum protection from noise.
IS6MC256K FUNCTIONAL BLOCK DIAGRAM
256KB PIPELINED BURST MODULE
PD0
32K x 32
Pipelined
Burst
SRAM
A17-A5
TWE
TIO7-TIO0
8K x 8
TAG SRAM
+5V
32K x 32
Pipelined
Burst
SRAM
D7-D0
D15-D8
D23-D16
D31-D24
D39-D32
D47-D40
D55-D48
D63-D56
CLK0
CWE4
CWE5
CWE6
CCS
CWE0
CWE1
CWE2
COE
ADSP
CADS
CADV
GWE
BWE
+3.3V
CWE7
CWE3
PD1
PD2
PD3
PD4
ECS1
ECS2
A3
A4
ISSI
®
PRESENCE DETECT TABLE
PD4 PD3 PD2 PD1 PD0 MODULE
NC NC NC NC NC No Cache Present
GND NC GND NC NC IS6MC256K
IS6MC256K
2
Integrated Silicon Solution, Inc.
SR004-1B-297
ISSI
®
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GND
TIO1
TIO7
TIO5
TIO3
NC
VCC5
NC
CADV
GND
COE
CWE5
CWE7
CWE1
VCC5
CWE3
NC
NC
GND
NC
A4
A6
A8
A10
VCC5
A17
GND
A9
A14
A15
NC
PD0
PD2
PD4
GND
CLK0
GND
D63
VCC5
D61
D59
D57
GND
D55
D53
D51
D49
GND
D47
D45
D43
VCC5
D41
D39
D37
GND
D35
D33
D31
VCC5
D29
D27
D25
GND
D23
D21
D19
VCC5
D17
D15
D13
GND
D11
D9
D7
VCC5
D5
D3
D1
GND
GND
TIO0
TIO2
TIO6
TIO4
NC
VCC3
TWE
CADS
GND
CWE4
CWE6
CWE0
CWE2
VCC3
CCS
GWE
BWE
GND
A3
A7
A5
A11
A16
VCC3
NC
GND
A12
A13
ADSP
ESC1
ESC2
PD1
PD3
GND
NC
GND
D62
VCC3
D60
D58
D56
GND
D54
D52
D50
D48
GND
D46
D44
D42
VCC3
D40
D38
D36
GND
D34
D32
D30
VCC3
D28
D26
D24
GND
D22
D20
D18
VCC3
D16
D14
D12
GND
D10
D8
D6
VCC3
D4
D2
D0
GND
TOP VIEW OF CONNECTOR (BURNDY CELP 2X80SC)
PIN CONFIGURATION
PIN DESCRIPTIONS
A17-A3 Address Inputs
A17-A5 Tag Address Inputs
CLK0 Clock Input
D63-D0 Cache Data Inputs/Outputs
TIO7-TIO0 Tag Inputs/Outputs
PD0-PD4 Presence Detect Pins
COE
Cache Data Output Enable Input
TWE
Tag Write Enable Input
CWE7-CWE
0 Cache Data Write Enable Input
CCS
Cache Data Chip Enable Input
CADS
Cache Address Status Input
ADSP
Processor Address Status Input
CADV
Burst Address Advance
GWE
Global Write Input
BWE
Byte Write Enable Input
ECS
1 Expansion Chip Select Input
ECS
2 Expansion Chip Select Output
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