ISSI IS63LV1024-12J, IS63LV1024-10T, IS63LV1024-10KI, IS63LV1024-12TI, IS63LV1024-12T Datasheet

IS63LV1024 ISSI

128K x 8 HIGH-SPEED CMOS STATIC RAM

®

3.3V REVOLUTIONARY PINOUT

FEATURES

• High-speed access times:
8, 10, 12 and 15 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for
greater noise immunity

• Easy memory expansion with CE and OE
options

• CE power-down

• Fully static operation: no clock or refresh
required

• TTL compatible inputs and outputs

• Single 3.3V power supply

• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)

SEPTEMBER 2000

DESCRIPTION

The ISSI IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.

When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.

The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.

FUNCTIONAL BLOCK DIAGRAM

A0-A16

VCC

GND

I/O0-I/O7

CE

OE

WE

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

128K X 8

MEMORY ARRAY

COLUMN I/O

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. H

10/02/00

1

IS63LV1024 ISSI

®

PIN CONFIGURATION

32-Pin SOJ

A0

A1

A2

A3

CE

I/O0

I/O1

Vcc

GND

I/O2

I/O3

WE

A4

A5

A6

A7

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A16

A15

A14

A13

OE

I/O7

I/O6

GND

Vcc

I/O5

I/O4

A12

A11

A10

A9

A8

PIN CONFIGURATION

32-Pin TSOP (Type II) (T)

A0
A1
A2
A3

CE
I/O0
I/O1

Vcc

GND

I/O2
I/O3

WE

A4
A5
A6
A7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8

PIN DESCRIPTIONS

A0-A16 Address Inputs

CE Chip Enable Input
OE Output Enable Input

TRUTH TABLE

Mode WE CE OE I/O Operation Vcc Current

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC1, ICC2

WE Write Enable Input

I/O0-I/O7 Bidirectional Ports

Read H L L DOUT ICC1, ICC2

Write L L X DIN ICC1, ICC2

Vcc Power

GND Ground

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. H

10/02/00

®

IS63LV1024 ISSI

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C 3.3V ± 0.15V

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V

VIH Input HIGH Voltage 2.2 VCC + 0.3 V

VIL Input LOW Voltage

ILI Input Leakage GND ≤ VIN ≤ VCC Com. –11µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –11µA

(1)

–0.3 0.8 V

Ind. –55

Ind. –55

Notes:

IL = –3.0V for pulse width less than 10 ns.

1. V

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC1 Vcc Operating VCC = Max., CE = VIL Com. — 160 — 150 — 130 — 120 mA

Supply Current I OUT = 0 mA, f = Max. Ind. — 170 — 160 — 140 — 130

ISB TTL Standby VCC = Max., Com. — 55 — 45 — 40 — 35 mA

Current VIN = VIH or VIL Ind. — 55 — 45 — 40 — 35
(TTL Inputs) CE ≥ VIH, f = Max

ISB1 TTL Standby VCC = Max., Com. — 25 — 25 — 25 — 25 mA

Current VIN = VIH or VIL Ind. — 30 — 30 — 30 — 30
(TTL Inputs) CE ≥ VIH, f = 0

ISB2 CMOS Standby VCC = Max., Com. — 5 — 5 — 5 — 5mA

Current CE ≤ VCC – 0.2V, Ind. — 10 — 10 — 10 — 10

(CMOS Inputs) VIN ≥ VCC – 0.2V, or

VIN ≤ 0.2V, f = 0

Notes:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

CAPACITANCE

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

CI/O Input/Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc = 3.3V.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. H

10/02/00

3