ISSI IS62WV51216ALL, IS62WV51216BLL User Manual

IS62WV51216ALL

®

IS62WV51216BLL

512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 45ns, 55ns

• CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby

• TTL compatible interface levels

• Single power supply
– 1.65V--2.2V V
– 2.5V--3.6V V

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Lead-free available

DD (62WV51216ALL)

DD (62WV51216BLL)

DESCRIPTION

The ISSI IS62WV51216ALL/ IS62WV51216BLL are high-
speed, 8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high­performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IS62WV51216ALL and IS62WV51216BLL are packaged
in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)
and 44-Pin TSOP (TYPE II).

ISSI

FEBRUARY 2005

FUNCTIONAL BLOCK DIAGRAM

A0-A18

VDD
GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CS2

CS1

OE

WE

UB

LB

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

512K x 16

MEMORY ARRAY

COLUMN I/O

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. B

02/24/05

1-800-379-4774

1

IS62WV51216ALL, IS62WV51216BLL ISSI

®

PIN CONFIGURATIONS
48-Pin mini BGA (7.2mm x 8.7mm)

1 2 3 4 5 6

A1

A
B
C
D
E
F
G
H

LB

I/O

I/O

GND

V

I/O

I/O

A18

8

9

DD

14

15

A0

OE

UB A3

I/O10A5

A17

I/O

11

I/O12GND

A14

I/O

13

A12

NC

A9

A8

A6

A7

A16

A15

A13

A10

A4

A2

CS1 I/O

I/O1I/O

I/O

3

I/O

GND

4

I/O

5

WE

A11 NC

CS2

V

I/O

I/O

DD`

PIN DESCRIPTIONS

A0-A18 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)

0

2

6

7

UB Upper-byte Control (I/O8-I/O15)
N C No Connection
VDD Power
GND Ground

44-Pin TSOP (Type II)

1

A4

2

A3

3

A2

4

A1

5

A0

6

CS1

7

I/O0

8

I/O1

9

I/O2

10

I/O3

11

V

DD

12

GND

13

I/O4

14

I/O5

15

I/O6

16

I/O7

17

WE

18

A16

19

A15

20

A14

21

A13

22

A12

44

A5

43

A6

42

A7

41

OE

40

UB

39

LB

38

I/O15

37

I/O14

36

I/O13

35

I/O12

34

GND

33

V

DD

32

I/O11

31

I/O10

30

I/O9

29

I/O8

28

A18

27

A8

26

A9

25

A10

24

A11

23

A17

2

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B

02/24/05

IS62WV51216ALL, IS62WV51216BLL ISSI

TRUTH TABLE

I/O PIN

Mode

WEWE

WE

WEWE

Not Selected X H X X X X High-Z High-Z I

Output Disabled H L H H L X High-Z High-Z ICC

Read H L H L L H DOUT High-Z ICC

Write L L H X L H DIN High-Z ICC

CS1CS1

CS1 CS2

CS1CS1

OEOE

OE

OEOE

LBLB

LB

LBLB

UBUB

UB I/O0-I/O7 I/O8-I/O15 VDD Current

UBUB

SB1, ISB2

X X L X X X High-Z High-Z ISB1, ISB2
XXXXHH High-Z High-Z ISB1, ISB2

H L H H X L High-Z High-Z ICC

H L H L H L High-Z DOUT
HLHLLL DOUT DOUT

L L H X H L High-Z DIN
LLHXLL DIN DIN

®

OPERATING RANGE (VDD)

Range Ambient Temperature IS62WV51216ALL (70ns) IS62WV51216BLL (55ns, 70ns) IS62WV51216BLL (45ns)

Commercial 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V 3.0 - 3.6V
Industrial –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. B

02/24/05

1-800-379-4774

3

IS62WV51216ALL, IS62WV51216BLL ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.2 to VDD+0.3 V
TBIAS Temperature Under Bias –40 to +85 °C
VDD VDD Related to GND –0.2 to +3.8 V
TSTG Storage Temperature –65 to +150 ° C
PT Power Dissipation 1.0 W

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions VDD Min. Max. Unit

VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V

IOH = -1 mA 2.5-3.6V 2.2 — V

VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V

IOL = 2.1 mA 2.5-3.6V — 0.4 V

VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V

2.5-3.6V 2.2 VDD + 0.3 V

(1)

VIL

Input LOW Voltage 1.65-2.2V – 0. 2 0 .4 V

2.5-3.6V –0.2 0.6 V
ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled – 1 1 µA

Notes:

1. VIL (min.) = –1.0V for pulse width less than 10 ns.

4

Integrated Silicon Solution, Inc. — www.issi.com —

1-800-379-4774

Rev. B

02/24/05

IS62WV51216ALL, IS62WV51216BLL ISSI

®

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 8 pF
COUT Input/Output Capacitance VOUT = 0V 10 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

AC TEST CONDITIONS

Parameter 62WV51216ALL 62WV51216BLL

(Unit) (Unit)

Input Pulse Level 0.4V to VDD-0.2 0.4V to VDD-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing VREF VREF

and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2

62WV51216ALL 62WV51216BLL

(1.65V - 2.2V) (2.5V - 3.6V)

R1(Ω) 3070 1029
R2(Ω) 3150 1728
VREF 0.9V 1.5V
VTM 1.8V 2.8V

AC TEST LOADS

R1

VTM

OUTPUT

30 pF

Including

jig and

scope

R2

VTM

OUTPUT

5 pF

Including

jig and

scope

R1

R2

Figure 1

Integrated Silicon Solution, Inc. — www.issi.com —

Rev. B

02/24/05

1-800-379-4774

Figure 2

5