ISSI IS62VV25616LL-85T, IS62VV25616LL-85MI, IS62VV25616LL-85M, IS62VV25616LL-70TI, IS62VV25616LL-70T Datasheet
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Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00C
11/30/00
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
IS62VV25616L/LL ISSI
®
256K x 16 LOW VOLTAGE, 1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 70, 85, 100 ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 1.65V-1.95V V
CC power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (7.2mm x 8.7mm)
DESCRIPTION
The ISSI IS62VV25616L and IS62VV25616LL are
high-speed, 4,194,304 bit static RAMs organized as
262,144 words by 16 bits. They are fabricated using
ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
For the IS62VV25616L/LL, when CE is HIGH (deselected)
or CE is low and both LB and UB are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62VV25616L and IS62VV25616LL are packaged in
the JEDEC standard 44-pin TSOP (Type II) and 48-pin
mini BGA (7.2mm x 8.7mm).
FUNCTIONAL BLOCK DIAGRAM
PRELIMINARY INFORMATION
NOVEMBER 2000
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS62VV25616L/LL ISSI
®
PIN CONFIGURATIONS
44-Pin TSOP (Type II) 48-Pin mini BGA (7.2mm x 8.7mm)
TRUTH TABLE
I/O PIN
Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 Vcc Current
Not Selected X H X X X High-Z High-Z ISB1, ISB2
X L X H H High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC
X L X H H High-Z High-Z ISB1, ISB2
Read H L L L H DOUT High-Z ICC
H L L H L High-Z DOUT
HLLLL DOUT DOUT
Write L L X L H DIN High-Z ICC
L L X H L High-Z DIN
LLXLL DIN DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A17
PIN DESCRIPTIONS
A0-A17 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vcc Power
GND Ground
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
N/C
I/O
8
UB A3
A4
CE I/O
0
I/O
9
I/O10A5
A6
I/O1I/O
2
GND
I/O
11
A17
A7
I/O
3
Vcc
Vcc
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11 NC
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00C
11/30/00
IS62VV25616L/LL ISSI
®
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = -0.1 mA 1.4 — V
VOL Output LOW Voltage IOL = 0.1 mA — 0.2 V
VIH Input HIGH Voltage 1.4 VCC + 0.2 V
VIL
(1)
Input LOW Voltage –0.3 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –11µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –11µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.2 to Vcc+0.3 V
TBIAS Temperature Under Bias –40 to +85 °C
VCC Vcc Related to GND –0.2 to +2.6 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 1.65V - 1.95V
Industrial –40°C to +85°C 1.65V - 1.95V
CAPACITANCE
(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Input/Output Capacitance VOUT = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
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