ISSI IS61S6432-8PQ, IS61S6432-7TQI, IS61S6432-7PQI, IS61S6432-7PQ, IS61S6432-8TQI Datasheet

IS61S6432 ISSI

64K x 32 SYNCHRONOUS

®

PIPELINE STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and
control

• Pentium™ or linear burst sequence control using
MODE input

• Three chip enables for simple depth expansion
and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin TQFP and PQFP package

• Single +3.3V power supply

• Two Clock enables and one Clock disable to
eliminate multiple bank bus contention

• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state

• Industrial temperature available

JUNE 2001

DESCRIPTION

The

ISSI

IS61S6432 is a high-speed, low-power
synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™,
680X0™, and PowerPC™ microprocessors. It is organized
as 65,536 words by 32 bits, fabricated with
CMOS technology. The device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge­triggered single clock input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3
controls DQ17-DQ24, BW4 controls DQ25-DQ32,
conditioned by BWE being LOW. A LOW on GW input would
cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61S6432 and controlled by the ADV
(burst address advance) input pin.

Asynchronous signals include output enable (OE), sleep
mode input (ZZ), clock (CLK) and burst mode input (MODE).
A HIGH input on the ZZ pin puts the SRAM in the power­down state. When ZZ is pulled LOW (or no connect), the
SRAM normally operates after three cycles of the wake-up
period. A LOW input, i.e., GND
LINEAR Burst. A VCCQ (or no connect) on MODE pin selects
INTERLEAVED Burst.

Q, on MODE pin selects

ISSI

's advanced

FAST ACCESS TIME

Symbol Parameter -200

tKQ CLK Access Time 45555678ns
tKC Cycle Time 5 6 7.5 8.5 10 12 13 15 ns
— Frequency 200 166 133 117 100 83 75 66 MHz

Note:

1. ADVANCE INFORMATION ONLY.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev. B
06/28/01

(1)

-166 -133 -117 -5 -6 -7 -8 Unit

1

IS61S6432 ISSI

BLOCK DIAGRAM

MODE

CLK

ADV

ADSC
ADSP

CLK

BINARY

COUNTER

CE

CLR

Q0

Q1

A0

A1

A0'

A1'

64K x 32

MEMORY

ARRAY

®

A15-A0

GW

BWE

BW4

BW3

BW2

BW1

16

D

Q

14 16

ADDRESS

REGISTER

CE

CLK

D

Q

32

32

DQ32-DQ25

BYTE WRITE

REGISTERS

CLK

D

Q

DQ24-DQ17

BYTE WRITE

REGISTERS

CLK

D

Q

DQ16-DQ9

BYTE WRITE

REGISTERS

CLK

D

Q

DQ8-DQ1

BYTE WRITE

REGISTERS

CLK

PB

CE1

CE2

CE3

OE

D

ENABLE

REGISTER

CE

CLK

D

ENABLE

DELAY

REGISTER

CLK

4

Q

Q

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

OE

32

DATA[32:1]

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev.B

06/28/01

IS61S6432 ISSI

PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)

A6A7CE1

CE2

BW4

BW3

BW2

BW1

CE3

VCC

GND

NC
DQ17
DQ18

VCCQ

GNDQ

DQ19
DQ20
DQ21
DQ22

GNDQ

VCCQ

DQ23
DQ24

VCCQ

VCC

NC

GND
DQ25
DQ26

VCCQ

GNDQ

DQ27
DQ28
DQ29
DQ30

GNDQ

VCCQ

DQ31
DQ32

NC

CLKGWBWEOEADSC

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

ADSP

ADVA8A9

46 47 48 49 50

80

NC

79

DQ16

78

DQ15

77

VCCQ

76

GNDQ

75

DQ14

74

DQ13

73

DQ12

72

DQ11

71

GNDQ

70

VCCQ

69

DQ10

68

DQ9

67

GND

66

NC

65

VCC

64

ZZ

63

DQ8

62

DQ7

61

VCCQ

60

GNDQ

59

DQ6

58

DQ5

57

DQ4

56

DQ3

55

GNDQ

54

VCCQ

53

DQ2

52

DQ1

51

NC

®

A5A4A3A2A1

MODE

A0

NC

NC

GND

VCC

NC

NC

A10

PIN DESCRIPTIONS

A0-A15 Address Inputs
CLK Clock

ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW4 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE1, CE2, CE3 Synchronous Chip Enable

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev.B

06/28/01

A11

A12

A13

NC

A14

A15

OE Output Enable
DQ1-DQ32 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply: +3.3V
GNDQ Isolated Output Buffer Ground
NC No Connect

3

®

IS61S6432 ISSI

TRUTH TABLE

Address

Operation Used CE1 CE2 CE3 ADSP ADSC ADV WRITE OE DQ

Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X H L X X X High-Z
Deselected, Power-down None L X H H L X X X High-Z
Read Cycle, Begin Burst External L H L L X X X L Q
Read Cycle, Begin Burst External L H L L X X X H High-Z
Write Cycle, Begin Burst External L H L H L X L X D
Read Cycle, Begin Burst External L H L H L X H L Q
Read Cycle, Begin Burst External L H L H L X H H High-Z
Read Cycle, Continue Burst Next X X X H H L H L Q
Read Cycle, Continue Burst Next X X X H H L H H High-Z
Read Cycle, Continue Burst Next H X X X H L H L Q
Read Cycle, Continue Burst Next H X X X H L H H High-Z
Write Cycle, Continue Burst Next X X X H H L L X D
Write Cycle, Continue Burst Next H X X X H L L X D
Read Cycle, Suspend Burst Current X X X HHHHLQ
Read Cycle, Suspend Burst Current X X X HHHHHHigh-Z
Read Cycle, Suspend Burst Current H X X X H H H L Q
Read Cycle, Suspend Burst Current H X X X HHHHHigh-Z
Write Cycle, Suspend Burst Current X X X H H H L X D
Write Cycle, Suspend Burst Current H X X X H H L X D

Notes:

1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).

2. Wait states are inserted by suspending burst.

3. "X" means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.

4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.

5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.

PARTIAL TRUTH TABLE

Function GW BWE BW1 BW2 BW3 BW4

READ H H X X X X
READ H X H H H H
WRITE Byte 1 H L L H H H
WRITE All Bytes X LLLLL
WRITE All Bytes L XXXXX

PB

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev.B

06/28/01

IS61S6432 ISSI

INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

LINEAR BURST ADDRESS TABLE (MODE = GNDQ)

0,0

0,1A1', A0' = 1,1

®

1,0

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PD Power Dissipation 1.8 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for for Address and Control Inputs –0.5 to 5.5 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

(1,2,3)

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev.B

06/28/01

5

IS61S6432 ISSI

®

DC ELECTRICAL CHARACTERISTICS

(1,2)

(Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND - VIN - VCCQ

(2)

Com. –55µA

Ind. –10 10

ILO Output Leakage Current GND - VOUT - VCCQ, OE = VIH Com. –55µA

Ind. –10 10

Notes:

1. MODE pin have an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect,
tied to GND,or tied to V

2. MODE pin should be tied to Vcc or GND. They exhibit ±30 µA maximum leakage current when tied
to - GND + 0.2V or • Vcc – 0.2V.

CCQ.

POWER SUPPLY CHARACTERISTICS (Operating Range)

(1)

-200

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

-166 -133 -117

ICC AC Operating Device Selected, Com. — 400 — 215 — 205 — 195 mA

Supply Current All Inputs = VIL or VIH Ind. —— —— —— —205

OE = VIH, Cycle Time • tKC min.

ISB Standby Current Device Deselected, Com. — 100 — 70 — 60 — 50 mA

VCC = Max., Ind. —— —— —— —60
CLK Cycle Time • tKC min.

IZZ Power-Down ZZ = VCCQ, CLK Running Com. — 5 — 5 — 5 — 5mA

Mode Current All Inputs - GND + 0.2V Ind. —— —— —— —10

or • VCC – 0.2V

Note:

1. ADVANCE INFORMATION ONLY.

-5 -6 -7 -8

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC AC Operating Device Selected, Com. — 175 — 165 — 150 — 140 mA

Supply Current All Inputs = VIL or VIH Ind. — 185 — 175 — 160 — 150

OE = VIH, Cycle Time • tKC min.

ISB Standby Current Device Deselected, Com. — 25 — 25 — 25 — 25 mA

VCC = Max., Ind. — 35 — 35 — 35 — 35
CLK Cycle Time • tKC min.

IZZ Power-Down ZZ = VCCQ, CLK Running Com. — 5 — 5 — 5 — 5mA

Mode Current All Inputs - GND + 0.2V Ind. — 10 — 10 — 10 — 10

or • VCC – 0.2V

PB

Integrated Silicon Solution, Inc. • 1-800-379-4774

Rev.B

06/28/01