ISSI IS61NW6432-6PQ, IS61NW6432-5TQ, IS61NW6432-5PQ, IS61NW6432-8TQ, IS61NW6432-8PQ Datasheet
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IS61NW6432
IS61NW6432
®
ISSI
64K x 32 SYNCHRONOUS STATIC RAM
WITH NO-WAIT STATE BUS FEATURE
FEATURES
• Fast access time:
– 5 ns-100 MHz; 6 ns-83 MHz;
– 7 ns-75 MHz; 8 ns-66 MHz
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-pin TQFP and PQFP package
• Single +3.3V power supply
• Optional data strobe pin (#80) for latching data
(See page 12 for detailed timing)
DESCRIPTION
The IS61NW6432 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, highperformance, 'no-wait' bus, secondary cache for the Pentium,
680X0, and Power PC microprocessors. It is organized as
65,536 words by 32 bits, fabricated with ISSI's advanced
CMOS technology.
Incorporating a 'no-wait' bus, wait cycles are eliminated when
the bus switches from read to write, or write to read. This
device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit.
All synchronous inputs pass through registers controlled by a
positive-edge-triggered clock input. Operations may be
suspended and all synchronous inputs ignored when Clock
Enable,
their previous values.
When the ADV/LD is HIGH the internal burst counter is
incremented. New external addresses can be loaded when
ADV/LD is LOW.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock inputs and when RD/WE is LOW.
Separate byte enables allow individual bytes to be written.
BW1
I/O17-I/O24;
when
CEN
is HIGH. In this state the internal device will hold
controls I/O1-I/O8;
BW4
BW1, BW2, BW3
ADVANCE INFORMATION
JULY 1998
BW2
controls I/O9-I/O16;
controls I/O25-I/O32. All Bytes are written
, and
BW4
are LOW.
BW3
controls
MODE pin upon power up is in interleave burst mode. It can be
connected to GNDQ or VCCQ to alter power up state.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B
07/15/98
1
IS61NW6432
BLOCK DIAGRAM
MODE
A0-A15
CE1, CE2, CE3
64K x 32 BIT
MEMORY ARRAY
I
O
ADDRESS
R/W
CEN
ADV/LD
BW1
BW2
BW3
BW4
OE
I
O
INPUT REGISTER
O
I
CONTROL
CONTROL LOGIC
D
IN
MUX
D
OUT
SEL
I
CLOCK
OUTPUT
REGISTER
O
OE
2
GATE
DATA
I/O1-I/O32
DS
(Optional)
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B
07/15/98
IS61NW6432
PIN CONFIGURATION
100-Pin TQFP and PQFP (Top View)
A6A7CE1
CE2
BW4
BW3
BW2
BW1
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
NC
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
I/O17
I/O18
VCCQ
GNDQ
I/O19
I/O20
I/O21
I/O22
GNDQ
VCCQ
I/O23
I/O24
VCC
VCC
VCC
GND
I/O25
I/O26
VCCQ
GNDQ
I/O27
I/O28
I/O29
I/O30
GNDQ
VCCQ
I/O31
I/O32
CE3
VCC
GND
CLK
R/W
CENOEADV/LDNCNCA8A9
46 47 48 49 50
80
NC
79
I/O16
78
I/O15
77
VCCQ
76
GNDQ
75
I/O14
74
I/O13
73
I/O12
72
I/O11
71
GNDQ
70
VCCQ
69
I/O10
68
I/O9
67
GND
66
VCC
65
VCC
64
GND
63
I/O8
62
I/O7
61
VCCQ
60
GNDQ
59
I/O6
58
I/O5
57
I/O4
56
I/O3
55
GNDQ
54
VCCQ
53
I/O2
52
I/O1
51
NC
A5A4A3A2A1
MODE
PIN DESCRIPTIONS
A0-A15 Address Inputs
CLK Clock
CEN
ADV/
CD
BW1-BW4
R/
W
CE1
, CE2,
CE3
OE
Note:
1. Optional, NC or DS.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B
07/15/98
Clock Enable
Advance Load
Synchronous Byte Write Enable
Read/Write
Synchronous Chip Enable
Output Enable
A0
NC
NC
GND
VCC
NC
NC
A13
DS
A14
(1)
A15
NC
Data Strobe
A10
A11
A12
I/O1-I/O32 Data Input/Output
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply: +3.3V
GNDQ Isolated Output Buffer Ground
NC No Connect
3
IS61NW6432
TRUTH TABLE
(1)
Address
Operation Used R/
WW
W
WW
CExCEx
CEx
CExCEx
ADV/
LDLD
LD
LDLD
CENCEN
CEN
CENCEN
BWxBWx
BWx
BWxBWx
Begin New Write Cycle External LLLLValid L-H
Begin New Read Cycle External H L L L X L-H
Advance Burst Counter
(2)
Internal X X H L Valid L-H
(Burst Write)
Advance Burst Counter Internal X X H L X L-H
(Burst Read)
Deselect (2 Cycle)
Hold/NOOP
Notes:
1. "X" Means don't care.
2. When ADV/LD signal is sampled HIGH, the internal burst counter is incremented. The R/W signal is ignored when the
counter is advanced. Therefore, the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal
when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when
tri-state two cycles after deselect is initiated.
4. When
CEN
The state of all the internal registers remains unchanged.
(3)
(4)
CEx
is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part.
X X H L L X L-H
XXXXHXL-H
is sampled HIGH and ADV/LD sampled LOW at rising edge of clock. The data bus will
CLK
PARTIAL TRUTH TABLE (Non-burst)
Function R/
W
WW
BW1BW1
BW1
BW1BW1
BW2BW2
BW2
BW2BW2
BW3BW3
BW3
BW3BW3
BW4BW4
BW4
BW4BW4
CExCEx
CEx
CExCEx
ADV/
WW
Read H XXXXL L
Write Byte 1 L L H H H L L
Write Byte 2 L H L H H L L
Write Byte 3 L H H L H L L
Write Byte 4 L H H H L L L
Write All Bytes LLLLLL L
FUNCTIONAL TIMING DIAGRAM
CYCLE
CLOCK
ADDRESS
(A0-A15)
CONTROL
(BWx, R/W, ADV/LD)
n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37
A29 A30 A31 A32 A33 A34 A35 A36 A37
C29 C30 C31 C32 C33 C34 C35 C36 C37
LDLD
LD
LDLD
4
DATA
(I/O1-I/O32)
D27 D28 D29 D30 D31 D32 D33 D34 D35
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR050-0B
07/15/98
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