ISSI IS42S81600A, IS42S16800A, IS42S32400A User Manual
查询42S16800A供应商
IS42S81600A,
IS42S16800A,
IS42S32400A,
16Meg x 8, 8Meg x16 & 4Meg x 32
128-MBIT SYNCHRONOUS DRAM
FEATURES
• Clock frequency: 166,143,100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Power supply
DD VDDQ
V
IS42S81600A 3.3V 3.3V
IS42S16800A 3.3V 3.3V
IS42S32400A 3.3V 3.3V
OVERVIEW
ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock
input.The 128Mb SDRAM is organized as follows.
IS42S81600A IS42S16800A IS42S32400A
4M x8x4 Banks 2M x16x4 Banks 1M x32x4 Banks
54-pin TSOPII 54-pin TSOPII 86-pin TSOPII
®
ISSI
PRELIMINARY INFORMATION
JANUARY 2005
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial Temperature Availability
• Lead-free Availability
KEY TIMING PARAMETERS
Parameter -6 -7 -10 Unit
Clk Cycle Time
CAS Latency = 3 6 7 10 ns
CAS Latency = 2 - 10 10 ns
Clk Frequency
CAS Latency = 3 166 143 100 M h z
CAS Latency = 2 - 100 100 M hz
Access Time from Clock
CAS Latency = 3 5.4 5.4 7 ns
CAS Latency = 2 - 6 9 ns
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION, Rev. 00C
01/20/05
1-800-379-4774
1
IS42S81600A, IS42S16800A, IS42S32400A
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V VDD
and 3.3V VDDQ memory systems containing 134,217,728
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK. All
inputs and outputs are LVTTL compatible.
The 128Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function enabled.
Precharge
one bank while accessing one of the
other three banks will hide the
seamless, high-speed, random-access operation.
SDRAM
a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
®
ISSI
precharge
read and write accesses are burst oriented starting at
cycles and provide
FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY)
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
ADDRESS
LATCH
12
ROW
ADDRESS LATCH
9
BURST COUNTER
ADDRESS BUFFER
MODE
REGISTER
COLUMN
COLUMN
REFRESH
CONTROLLER
12
MULTIPLEXER
REFRESH
CONTROLLER
REFRESH
COUNTER
ADDRESS
BUFFER
12
SELF
ROW
12
ROW DECODER
BANK CONTROL LOGIC
DATA IN
BUFFER
16
DATA OUT
BUFFER
16 16
4096
4096
4096
4096
MEMORY CELL
SENSE AMP I/O GATE
512
(x 16)
COLUMN DECODER
9
16
2
ARRAY
BANK 0
DQML
DQMH
I/O 0-15
V
DD/VDDQ
Vss/V
ss
Q
2
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x8
®
ISSI
I/O0
V
DD
I/O1
V
SS
I/O2
V
DD
I/O3
V
SS
CAS
RAS
BA0
BA1
V
DD
NC
NC
NC
NC
V
DD
NC
WE
CS
A10
A0
A1
A2
A3
V
DD
1
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O7
V
SS
NC
I/O6
V
DD
NC
I/O5
V
SS
NC
I/O4
V
DD
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Q
Q
Q
Q
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A9 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O7 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
WE Write Enable
DQ M x 8 Lower Byte, Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
3
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
®
ISSI
V
DD
I/O0
V
DD
I/O1
I/O2
V
SS
I/O3
I/O4
V
DD
I/O5
I/O6
SS
V
I/O7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
I/O15
V
SS
Q
I/O14
I/O13
V
DD
Q
I/O12
I/O11
V
SS
Q
I/O10
I/O9
DD
Q
V
I/O8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A8 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O15 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
4
Integrated Silicon Solution, Inc. — www.issi.com —
WE Write Enable
DQML x16 Lower Byte, Input/Output Mask
DQMH x16 Upper Byte, Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
1
NC
CS
NC
2
3
Q
4
5
6
Q
7
8
9
Q
10
11
12
Q
13
14
15
DD
16
17
18
19
20
21
22
23
24
25
A0
26
A1
27
A2
28
29
DD
30
31
32
Q
33
34
35
Q
36
37
38
Q
39
40
41
Q
42
43
DD
I/O0
V
DD
I/O1
I/O2
V
SS
I/O3
I/O4
DD
V
I/O5
I/O6
V
SS
I/O7
V
DQM0
CAS
RAS
A11
BA0
BA1
A10
DQM2
V
I/O16
V
SS
I/O17
I/O18
V
DD
I/O19
I/O20
V
SS
I/O21
I/O22
V
DD
I/O23
V
WE
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
I/O15
V
SS
I/O14
I/O13
V
DD
I/O12
I/O11
SS
V
I/O10
I/O9
V
DD
I/O8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
I/O31
V
DD
I/O30
I/O29
V
SS
I/O28
I/O27
V
DD
I/O26
I/O25
V
SS
I/O24
V
SS
®
ISSI
Q
Q
Q
Q
Q
Q
Q
Q
PIN DESCRIPTIONS
A0-A11 Row Address Input
A0-A7 Column Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O31 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
WE Write Enable
DQM0-DQM3 x32 Input/Output Mask
VDD Power
Vss Ground
VDDQ Power Supply for I/O Pin
VssQ Ground for I/O Pin
N C No Connection
1-800-379-4774
5
IS42S81600A, IS42S16800A, IS42S32400A
PIN FUNCTIONS
Symbol Type Function (In Detail)
®
ISSI
A0-A11
BA0, BA1 Input Pin
CAS
CKE
CLK
CS
DQML,
DQMH mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A9 (x8); A0-A8
(x16); A0-A7(x32) with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command
to determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode.
CKE is an asynchronous i
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer.
WhenDQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can
be written to the device. WhenDQML or DQMH is HIGH, input data is masked and
cannot be written to the device.
nput.
DQM0-DQM3
DQ M Input Pin For IS42S81600A only.
RAS
WE
VDDQ
VDD
VSSQ
VSS
6
Input Pin For IS42S32400A only
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
VDDQ is the output buffer power supply.
VDD is the device internal power supply.
VSSQ is the output buffer ground.
VSS is the device internal ground.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
GENERAL DESCRIPTION
READ
The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A9 (x8); A0-A8 (x16); A0-A7 (x32) provides the
starting column location. When A10 is HIGH, this command
functions as an AUTO PRECHARGE command. When the
auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst. The row will
remain open for subsequent accesses when AUTO
PRECHARGE is not selected. DQ’s read data is subject to
the logic level on the DQM inputs two clocks earlier. When
a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide
valid data when the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A9
(x8); A0-A8 (x16); A0-A7 (x32). Whether or not AUTOPRECHARGE is used is determined by A10.
The row being accessed will be precharged at the end of the
WRITE burst, if AUTO PRECHARGE is selected. If AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
A memory array is written with corresponding input data on
DQ’s and DQM input logic level appearing at the same time.
Data will be written to memory when DQM signal is LOW.
When DQM is HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. BA0,
BA1 can be used to select which bank is precharged or they
are treated as “Don’t Care”. A10 determined whether one or
all banks are precharged. After executing this command,
the next command for the selected banks(s) is executed
after passage of the period tRP, which is the period required
for bank precharging. Once a bank has been precharged,
it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge
is initiated at the earliest valid stage within a burst. This
function allows for individual-bank precharge without requiring an explicit command. A10 to enable the AUTO
PRECHARGE function in conjunction with a specific READ
or WRITE command. For each individual READ or WRITE
command, auto precharge is either enabled or disabled.
AUTO PRECHARGE does not apply except in full-page
burst mode. Upon completion of the READ or WRITE burst,
a precharge of the bank/row that is addressed is automatically performed.
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC) is
required for a single refresh operation, and no other commands can be executed during this period. This command is
executed at least 4096 times for every 64ms. During an
AUTO REFRESH command, address bits are “Don’t Care”.
This command corresponds to CBR Auto-refresh.
BURST TERMINATE
The BURST TERMINATE command forcibly terminates the
burst read and write operations by truncating either fixedlength or full-page bursts and the most recently registered
READ or WRITE command prior to the BURST TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait states.
LOAD MODE REGISTER
During the LOAD MODE REGISTER command the mode
register is loaded from A0-A11. This command can only be
issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.
®
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
7
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
COMMAND TRUTH TABLE
CKE A11
Function Symbol n – 1 n
Device deselect H × H × × × × × × ×
No operation H × L H H H × × ×
Burst stop H H L H H L × × × ×
Read H × L H L H V V L V
Read with auto precharge H × L H L H V V H V
Write H × L H L L V V L V
Write with auto precharge H × L H L L V V H V
Bank activate H × L L H H V V V V
Precharge select bank H × L L H L V V L ×
Precharge all banks H × L L H L × × H ×
Mode register set H × L L L L L L L V
CSCS
CS
CSCS
RASRAS
RAS
RASRAS
CASCAS
CAS
CASCAS
WEWE
WE B A1 BA 0 A1 0 A9 - A0
WEWE
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
DQM TRUTH TABLE
CKE DQM
Function Symbol n- 1 n U L
Data write / output enable H × L L
Data mask / output disable H × H H
Upper byte write enable / output enable H × L ×
Lower byte write enable / output enable H × × L
Upper byte write inhibit / output disable H × H ×
Lower byte write inhibit / output disable H × × H
Note: H=V
IH, L=VIL x= VIH or VIL, V = Valid Data.
8
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
CKE TRUTH TABLE
CKE
Current State /Function n – 1 n CS RAS CAS WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend mode exit L H × × × × ×
Auto refresh command Idle H H L L L H ×
Self refresh entry Idle H L L L L H ×
Power down entry Idle H L L H H H ×
HL H × ×× ×
Deep power down entry H L L H H L ×
Self refresh exit L H L H H H ×
LH H× ×× ×
Power down exit L H L H H H ×
LH H× ×× ×
Deep power down exit L H × × × × ×
®
ISSI
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
9
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE
CSCS
RAS RAS
CASCAS
CS
RAS
CSCS
RAS RAS
Idle H X X X X DESL Nop
LHHH X NOP Nop
LHHL X BST Nop
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L A, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT Row activating
L L H L BA, A10 PRE/PALL N op
L L L H X REF Auto refresh
L L L L OC, BA1=L MRS Mode register set
L L L L OC, BA1=H EMRS Extended mode register set
Row Active H X X X X DESL Nop
LHHH X NOP Nop
LHHL X BST Nop
L H L H BA, CA, A10 READ/READA Begin read
L H L L BA, CA, A10 WRIT/ WRITA Begin write
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Precharge/Precharge all banks
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Read H X X X X DESL Continue burst to end to
L H H H X NOP Continue burst to end Row
L H H L X BST Burst stop Row active
L H L H BA, CA, A10 READ/READA Terminate burst,
L H L L BA, CA, A10 WRIT/WRITA Terminate burst,
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Terminate burst
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write H X X X X DESL Continue burst to end
L H H H X NOP Continue burst to end
L H H L X BST Burst stop Row active
L H L H BA, CA, A10 READ/READA Terminate burst, start read :
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write :
L L H H BA, RA RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Terminate burst Precharging
L L L H X REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(2)
(2)
(3)
(3)
(2)
Row active
Row active
begin new read
begin write
(5, 6)
(2)
Precharging
Write recovering
Write recovering
Determine AP
Determine AP
(2)
(5)
(5, 6)
(5)
®
(
(7)
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
10
Integrated Silicon Solution, Inc. — www.issi.com —
PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CSCS
RAS RAS
CS
RAS
CSCS
RAS RAS
Read with auto H × × × × DESL Continue burst to end Precharging
Precharge L H H H x NOP Continue burst to end Precharging
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write with Auto H × × × × DESL Continue burst to end -Write
Precharge recovering with auto precharge
L H H H × NOP Continue burst to end -Write
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Precharging H × × × × DESL Nop Enter idle after tRP
L H H H × NOP Nop Enter idle after tRP
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL Nop Enter idle after tRP
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Row Activating H × × × × DESL Nop Enter bank active after tRCD
L H H H × NOP Nop Enter bank active after tRCD
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
CASCAS
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(2)
(2)
(2)
(2)
recoveringwith auto precharge
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2,8)
(2)
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
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PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
11
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
CSCS
RAS RAS
CASCAS
CS
RAS
CSCS
RAS RAS
Write Recovering H × × × × DESL Nop Enter row active after tDPL
L H H H × NOP Nop Enter row active after tDPL
L H H L × BST Nop Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Begin read
L H L L BA, CA, A10 WRIT/ WRITA Begin new write
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Write Recovering H × × × × DESL Nop Enter precharge after tDPL
with Auto L H H H × NOP Nop Enter precharge after tDPL
Precharge L H H L × BST Nop Enter row active after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × R EF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Refresh H × × × × DESL Enter idle after tRC1
L H H H × NOP Nop Enter idle after tRC1
L H H L × BST Nop Enter idle after tRC1
L H L H BA, CA, A10 EAD/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
Mode Register H × × × × DESL Nop Enter idle after tRSC
Accessing L H H H × NOP Nop Enter idle after tRSC
L H H L × BST Nop Enter idle after tRSC
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF ILLEGAL
L L L L OC, BA MRS/EMRS ILLEGAL
WE WE
CAS
WE Address Command Action
CASCAS
WE WE
(6)
(2)
(2)
(2, 6)
(2)
(2)
®
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
12
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PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
FUNCTIONAL TRUTH TABLE Continued:
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
3. Illegal if tRCD is not satisfied.
4. Illegal if tRAS is not satisfied.
5. Must satisfy burst interrupt condition.
6. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
7. Must mask preceding data which don’t satisfy tDPL.
8. Illegal if tRRD is not satisfied.
®
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PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
13
IS42S81600A, IS42S16800A, IS42S32400A
STATE DIAGRAM
Extended
Mode
Register
Set
SELF
Mode
Register
Set
EMRS
MRS
IDLE
SELF exit
REF
®
ISSI
Self
Refresh
CBR (Auto)
Refresh
WRITE
SUSPEND
WRITEA
SUSPEND
CKE
CKE
CKE
Write
Deep
Power
Down
WRITE
WRITEA
DPD
DPD Exit
BST
Write
Write with
RRE (Precharge term
ACT
Row
Active
Auto Precharge
Read
Auto Precharge
Write
ination)
CKE
CKE
CKE
CKE
BST
Read
Read with
READ
READA
PRE (Precharge termination)
Power
Down
Active
Power
Down
Read
CKE
CKECKE
CKE
CKE
READ
SUSPEND
READA
SUSPEND
14
POWER
ON
Precharge
Precharge
Automatic sequence
Manual Input
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PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VDD MAX Maximum Supply Voltage –0.5 to +4.6 V
VDDQ
MAX Maximum Supply Voltage for Output Buffer 0.5 to +4.6 V
VIN Input Voltage –0.5 to +4.6 V
VOUT Output Voltage –0.5 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature Com. 0 to +70 ° C
Ind. –40 to +85
TSTG Storage Temperature –55 to +125 °C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. All voltages are referenced to Vss.
DC RECOMMENDED OPERATING CONDITIONS
(2)
(At TA = 0 to +70°C)
Symbol Parameter Min. Typ. Max. Unit
VDD Supply Voltage 3.0 3.3 3.6 V
VDDQ I/O Supply Voltage 3.0 3.3 3.6 V
(1)
VIH
(2)
VIL
Note:
IH (max) = VDDQ +1.5V (PULSE WIDTH < 5NS).
1. V
2. VIL (min) = -1.5V (PULSE WIDTH < 5NS).
Input High Voltage 2.0 — VDDQ + 0.3 V
Input Low Voltage -0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS (At TA = 0 to +25°C, VDD = VDDQ= 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter Typ. Max. Unit
CIN1 Input Capacitance: CLK — 3.5 pF
CIN2 Input Capacitance:All other input pins — 3.8 pF
CI/O Data Input/Output Capacitance:I/Os — 6.5 pF
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PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
15
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
I
IL Input Leakage Current 0V ≤ VIN ≤ VCC, with pins other than –5 5 µA
the tested pin at 0V
IOL Output Leakage Current Output is disabled, 0V ≤ VOUT ≤ VCC –5 5 µA
VOH Output High Voltage Level IOUT = –2 mA 2. 4 — V
VOL Output Low Voltage Level IOUT = +2 mA — 0. 4 V
®
IDD1 Operating Current
IDD2P Precharge Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN)——3mA
IDD2PS (In Power-Down Mode) tCK = ∞ ——2mA
IDD2N Precharge Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN)——25mA
IDD2NS (In Non Power-Down Mode) tCK = ∞ ——15mA
IDD3P Active Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN)——10mA
IDD3PS (In Power-Down Mode) tCK = ∞ ——10mA
IDD3N Active Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN) Com. — — 35 mA
IDD3NS (In Non Power-Down Mode) tCK = ∞ Com. — — 30 mA
IDD4 Operating Current tCK = tCK (MIN) Com. -7 — 150 mA
(In Burst Mode)
IDD5 Auto-Refresh Current tRC = tRC (MIN) Com. -7 — 300 mA
IDD6 Self-Refresh Current CKE ≤ 0.2V Com. — — 2 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
DD1 and IDD4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
2. I
(1,2)
(1)
One Bank Operation, Com. -6 — 170 mA
Com. -7 — 160 mA
Burst Length=1 Ind. -7 — 170 m A
tRC ≥ tRC (min.) Com. -10 — 140 mA
IOUT = 0mA Ind. -10 — 150 m A
Ind. — — 45 mA
Ind. — — 35 mA
Com. -6 — 165 mA
IOUT = 0mA Ind. -7 — 160 mA
Com. -10 — 140 mA
Ind. -10 — 150 mA
Com. -6 — 330 mA
Ind. -7 — 330 mA
Com. -10 — 270 mA
Ind. -10 — 300 mA
Ind. — — 3 mA
DD and Vss for each memory
16
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PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
®
ISSI
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6 -7 -10
Symbol Parameter Min. Max. Min. Max. Min. Max Units
CK3 Clock Cycle Time CAS Latency = 3 6 — 7 — 1 0 — n s
t
tCK2 CAS Latency = 2 — — 10 — 10 — ns
t
AC3 Access Time From CLK
(4)
CAS Latency = 3 — 5.4 — 5.4 — 7 ns
tAC2 CAS Latency = 2 — — — 6 — 9 ns
tCHI CLK HIGH Level Width 2.5 — 2.5 — 3.5 — n s
tCL CLK LOW Level Width 2.5 — 2.5 — 3.5 — ns
OH3 Output Data Hold Time CAS Latency = 3 2.5 — 2.5 — 2.5 — ns
t
tOH2 CAS Latency = 2 2.5 — 2.5 — 2.5 — ns
tLZ Output LOW Impedance Time 0 — 0 — 0 — ns
HZ3 Output HIGH Impedance Time
t
(5)
CAS Latency = 3 — 6 — 6 — 7 ns
tHZ2 CAS Latency = 2 — 6 — 6 — 9 n s
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
(2,3)
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
1CLK+3
—
1CLK+3
—
1CLK+3
—ns
1.5 — 1.5 — 2.0 — n s
0.8 — 0.8 — 1 — ns
tDS Input Data Setup Time
tDH Input Data Hold Time
tAS Address Setup Time
tAH Address Hold Time
tCKS CKE Setup Time
tCKH CKE Hold Time
tCKA CKE to CLK Recovery Delay Time
tCS Command Setup Time (CS, RAS, CAS, WE, DQM)
tCH Command Hold Time (CS, RAS, CAS, WE, DQM)
tRC Command Period (REF to REF / ACT to ACT) 60 — 63 — 70 — n s
tRAS Command Period (ACT to PRE) 37
120,000
37
120,000
44
120,000
tRP Command Period (PRE to ACT) 18 — 18 — 20 — n s
tRCD Active Command To Read / Write Command Delay Time 1 8 — 18 — 20 — n s
tRRD Command Period (ACT [0] to ACT[1]) 12 — 14 — 15 — n s
tDPL3 Input Data To Precharge CAS Latency = 3 2CLK — 2CLK — 2CLK — ns
Command Delay time
tDPL2 CAS Latency = 2 2CLK — 2CLK — 2CLK — ns
tDAL3 Input Data To Active / Refresh CAS Latency = 3
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
Command Delay time (During Auto-Precharge)
tDAL2 CAS Latency = 2
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
tT Transition Time 0.5 30 0.5 30 0.5 30 ns
tREF Refresh Cycle Time (4096) — 64 — 64 — 64 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after V
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
3. Assumed input rise and fall time (t
considered and (t
4. Access time is measured at 1.5V with the load shown in the figure below.
5. The time t
when the output is in the high impedance state.
T = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
R & tF) = 1ns. If tR and tF are longer than 1ns, transient time compensation should be
R + tF) / 2-1 ns should be added to the parameter.
HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
DD and VDDQ reach their stipulated voltages.
ns
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PRELIMINARY INFORMATION Rev. 00C
01/20/05
1-800-379-4774
17
IS42S81600A, IS42S16800A, IS42S32400A
ISSI
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER - 6 -7 -10. UNITS
— Clock Cycle Time 6 7 1 0 ns
— Operating Frequency 166 143 100 MHz
tCCD READ/WRITE command to READ/WRITE command 1 1 1 cycle
tCKED CKE to clock disable or power-down entry mode 1 1 1 cycle
tPED CKE to clock enable or power-down exit setup mode 1 1 1 cycle
tDQD DQM to input data delay 0 0 0 cycle
tDQM DQM to data mask during WRITEs 0 0 0 cycle
tDQZ DQM to data high-impedance during READs 2 2 2 cycle
tDWD WRITE command to input data delay 0 0 0 cycle
tDAL Data-in to ACTIVE command 5 4 4 cycle
tDPL Data-in to PRECHARGE command 2 2 2 cycle
tBDL Last data-in to burst STOP command 1 1 1 cycle
®
tCDL Last data-in to new READ/WRITE command 1 1 1 cycle
tRDL Last data-in to PRECHARGE command 2 2 2 cycle
tMRD LOAD MODE REGISTER command 2 2 2 cycle
to ACTIVE or REFRESH command
tROH Data-out to high-impedance from CL = 3 3 3 3 cycle
PRECHARGE command CL = 2 2 2 2
18
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PRELIMINARY INFORMATION Rev. 00C
1-800-379-4774
01/20/05
IS42S81600A, IS42S16800A, IS42S32400A
AC TEST CONDITIONS
Input Load Output Load
t
CK
CLK
INPUT
3.0V
1.5V
0V
3.0V
1.5V
0V
t
t
OH
CS
CHI
t
t
CH
t
AC
t
CL
Output
Z
= 50Ω
®
ISSI
1.5V
50Ω
30 pF
OUTPUT
1.5V 1.5V
AC TEST CONDITIONS
Parameter Unit
AC High Level Input Voltage/Low Level Input Voltage 3.0V to 0V
Input Rise and Fall Times 1 ns
Input Timing Reference Level 1.5V
Output Timing Measurement Reference Level 1.5V
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01/20/05
1-800-379-4774
19
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