ISSI IS42S16400-7TI, IS42S16400-7T, IS42S16400-10TI, IS42S16400-10T, IS42S16400-6T Datasheet

IS42S16400 ISSI

VCC

I/O0

VCCQ

I/O1
I/O2

GNDQ

I/O3
I/O4

VCCQ

I/O5
I/O6

GNDQ

I/O7

VCC

LDQM

WE
CAS
RAS

CS

BA0
BA1

A10

A0
A1
A2
A3

VCC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND

®

1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM

FEATURES

• Clock frequency: 166, 133, 100 MHz

• Fully synchronous; all signals referenced to a
positive clock edge

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length
– (1, 2, 4, 8, full page)

• Programmable burst sequence:
Sequential/Interleave

• Self refresh modes

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write
operations capability

OVERVIEW

ISSI

's 64Mb Synchronous DRAM IS42S16400 is organized
as 1,048,576 bits x 16-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.

PIN CONFIGURATIONS

54-Pin TSOP (Type II)

FINAL PRODUCTION

MAY 2001

• Burst termination by burst stop and precharge
command

• Byte controlled by LDQM and UDQM

• Industrial temperature availability

• Package:

PIN DESCRIPTIONS

A0-A11 Address Input
BA0, BA1 Bank Select Address
I/O0 to I/O15 Data I/O
CLK System Clock Input
CKE Clock Enable

CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command

This document contains TARGET SPECIFICATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

TARGET SPECIFICATION Rev. C

05/04/01

400-mil 54-pin TSOP II

WE Write Enable
LDQM Lower Bye, Input/Output Mask
UDQM Upper Bye, Input/Output Mask
Vcc Power
GND Ground
VccQ Power Supply for I/O Pin
GNDQ Ground for I/O Pin
NC No Connection

1

IS42S16400 ISSI

GENERAL DESCRIPTION

The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.

The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.

The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.

A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE

function enabled.
of the other three banks will hide the

Precharge

one bank while accessing one

precharge

cycles and

provide seamless, high-speed, random-access operation.
SDRAM

read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The READ or
WRITE commands in conjunction with address bits reg­istered are used to select the starting column location for
the burst access.

Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.

®

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

CS

RAS

CAS

WE

A11

A10

A9
A8
A7
A6
A5
A4
A3
A2
A1

A0
BA0
BA1

COMMAND

DECODER

&

CLOCK

GENERATOR

ADDRESS

LATCH

11

ROW

ADDRESS LATCH

8

BURST COUNTER

ADDRESS BUFFER

MODE

REGISTER

11

COLUMN

COLUMN

MULTIPLEXER

REFRESH

CONTROLLER

SELF

REFRESH

CONTROLLER

REFRESH

COUNTER

ROW

ADDRESS

BUFFER

11

11

ROW DECODER

BANK CONTROL LOGIC

DATA IN

BUFFER

16

DATA OUT

BUFFER

16 16

4096

4096

4096

4096

MEMORY CELL

SENSE AMP I/O GATE

256K
(x 16)

COLUMN DECODER

8

16

ARRAY

BANK 0

DQM

I/O 0-15

Vcc/Vcc

Q

GND/GNDQ

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

TARGET SPECIFICATION Rev. C

05/04/01

IS42S16400 ISSI

PIN FUNCTIONS

Symbol Pin No. Type Function (In Detail)

®

A0-A11

BA0, BA1 20, 21 Input Pin

CAS

CKE

CLK

CS

I/O0 to

I/O15

LDQM,

UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is

23 to 26 Input Pin
29 to 34

22, 35

17 Input Pin

37 Input Pin

38 Input Pin

19 Input Pin

2, 4, 5, 7, 8, 10, I/O Pin
11,13, 42, 44, 45,
47, 48, 50, 51, 53

15, 39 Input Pin

Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (A0-A7
with A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.

Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.

CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.

The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode.

CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.

The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.

I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.

LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The
outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This
function corresponds to OE in conventional DRAMs. In write mode, LDQM and
UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When LDQM or
UDQM is HIGH, input data is masked and cannot be written to the device.

CKE is an asynchronous i

nput.

RAS

WE

VCCQ

VCC

GNDQ

GND

18 Input Pin

16 Input Pin

3, 9, 43, 49 Power Supply Pin

1, 14, 27 Power Supply Pin

6, 12, 46, 52 Power Supply Pin

28, 41, 54 Power Supply Pin

RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.

WE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.

VCCQ is the output buffer power supply.
VCC is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.

Integrated Silicon Solution, Inc. — 1-800-379-4774

TARGET SPECIFICATION Rev. C

05/04/01

3

IS42S16400 ISSI

®

FUNCTION (In Detail)

A0-A11 are address inputs sampled during the ACTIVE
(row-address A0-A11)
with A10 defining auto PRECHARGE)
a PRECHARGE command to determine if all banks are to
be PRECHARGED
BA1

(LOW)

. The address inputs also provide the op-code

during a LOAD MODE REGISTER command.
Bank Select Address

ACTIVE, READ, WRITE or PRECHARGE command is
being applied.

CAS, in conjunction with the RAS and WE, forms the
device command. See the “Command Truth Table” for
details on device commands.

The CKE input determines whether the CLK input is
enabled. The next rising edge of the CLK signal will be
valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down
mode, CLOCK SUSPEND mode, or SELF-REFRESH
mode. CKE is an asynchronous input.

CLK is the master clock input for this device. Except for
CKE, all inputs to this device are acquired in synchroni­zation with the rising edge of this pin.

The CS input determines whether command input is
enabled within the device. Command input is enabled
when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH. I/
O0 to I/O15 are I/O pins. I/O through these pins can be
controlled in byte units using the LDQM and UDQM pins.

LDQM and UDQM control the lower and upper bytes of the
I/O buffers. In read mode, LDQM and UDQM control the
output buffer. When LDQM or UDQM is LOW, the corre­sponding buffer byte is enabled, and when HIGH, dis­abled. The outputs go to the HIGH Impedance State when
LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM
control the input buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.

RAS, in conjunction with CAS and WE , forms the device
command. See the “Command Truth Table” item for
details on device commands.

WE , in conjunction with RAS and CAS , forms the device
command. See the “Command Truth Table” item for
details on device commands.

VCCQ is the output buffer power supply.
VCC is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.

and READ/WRITE command

. A10 is sampled during

(A10 HIGH)

(BA0 and BA1)

or bank selected by BA0,

defines which bank the

(A0-A7

READ

The READ command selects the bank from BA0, BA1
inputs and starts a burst read access to an active row.
Inputs A0-A7 provides the starting column location. When
A10 is HIGH, this command functions as an AUTO
PRECHARGE command. When the auto precharge is
selected, the row being accessed will be precharged at
the end of the READ burst. The row will remain open for
subsequent accesses when AUTO PRECHARGE is not
selected. DQ’s read data is subject to the logic level on
the DQM inputs two clocks earlier. When a given DQM
signal was registered HIGH, the corresponding DQ’s will
be High-Z two clocks later. DQ’s will provide valid data
when the DQM signal was registered LOW.

WRITE

A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank, and
the starting column location is provided by inputs A0-A7.
Whether or not AUTO-PRECHARGE is used is deter­mined by A10.

The row being accessed will be precharged at the end of
the WRITE burst, if AUTO PRECHARGE is selected. If
AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.

A memory array is written with corresponding input data
on DQ’s and DQM input logic level appearing at the same
time. Data will be written to memory when DQM signal is
LOW. When DQM is HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that
byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
BA0, BA1 can be used to select which bank is precharged
or they are treated as “Don’t Care”. A10 determined
whether one or all banks are precharged. After executing
this command, the next command for the selected banks(s)
is executed after passage of the period tRP, which is the
period required for bank precharging. Once a bank has
been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being
issued to that bank.

AUTO PRECHARGE

The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst. This function allows for individual-bank precharge
without requiring an explicit command. A10 to enables the
AUTO PRECHARGE function in conjunction with a spe­cific READ or WRITE command. For each individual
READ or WRITE command, auto precharge is either

4

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TARGET SPECIFICATION Rev. C

05/04/01

IS42S16400 ISSI

®

enabled or disabled. AUTO PRECHARGE does not apply
except in full-page burst mode. Upon completion of the
READ or WRITE burst, a precharge of the bank/row that
is addressed is automatically performed.

AUTO REFRESH COMMAND

This command executes the AUTO REFRESH operation.
The row address and bank to be refreshed are automatically
generated during this operation. The stipulated period (tRC)
is required for a single refresh operation, and no other
commands can be executed during this period. This com­mand is executed at least 4096 times every 64ms. During
an AUTO REFRESH command, address bits are “Don’t
Care”. This command corresponds to CBR Auto-refresh.

SELF REFRESH

During the SELF REFRESH operation, the row address to
be refreshed, the bank, and the refresh interval are
generated automatically internally. SELF REFRESH can
be used to retain data in the SDRAM without external
clocking, even if the rest of the system is powered down.
The SELF REFRESH operation is started by dropping the
CKE pin from HIGH to LOW. During the SELF REFRESH
operation all other inputs to the SDRAM become “Don’t
Care”.The device must remain in self refresh mode for a
minimum period equal to tRAS or may remain in self refresh
mode for an indefinite period beyond that.The SELF­REFRESH operation continues as long as the CKE pin
remains LOW and there is no need for external control of
any other pins.The next command cannot be executed
until the device internal recovery period (tRC) has elapsed.
Once CKE goes HIGH, the NOP command must be
issued
completion of any internal refresh in progress. After the
self-refresh, since it is impossible to determine the ad­dress of the last row to be refreshed, an AUTO-REFRESH
should immediately be performed for all addresses.

(minimum of two clocks)

to provide time for the

BURST TERMINATE

The BURST TERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registered READ or WRITE command prior to the BURST
TERMINATE.

COMMAND INHIBIT

COMMAND INHIBIT prevents new commands from being
executed. Operations in progress are not affected, apart
from whether the CLK signal is enabled

NO OPERATION

When CS is low, the NOP command prevents unwanted
commands from being registered during idle or wait
states.

LOAD MODE REGISTER

During the LOAD MODE REGSITER command the mode
register is loaded from A0-A11. This command can only
be issued when all banks are idle.

ACTIVE COMMAND

When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputs on A0-A11 selects the row. Until a PRECHARGE
command is issued to the bank, the row remains open for
accesses.

Integrated Silicon Solution, Inc. — 1-800-379-4774

TARGET SPECIFICATION Rev. C

05/04/01

5

IS42S16400 ISSI

®

TRUTH TABLE – COMMANDS AND DQM OPERATION

(1)

FUNCTION CS RAS CAS WE DQM ADDR DQs

COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (Select bank and activate row)
READ (Select bank/column, start READ burst)
WRITE (Select bank/column, start WRITE burst)

(3)

(4)

L L H H X Bank/Row X
LHLHL/H

(4)

LHLLL/H

(8)

(8)

Bank/Col X
Bank/Col Valid

BURST TERMINATE L H H L X X Active

(6,7)

(5)

L L H L X Code X
LLLHXXX

PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH

(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z

NOTES:

1. CKE is HIGH for all commands except SELF REFRESH.

2. A0-A11 define the op-code written to the mode register.

3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
auto precharge; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”

6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

(2)

(8)

(8)

L L L L X Op-Code X

———— L — Active
———— H — High-Z

6

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TARGET SPECIFICATION Rev. C

05/04/01

IS42S16400 ISSI

®

TRUTH TABLE – CKE

(1-4)

CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn

Power-Down X Maintain Power-Down L L
Self Refresh X Maintain Self Refresh L L
Clock Suspend X Maintain Clock Suspend L L
Power-Down
Self Refresh
Clock Suspend

(5)

(6)

(7)

COMMAND INHIBIT or NOP Exit Power-Down L H
COMMAND INHIBIT or NOP Exit Self Refresh L H

X Exit Clock Suspend L H
All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry H L
All Banks Idle AUTO REFRESH Self Refresh Entry H L
Reading or Writing VALID Clock Suspend Entry H L

See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK nHH

NOTES:

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge

3. COMMANDn is the command registered at clock edge

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge

6. Exiting self refresh at clock edge
should be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period.

7. After exiting clock suspend at clock edge

n

will put the device in the all banks idle state in time for clock edge

n

will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands

n

, the device will resume operation and recognize the next command at clock edge

n

, and ACTONn is a result of COMMANDn.

n

.

n+1

(provided that t

CKS

is met)

.

n+1

.

TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK

CURRENT STATE
Any COMMAND INHIBIT

COMMAND (ACTION) CS RAS CAS WE

(NOP/Continue previous operation)

NO OPERATION

(NOP/Continue previous operation)

n

(1-6)

HX XX

LH HH

Idle ACTIVE (Select and activate row) L L H H

(11)

(7)

(7)

LL LH
LL LL
LL HL

(10)

(10)

(8)

(10)

(10)

(8)

(9)

(10)

(10)

(8)

(9)

LH LH
LH LL
LL HL
LH LH
LH LL
LL HL
LH HL
LH LH
LH LL
LL HL
LH HL

AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE

Row Active READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)
Read READ (Select column and start new READ burst)
(Auto WRITE (Select column and start WRITE burst)
Precharge PRECHARGE (Truncate READ burst, start PRECHARGE)
Disabled) BURST TERMINATE
Write READ (Select column and start READ burst)
(Auto WRITE (Select column and start new WRITE burst)
Precharge PRECHARGE (Truncate WRITE burst, start PRECHARGE)
Disabled) BURST TERMINATE

Integrated Silicon Solution, Inc. — 1-800-379-4774

TARGET SPECIFICATION Rev. C

05/04/01

7

IS42S16400 ISSI

®

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t

XSR has been met (if the

previous state was SELF REFRESH).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Row Active: A row in the bank has been activated, and t

Idle: The bank has been precharged, and t

RP has been met.

RCD has been met. No data bursts/accesses and no register

accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to
the other bank are determined by its current state and CURRENT STATE BANK n truth tables.

Precharging: Starts with registration of a PRECHARGE command and ends when t

RP is met. Once tRP is met, the bank

will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when t

RCD is met. Once tRCD is met, the bank will

be in the row active state.

Read w/Auto

Precharge Enabled:

Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met.

RP is met, the bank will be in the idle state.

Once t

Write w/Auto

Precharge Enabled:

Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met.

RP is met, the bank will be in the idle state.

Once t

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when t

RC is met. Once tRC is met, the

SDRAM will be in the all banks idle state.

Accessing Mode

Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once

tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All:

Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all
banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs
or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

8

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TARGET SPECIFICATION Rev. C

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IS42S16400 ISSI

®

TRUTH TABLE – CURRENT STATE BANK

CURRENT STATE

COMMAND (ACTION) CS RAS CAS WE

n,

COMMAND TO BANK

m

(1-6)

Any COMMAND INHIBIT (NOP/Continue previous operation) H X X X

NO OPERATION (NOP/Continue previous operation) L H H H

Idle Any Command Otherwise Allowed to Bank

m

XX XX
Row ACTIVE (Select and activate row) L L H H
Activating, READ (Select column and start READ burst)
Active, or WRITE (Select column and start WRITE burst)

(7)

(7)

LH LH

LH LL
Precharging PRECHARGE L L H L
Read ACTIVE (Select and activate row) L L H H

(7,11)

(7,10)

LH LH

LH LL

LL HL

(Auto READ (Select column and start new READ burst)
Precharge WRITE (Select column and start WRITE burst)
Disabled) PRECHARGE

(9)

Write ACTIVE (Select and activate row) L L H H
(Auto READ (Select column and start READ burst)
Precharge WRITE (Select column and start new WRITE burst)
Disabled) PRECHARGE

(9)

(7,12)

(7,13)

LH LH

LH LL

LL HL
Read ACTIVE (Select and activate row) L L H H
(With Auto READ (Select column and start new READ burst)
Precharge) WRITE (Select column and start WRITE burst)

PRECHARGE

(9)

(7,8,14)

(7,8,15)

LH LH

LH LL

LL HL
Write ACTIVE (Select and activate row) L L H H
(With Auto READ (Select column and start READ burst)
Precharge) WRITE (Select column and start new WRITE burst)

PRECHARGE

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after t
state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank
are those allowed to be issued to bank
covered in the notes below.

3. Current state definitions:

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register

Read w/Auto

Precharge Enabled:

Write w/Auto

Precharge Enabled:

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

Idle: The bank has been precharged, and t

accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.

Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met.
Once tRP is met, the bank will be in the idle state.

Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been
met. Once tRP is met, the bank will be in the idle state.

(9)

m

(assuming that bank m is in such a state that the given command is allowable)

RP has been met.

(7,8,16)

(7,8,17)

LH LH
LH LL
LL HL

XSR has been met (if the previous

n

and the commands shown

. Exceptions are

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IS42S16400 ISSI

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter­rupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later (Consecutive READ Bursts).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after

WR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered

t
one clock prior to the READ to bank m (Fig CAP 3).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).

WR is met, where t WR begins when the WRITE

®

10

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IS42S16400 ISSI

®

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VCC MAX Maximum Supply Voltage –1.0 to +4.6 V
VCCQ

MAX Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V

VIN Input Voltage –1.0 to +4.6 V
VOUT Output Voltage –1.0 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature Com. 0 to +70 °C

Ind. –40 to +85

TSTG Storage Temperature –55 to +150 °C

DC RECOMMENDED OPERATING CONDITIONS

(2)

(At TA = 0 to +70°C)

Symbol Parameter Min. Typ. Max. Unit

VCC, VCCQ Supply Voltage 3.0 3.3 3.6 V

VIH Input High Voltage 2.0 — VCC + 0.3 V
VIL Input Low Voltage -0.3 — +0.8 V

CAPACITANCE CHARACTERISTICS

(1,2)

(At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)

Symbol Parameter Typ. Max. Unit

CIN1 Input Capacitance: A0-A11, BA0, BA1 — 4pF
CIN2 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) — 4pF
CI/O Data Input/Output Capacitance: I/O0-I/O15 — 5pF

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

2. All voltages are referenced to GND.

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®

IS42S16400 ISSI

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current 0V ≤ VIN ≤ VCC, with pins other than –55µA

the tested pin at 0V

IOL Output Leakage Current Output is disabled, 0V ≤ VOUT ≤ VCC –55µA
VOH Output High Voltage Level IOUT = –2 mA 2.4 — V
VOL Output Low Voltage Level IOUT = +2 mA — 0.4 V

ICC1 Operating Current

ICC2P Precharge Standby Current CKE ≤ VIL (MAX)tCK = tCK ( MIN) Com. —— 3mA

ICC2PS (In Power-Down Mode) tCK = ∞ Com. —— 2mA

ICC2N Precharge Standby Current CKE ≥ VIH (MIN)tCK = tCK ( MIN) ——30 mA
ICC2NS (In Non Power-Down Mode) tCK = ∞ Com. ——10 mA

ICC3P Active Standby Current CKE ≤ VIL (MAX)tCK = tCK ( MIN) Com. —— 3mA

ICC3PS (In Power-Down Mode) tCK = ∞ Com. —— 3mA

ICC3N Active Standby Current CKE ≥ VIH (MIN)tCK = tCK ( MIN) ——40 mA
ICC3NS (In Non Power-Down Mode) tCK = ∞ Com. ——20 mA

ICC4 Operating Current tCK = tCK ( MIN) CAS latency = 3 -6 — 130 mA

(In Burst Mode)

ICC5 Auto-Refresh Current tRC = tRC ( MIN) CAS latency = 3 -6 — 150 mA

ICC6 Self-Refresh Current CKE ≤ 0.2V —— 1mA

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.

1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.

2. Icc

(1,2)

One Bank Operation, CAS latency = 3 -6 — 140 mA
Burst Length=1 Com. -7 — 125 mA
tRC ≥ tRC (min.) Ind. -7 — 145 mA
IOUT = 0mA Com. -10 — 110 mA

Ind. -10 — 125 mA

Ind. —— 4mA

Ind. —— 3mA

Ind. ——15 mA

Ind. Ind. —— 7mA

Ind. —— 5mA

Ind. ——25 mA

(1)

IOUT = 0mA Com. -7 — 100 mA

Ind. -7 — 120 mA

Com. -10 — 80 mA

Ind. -10 — 100 mA

CAS latency = 2 -6 — 130 mA

Com. -7 — 100 mA

Ind. -7 — 120 mA

Com. -10 — 80 mA

Ind. -10 — 100 mA

Com. -7 — 130 mA

Ind. -7 — 150 mA

Com. -10 — 110 mA

Ind. -10 — 130 mA

CAS latency = 2 -6 — 130 mA

Com. -7 — 100 mA

Ind. -7 — 120 mA

Com. -10 — 80 mA

Ind. -10 — 100 mA

12

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IS42S16400 ISSI

®

AC ELECTRICAL CHARACTERISTICS

(1,2,3)

-6 -7 -10

Symbol Parameter Min. Max. Min. Max. Min. Max Units

tCK3 Clock Cycle Time CAS Latency = 3 6 — 7 — 10 — ns
tCK2 CAS Latency = 2 8 — 10 — 10 — ns

tAC3 Access Time From CLK

(4)

CAS Latency = 3 — 5.5 — 6 — 7ns

tAC2 CAS Latency = 2 — 6 — 6 — 9ns
tCHI CLK HIGH Level Width 2 — 2.5 — 3.5 — ns
tCL CLK LOW Level Width 2 — 2.5 — 3.5 — ns
tOH3 Output Data Hold Time CAS Latency = 3 2.5 — 2.5 — 2.5 — ns

tOH2 CAS Latency = 2 2.5 — 2.5 — 2.5 — ns
tLZ Output LOW Impedance Time 0 — 0 — 0 — ns
tHZ3 Output HIGH Impedance Time

(5)

CAS Latency = 3 — 5.5 — 6 — 7ns

tHZ2 CAS Latency = 2 — 6 — 6 — 9ns
tDS Input Data Setup Time 1.5 — 1.5 — 2.0 — ns
tDH Input Data Hold Time 0.8 — 0.8 — 1 — ns
tAS Address Setup Time 1.5 — 1.5 — 2.0 — ns
tAH Address Hold Time 0.8 — 0.8 — 1 — ns
tCKS CKE Setup Time 1.5 — 1.5 — 2.0 — ns
tCKH CKE Hold Time 0.8 — 0.8 — 1 — ns
tCKA CKE to CLK Recovery Delay Time

1CLK+3

—

1CLK+3

—

1CLK+3

— ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 1.5 — 1.5 — 2.0 — ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 0.8 — 0.8 — 1 — ns
tRC Command Period (REF to REF / ACT to ACT) 60 — 63 — 70 — ns
tRAS Command Period (ACT to PRE) 35

120,000

37

120,000

44

120,000

ns
tRP Command Period (PRE to ACT) 15 — 15 — 18 — ns
tRCD Active Command To Read / Write Command Delay Time 15 — 15 — 18 — ns
tRRD Command Period (ACT [0] to ACT[1]) 14 — 14 — 15 — ns
tDPL3 Input Data To Precharge CAS Latency = 3 2CLK — 2CLK — 2CLK — ns

Command Delay time

tDPL2 CAS Latency = 2 2CLK — 2CLK — 2CLK — ns
tDAL3 Input Data To Active / Refresh CAS Latency = 3

2CLK+tRP

—

2CLK+tRP

—

2CLK+tRP

— ns

Command Delay time (During Auto-Precharge)

tDAL2 CAS Latency = 2

2CLK+tRP

—

2CLK+tRP

—

2CLK+tRP

— ns
tT Transition Time 1 10 1 10 1 10 ns
tREF Refresh Cycle Time (4096) — 64 — 64 — 64 ms

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vcc and Vcc
note that the power-on sequence must be executed before starting memory operation.

2. Measured with t

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
(max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time t
when the output is in the high impedance state.

T = 1 ns.

HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)

Q reach their stipulated voltages. Also

IH (min.) and VIL

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IS42S16400 ISSI

OPERATING FREQUENCY / LATENCY RELATIONSHIPS

SYMBOL PARAMETER -6 -7 -10. UNITS

— Clock Cycle Time 6 7 10 ns
— Operating Frequency 166 133 100 MHz

tCCD READ/WRITE command to READ/WRITE command 1 1 1 cycle
tCKED CKE to clock disable or power-down entry mode 1 1 1 cycle
tPED CKE to clock enable or power-down exit setup mode 1 1 1 cycle
tDQD DQM to input data delay 0 0 0 cycle
tDQM DQM to data mask during WRITEs 0 0 0 cycle
tDQZ DQM to data high-impedance during READs 2 2 2 cycle
tDWD WRITE command to input data delay 0 0 0 cycle
tDAL Data-in to ACTIVE command 5 5 4 cycle
tDPL Data-in to PRECHARGE command 2 2 2 cycle
tBDL Last data-in to burst STOP command 1 1 1 cycle

®

tCDL Last data-in to new READ/WRITE command 1 1 1 cycle
tRDL Last data-in to PRECHARGE command 2 2 2 cycle
tMRD LOAD MODE REGISTER command 2 2 2 cycle

to ACTIVE or REFRESH command

tROH Data-out to high-impedance from CL = 3 3 3 3

cycle

PRECHARGE command CL = 2 2 2 2

AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
Input Load Output Load

t

CK

t

CLK

INPUT

2.0V

1.4V

0.8V

2.0V

1.4V

CHI

t

t

CS

CH

t

CL

50 Ω

I/O

+1.4V

50 pF

OUTPUT

14

0.8V

t

t

OH

1.4V 1.4V

AC

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IS42S16400 ISSI

®

FUNCTIONAL DESCRIPTION

The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank
DRAMs which operate at 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed
select the row)
with the READ or WRITE command are used to select the
starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.

. The address bits

(BA0 and BA1 select the bank, A0-A11

(A0-A7)

registered coincident

Initialization

SDRAMs must be powered up and initialized in a
predefined manner.

The 64M SDRAM is initialized after the power is applied
to VCC and VCCQ (simultaneously) and the clock is stable.

A 100µs delay is required prior to issuing any command
other than a
INHIBIT or NOP may be applied during the 100us period
and continue should at least through the end of the period.

With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100µs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle idle state where two
performed. After the
the SRDRAM is then ready for mode register programming.

The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state.

COMMAND INHIBIT

AUTO REFRESH

or a

AUTO REFRESH

NOP

. The COMMAND

cycles must be

cycles are complete,

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IS42S16400 ISSI

®

REGISTER DEFINITION
Mode Register

The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS\ latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.

The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information

MODE REGISTER DEFINITION

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Reserved

(1)

until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3

specifies the type of burst

(sequential or interleaved)

, M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use.

The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements will result in unspecified operation.

Address Bus
Mode Register (Mx)

Burst Length

M2 M1 M0 M3=0 M3=1

0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved

Latency Mode

M6 M5 M4 CAS Latency

0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

Operating Mode

M8 M7 M6-M0 Mode

0 0 Defined Standard Operation
— — — All Other States Reserved

Write Burst Mode

M9 Mode

0 Programmed Burst Length
1 Single Location Access

Burst Type

M3 Type

0 Sequential
1 Interleaved

1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"

16

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®

Burst Length

Read and write accesses to the SDRAM are burst ori­ented, with the burst length being programmable, as
shown in MODE REGISTER DEFINITION. The burst
length determines the maximum number of column loca­tions that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary
burst lengths.

Reserved states should not be used, as unknown opera­tion or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A7 (x16) when the burst length is set to two; by A2-A7
(x16) when the burst length is set to four; and by A3-A7
(x16) when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in BURST DEFINITION table.

BURST DEFINITION

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

A0

200-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

4 0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7 Cn, Cn + 1, Cn + 2 Not Supported

Page Cn + 3, Cn + 4...

(y) (location 0-y) …Cn - 1,

Cn…

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