ISSI IS42S16100-10T, IS42S16100-7T, IS42S16100-6T, IS42S16100-8T Datasheet

Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. A

09/29/00

IS42S16100 ISSI

®

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.

FEATURES

• Clock frequency: 166, 143, 125, 100 MHz

• Fully synchronous; all signals referenced to a
positive clock edge

• Two banks can be operated simultaneously and
independently

• Dual internal bank controlled by A11 (bank select)

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length
– (1, 2, 4, 8, full page)

• Programmable burst sequence:
Sequential/Interleave

• Auto refresh, self refresh

• 4096 refresh cycles every 128 ms

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write
operations capability

• Burst termination by burst stop and precharge
command

• Byte controlled by LDQM and UDQM

• Package 400-mil 50-pin TSOP II

DESCRIPTION

ISSI

's 16Mb Synchronous DRAM IS42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.

512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM

SEPTEMBER 2000

PIN CONFIGURATIONS

50-Pin TSOP (Type II)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VCC

I/O0
I/O1

GNDQ

I/O2
I/O3

VCCQ

I/O4
I/O5

GNDQ

I/O6

I/O7
VCCQ
LDQM

WE
CAS
RAS

CS
A11
A10

A0
A1
A2
A3

VCC

GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND

PIN DESCRIPTIONS

A0-A11 Address Input
A0-A10 Row Address Input
A11 Bank Select Address
A0-A7 Column Address Input
I/O0 to I/O15 Data I/O
CLK System Clock Input
CKE Clock Enable

CS Chip Select
RAS Row Address Strobe Command

CAS Column Address Strobe Command
WE Write Enable

LDQM Lower Bye, Input/Output Mask
UDQM Upper Bye, Input/Output Mask
Vcc Power
GND Ground
VccQ Power Supply for I/O Pin
GNDQ Ground for I/O Pin
NC No Connection

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PIN FUNCTIONS

Pin No. Symbol Type Function (In Detail)

20 to 24 A0-A10 Input Pin A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32 command input and A0-A7 as column address inputs during read or write command

input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automati­cally after the burst access.
These signals become part of the OP CODE during mode register set command
input.

19 A11 Input Pin A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when

high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.

16 CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the

"Command Truth Table" item for details on device commands.

34 CKE Input Pin The CKE input determines whether the CLK input is enabled within the device.

When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode.

The CKE is an asynchronous i

nput.

35 CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this device

are acquired in synchronization with the rising edge of this pin.

18 CS Input Pin The CS input determines whether command input is enabled within the device.

Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.

2, 3, 5, 6, 8, 9, 11 I/O0 to I/O Pin I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units

12, 39, 40, 42, 43, I/O15 using the LDQM and UDQM pins.

45, 46, 48, 49

14, 36 LDQM, Input Pin LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read

UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,

the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre­sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.

17 RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the

"Command Truth Table" item for details on device commands.

15 WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the

"Command Truth Table" item for details on device commands.

7, 13, 38, 44 VCCQ Power Supply Pin VCCQ is the output buffer power supply.

1, 25 VCC Power Supply Pin VCC is the device internal power supply.

4, 10, 41, 47 GNDQ Power Supply Pin GNDQ is the output buffer ground.

26, 50 GND Power Supply Pin GND is the device internal ground.

IS42S16100 ISSI

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Rev. A

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FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

CS
RAS
CAS

WE
A11

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

A10

COMMAND

DECODER

&

CLOCK

GENERATOR

MODE

REGISTER

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

MULTIPLEXER

ROW

ADDRESS

BUFFER

ROW

ADDRESS

BUFFER

COLUMN

ADDRESS LATCH

BURST COUNTER

COLUMN

ADDRESS BUFFER

ROW DECODER ROW DECODER

MEMORY CELL

ARRAY

BANK 0

COLUMN DECODER

MEMORY CELL

ARRAY

BANK 1

DATA IN

BUFFER

DATA OUT

BUFFER

SENSE AMP I/O GATE

SENSE AMP I/O GATE

2048

2048

DQM

I/O 0-15

Vcc/VccQ
GND/GNDQ

11

11

11

11

8

11

11

8

16

16 16

16

256

256

S16BLK.eps

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09/29/00

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameters Rating Unit

VCC MAX Maximum Supply Voltage –1.0 to +4.6 V
VCCQ

MAX Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V

VIN Input Voltage –1.0 to +4.6 V
VOUT Output Voltage –1.0 to +4.6 V
PD MAX Allowable Power Dissipation 1 W
ICS Output Shorted Current 50 mA
TOPR Operating Temperature 0 to +70 °C
TSTG Storage Temperature –55 to +150 °C

DC RECOMMENDED OPERATING CONDITIONS

(2)

(At TA = 0 to +70°C)

Symbol Parameter Min. Typ. Max. Unit

VCC, VCCQ Supply Voltage 3.0 3.3 3.6 V

VIH Input High Voltage

(3)

2.0 — VDD + 0.3 V

VIL Input Low Voltage

(4)

-0.3 — +0.8 V

CAPACITANCE CHARACTERISTICS

(1,2)

(At TA = 0 to +25°C, Vcc = VccQ = 3.3 ± 0.3V, f = 1 MHz)

Symbol Parameter Typ. Max. Unit

CIN1 Input Capacitance: A0-A11 — 4pF
CIN2 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) — 4pF
CI/O Data Input/Output Capacitance: I/O0-I/O15 — 5pF

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

2. All voltages are referenced to GND.

3. V

IH (max) = VCCQ + 2.0V with a pulse width ≤ 3 ns.

4. V

IL (min) = GND – 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns.

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Rev. A

09/29/00

DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current 0V ≤ VIN ≤ VCC, with pins other than –55µA

the tested pin at 0V

I

OL Output Leakage Current Output is disabled –55µA

0V ≤ VOUT ≤ VCC
VOH Output High Voltage Level IOUT = –2 mA 2.4 — V
VOL Output Low Voltage Level IOUT = +2 mA — 0.4 V

I

CC1 Operating Current

(1,2)

One Bank Operation, CAS latency = 3 -6 — 190 mA

Burst Length=1 -7 — 160 mA

t

RC ≥ tRC (min.) -8 — 140 mA

IOUT = 0mA -10 — 120 mA
ICC2P Precharge Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN) —— 3mA

ICC2PS (In Power-Down Mode) tCK = ∞ —— 2mA
ICC2N Precharge Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN) ——30 mA

ICC2NS (In Non Power-Down Mode) tCK = ∞ —— 6mA
ICC3P Active Standby Current CKE ≤ VIL (MAX)tCK = tCK (MIN) —— 3mA

ICC3PS (In Power-Down Mode) tCK = ∞ —— 2mA
ICC3N Active Standby Current CKE ≥ VIH (MIN)tCK = tCK (MIN) ——40 mA

ICC3NS (In Non Power-Down Mode) tCK = ∞ ——15 mA
ICC4 Operating Current tCK = tCK (MIN) CAS latency = 3 -6 — 210 mA

(In Burst Mode)

(1)

IOUT = 0mA -7 — 180 mA

-8 — 160 mA

-10 — 140 mA

CAS latency = 2 -6 — 210 mA

-7 — 180 mA

-8 — 160 mA

-10 — 140 mA

ICC5 Auto-Refresh Current tRC = tRC (MIN) CAS latency = 3 -6 — 210 mA

-7 — 180 mA

-8 — 160 mA

-10 — 140 mA

CAS latency = 2 -6 — 210 mA

-7 — 180 mA

-8 — 160 mA

-10 — 140 mA

ICC6 Self-Refresh Current CKE ≤ 0.2V —— 1mA

Notes:

1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.

2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.

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AC CHARACTERISTICS

(1,2,3)

-6 -7

Symbol Parameter Min. Max. Min. Max. Units

tCK3 Clock Cycle Time CAS Latency = 3 6 — 7 — ns
tCK2 CAS Latency = 2 8 — 8.6 — ns

tAC3 Access Time From CLK

(4)

CAS Latency = 3 — 5.5 — 6ns

tAC2 CAS Latency = 2 — 6 — 6ns
tCHI CLK HIGH Level Width 2 — 2.5 — ns
tCL CLK LOW Level Width 2 — 2.5 — ns
tOH3 Output Data Hold Time CAS Latency = 3 2.5 — 2.5 — ns

tOH2 CAS Latency = 2 2.5 — 2.5 — ns
tLZ Output LOW Impedance Time 0 — 0 — ns
tHZ3 Output HIGH Impedance Time

(5)

CAS Latency = 3 — 5.5 — 6ns

tHZ2 CAS Latency = 2 — 6 — 6ns
tDS Input Data Setup Time 2 — 2 — ns
tDH Input Data Hold Time 1 — 1 — ns
tAS Address Setup Time 2 — 2 — ns
tAH Address Hold Time 1 — 1 — ns
tCKS CKE Setup Time 2 — 2 — ns
tCKH CKE Hold Time 1 — 1 — ns
tCKA CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 2 — 2 — ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 1 — 1 — ns
tRC Command Period (REF to REF / ACT to ACT) 60 — 63 — ns
tRAS Command Period (ACT to PRE) 42 100,000 42 100,000 ns
tRP Command Period (PRE to ACT) 18 — 20 — ns
tRCD Active Command To Read / Write Command Delay Time 16 — 16 — ns
tRRD Command Period (ACT [0] to ACT[1]) 12 — 14 — ns
tDPL3 Input Data To Precharge CAS Latency = 3 1CLK — 1CLK — ns

Command Delay time

tDPL2 CAS Latency = 2 1CLK — 1CLK — ns
tDAL3 Input Data To Active / Refresh CAS Latency = 3 1CLK+tRP — 1CLK+tRP — ns

Command Delay time (During Auto-Precharge)

tDAL2 CAS Latency = 2 1CLK+tRP — 1CLK+tRP — ns
tT Transition Time 1 10 1 10 ns
tREF Refresh Cycle Time (4096) — 128 — 128 ms

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.

2. Measured with t

T = 1 ns.

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL
(max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time t

HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)

when the output is in the high impedance state.

IS42S16100 ISSI

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Rev. A

09/29/00

AC CHARACTERISTICS

(1,2,3)

-8 -10

Symbol Parameter Min. Max. Min. Max. Units

tCK3 Clock Cycle Time CAS Latency = 3 8 — 10 — ns
tCK2 CAS Latency = 2 10 — 10 — ns

tAC3 Access Time From CLK

(4)

CAS Latency = 3 — 6 — 7ns

tAC2 CAS Latency = 2 — 7 — 9ns
tCHI CLK HIGH Level Width 3 — 3.5 — ns
tCL CLK LOW Level Width 3 — 3.5 — ns
tOH3 Output Data Hold Time CAS Latency = 3 2.5 — 2.5 — ns

tOH2 CAS Latency = 2 2.5 — 2.5 — ns
tLZ Output LOW Impedance Time 0 — 0 — ns
tHZ3 Output HIGH Impedance Time

(5)

CAS Latency = 3 — 6 — 7ns

tHZ2 CAS Latency = 2 — 7 — 9ns
tDS Input Data Setup Time 2.5 — 2.5 — ns
tDH Input Data Hold Time 1 — 1 — ns
tAS Address Setup Time 2.5 — 2.5 — ns
tAH Address Hold Time 1 — 1 — ns
tCKS CKE Setup Time 2.5 — 2.5 — ns
tCKH CKE Hold Time 1 — 1 — ns
tCKA CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM) 2.5 — 2.5 — ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM) 1 — 1 — ns
tRC Command Period (REF to REF / ACT to ACT) 68 — 70 — ns
tRAS Command Period (ACT to PRE) 48 100,000 50 100,000 ns
tRP Command Period (PRE to ACT) 20 — 20 — ns
tRCD Active Command To Read / Write Command Delay Time 20 — 20 — ns
tRRD Command Period (ACT [0] to ACT[1]) 16 — 20 — ns
tDPL3 Input Data To Precharge CAS Latency = 3 1CLK — 1CLK — ns

Command Delay time

tDPL2 CAS Latency = 2 1CLK — 1CLK — ns
tDAL3 Input Data To Active / Refresh CAS Latency = 3 1CLK+tRP — 1CLK+tRP — ns

Command Delay time (During Auto-Precharge)

tDAL2 CAS Latency = 2 1CLK+tRP — 1CLK+tRP — ns
tT Transition Time 1 10 1 10 ns
tREF Refresh Cycle Time — 128 — 128 ms

Notes:

1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.

2. Measured with t

T = 1 ns.

3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL
(max.).

4. Access time is measured at 1.4V with the load shown in the figure below.

5. The time t

HZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)

when the output is in the high impedance state.

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OPERATING FREQUENCY / LATENCY RELATIONSHIPS

SYMBOL PARAMETER -6 -7 -8. -10. UNITS

— Clock Cycle Time 6 7 8 10 ns
— Operating Frequency 166 143 125 100 MHz

tCAC CAS Latency 3 3 3 3 cycle
tRCD Active Command To Read/Write Command Delay Time 3 3 3 3 cycle
tRAC RAS Latency (tRCD + tCAC) 6 6 6 6 cycle
tRC Command Period (REF to REF / ACT to ACT) 9 9 9 9 cycle
tRAS Command Period (ACT to PRE) 6 6 6 6 cycle
tRP Command Period (PRE to ACT) 3 3 3 3 cycle
tRRD Command Period (ACT[0] to ACT [1]) 3 3 3 3 cycle
tCCD Column Command Delay Time 1 1 1 1 cycle

(READ, READA, WRIT, WRITA)
tDPL Input Data To Precharge Command Delay Time 1 1 1 1 cycle
tDAL Input Data To Active/Refresh Command Delay Time 4 4 4 4 cycle

(During Auto-Precharge)
tRBD Burst Stop Command To Output in HIGH-Z Delay Time 3 3 3 3 cycle

(Read)
tWBD Burst Stop Command To Input in Invalid Delay Time 0 0 0 0 cycle

(Write)
tRQL Precharge Command To Output in HIGH-Z Delay Time 3 3 3 3 cycle

(Read)
tWDL Precharge Command To Input in Invalid Delay Time 0 0 0 0 cycle

(Write)
tPQL Last Output To Auto-Precharge Start Time (Read) –2 –1 –2 –1 cycle
tQMD DQM To Output Delay Time (Read) 2 2 2 2 cycle
tDMD DQM To Input Delay Time (Write) 0 0 0 0 cycle
tMCD Mode Register Set To Command Delay Time 2 2 2 2 cycle

AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)

I/O

50 Ω

+1.4V

50 pF

Input

Output Load

2.0V

1.4V

0.8V

CLK

INPUT

OUTPUT

t

CHI

tCH

tAC

tOH

tCS

tCK

tCL

2.0V

1.4V

1.4V 1.4V

0.8V

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Rev. A

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COMMANDS

CLK

CKE

HIGH

ROW

ROW

BANK 1

BANK 0

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

HIGH

COLUMN

BANK 1

AUTO PRECHARGE

NO PRECHARGE

BANK 0

CS

RAS

CAS

WE

A0-A9

A10

A11

(1)

CLK

CKE

HIGH

COLUMN

AUTO PRECHARGE

BANK 1

BANK 0

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

HIGH

BANK 1

BANK 0 AND BANK 1

BANK 0 OR BANK 1NO PRECHARGE

BANK 0

CS

RAS

CAS

WE

A0-A9

A10

A11

(1)

Active Command Read Command

Write Command Precharge Command

Don't Care

Notes:

1. A8-A9 = Don't Care.

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CLK

CKE

HIGH

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

HIGH

CS

RAS

CAS

WE

A0-A9

A10

A11

No-Operation Command Device Deselect Command

Don't Care

COMMANDS (cont.)

Mode Register Set Command Auto-Refresh Command

CLK

CKE

HIGH

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

HIGH

CS

RAS

CAS

WE

A0-A9

A10

A11

OP-CODE

OP-CODE

OP-CODE

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COMMANDS (cont.)

Self-Refresh Command Power Down Command

Clock Suspend Command Burst Stop Command

Don't Care

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

ALL BANKS IDLE

NOP

NOP

NOP

NOP

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

CLK

CKE

CS

RAS

CAS

WE

A0-A9

A10

A11

BANK(S) ACTIVE

HIGH

NOP

NOP

NOP

NOP

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Mode Register Set Command

(CS, RAS, CAS, WE = LOW)
The IS42S16100 product incorporates a register that

defines the device operating mode. This command
functions as a data input pin that loads this register from
the pins A0 to A11. When power is first applied, the
stipulated power-on sequence should be executed and
then the IS42S16100 should be initialized by executing a
mode register set command.

Note that the mode register set command can be executed
only when both banks are in the idle state (i.e. deactivated).

Another command cannot be executed after a mode
register set command until after the passage of the period
tMCD, which is the period required for mode register set
command execution.

Active Command

(CS, RAS = LOW, CAS, WE= HIGH)
The IS42S16100 includes two banks of 4096 rows each.

This command selects one of the two banks according to
the A11 pin and activates the row selected by the pins A0
to A10.

This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.

Precharge Command

(CS, RAS, WE = LOW, CAS = HIGH)
This command starts precharging the bank selected by

pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the bank
selected by A11 is precharged. After executing this
command, the next command for the selected bank(s) is
executed after passage of the period tRP, which is the
period required for bank precharging.

This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs

Read Command

(CS, CAS = LOW, RAS, WE = HIGH)
This command selects the bank specified by the A11 pin

and starts a burst read operation at the start address
specified by pins A0 to A9. Data is output following CAS
latency.

The selected bank must be activated before executing this
command.

When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11
pin remains in the activated state after the burst read
completes.

Write Command

(CS, CAS, WE = LOW, RAS = HIGH)
When burst write mode has been selected with the mode

register set command, this command selects the bank
specified by the A11 pin and starts a burst write operation
at the start address specified by pins A0 to A9. This first
data must be input to the I/O pins in the cycle in which this
command.

The selected bank must be activated before executing this
command.

When A10 pin is HIGH, this command functions as a write
with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11 pin
remains in the activated state after the burst write
completes.

After the input of the last burst write data, the application
must wait for the write recovery period (tDPL, tDAL) to elapse
according to CAS latency.

Auto-Refresh Command

(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command executes the auto-refresh operation. The

row address and bank to be refreshed are automatically
generated during this operation.

Both banks must be placed in the idle state before executing
this command.

The stipulated period (tRC) is required for a single refresh
operation, and no other commands can be executed
during this period.

The device goes to the idle state after the internal refresh
operation completes.

This command must be executed at least 4096 times
every 128 ms.

This command corresponds to CBR auto-refresh in
conventional DRAMs.

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Rev. A

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Self-Refresh Command

(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. The

row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by dropping
the CKE pin from HIGH to LOW. The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The
self-refresh operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the device internal recovery period (tRC)
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addresses (4096 cycles).

Both banks must be placed in the idle state before
executing this command.

Burst Stop Command

(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write

operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.

No Operation

(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.

Device Deselect Command

(CS = HIGH)
This command does not select the device for an object of

operation. In other words, it performs no operation with
respect to the device.

Power-Down Command

(CKE = LOW)
When both banks are in the idle (inactive) state, or when

at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to the
absolute minimum. Power-down mode is started by
dropping the CKE pin from HIGH to LOW. Power-down
mode continues as long as the CKE pin is held low. All pins
other than the CKE pin are invalid and none of the other
commands can be executed in this mode. The power-down
operation is terminated by raising the CKE pin from LOW
to HIGH. The next command cannot be executed until the
recovery period (tCKA) has elapsed.

Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that power-down mode can be held is
just under the refresh cycle time.

Clock Suspend

(CKE = LOW)
This command can be used to stop the device internal

clock temporarily during a read or write cycle. Clock
suspend mode is started by dropping the CKE pin from
HIGH to LOW. Clock suspend mode continues as long as
the CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated by
raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tCKA) has elapsed.

Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.

IS42S16100 ISSI

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COMMAND TRUTH TABLE

(1,2)

CKE

Symbol Command n-1 n CS RAS CAS WE DQM A11 A10 A9-A0 I/On

MRS Mode Register Set

(3,4)

HXLLLLX OP CODE X

REF Auto-Refresh

(5)

H H L L L H X X X X HIGH-Z

SREF Self-Refresh

(5,6)

HLLLLHXX X XHIGH-Z
PRE Precharge Selected Bank H X L L H L X BS L X X
PALL Precharge Both Banks H X L L H L X X H X X
ACT Bank Activate

(7)

H X L L H H X BS Row Row X
WRIT Write H X L H L L X BS L Column

(18)

X

WRITA Write With Auto-Precharge

(8)

H X L H L L X BS H Column

(18)

X

READ Read

(8)

H X L H L H X BS L Column

(18)

X

READA Read With Auto-Precharge

(8)

H X L H L H X BS H Column

(18)

X

BST Burst Stop

(9)

HXLHHLXXXX X
NOP No Operation H X L H H H X X X X X
DESL Device Deselect H X H XXXXX X X X
SBY Clock Suspend / Standby Mode L XXXXXXX X X X
ENB Data Write / Output Enable H XXXXXLX X X Active
MASK Data Mask / Output Disable H XXXXXHX X X HIGH-Z

DQM TRUTH TABLE

(1,2)

CKE DQM

Symbol Command n-1 n UPPER LOWER

ENB Data Write / Output Enable H X L L
MASK Data Mask / Output Disable H X H H
ENBU Upper Byte Data Write / Output Enable H X L X
ENBL Lower Byte Data Write / Output Enable H X X L
MASKU Upper Byte Data Mask / Output Disable H X H X
MASKL Lower Byte Data Mask / Output Disable H X X H

CKE TRUTH TABLE

(1,2)

CKE

Symbol Command Current State n-1 n CS RAS CAS W E A11 A10 A9-A0

SPND Start Clock Suspend Mode Active H L XXXXXXX

— Clock Suspend Other States L L XXXXXXX
— Terminate Clock Suspend Mode Clock Suspend L H XXXXXXX

REF Auto-Refresh Idle H H L L L H X X X
SELF Start Self-Refresh Mode Idle H LLLLHXXX
SELFX Terminate Self-Refresh Mode Self-Refresh L H L H H H X X X

LHHXXXXXX

PDWN Start Power-Down Mode Idle H L L H H H X X X

HLHXXXXXX

— Terminate Power-Down Mode Power-Down L H XXXXXXX

IS42S16100 ISSI

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Rev. A

09/29/00

OPERATION COMMAND TABLE

(1,2)

Current State Command Operation CS RAS CAS WE A11 A10 A9-A0

Idle DESL No Operation or Power-Down

(12)

HXXXXXX

NOP No Operation or Power-Down

(12)

LHHHXXX
BST No Operation or Power-Down L H H L X X X
READ / READA Illegal L H L H V V V

(18)

WRIT/WRITA Illegal L H L L V V V

(18)

ACT Row Active L L H H V V V

(18)

PRE/PALL No Operation L L H L V V X
REF/SELF Auto-Refresh or Self-Refresh

(13)

LLLHXXX
MRS Mode Register Set LLLL OP CODE

Row Active DESL No Operation H XXXXXX

NOP No Operation L H H H X X X
BST No Operation L H H L X X X
READ/READA Read Start

(17)

LHLHVVV

(18)

WRIT/WRITA Write Start

(17)

LHLLVVV

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Precharge

(15)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Read DESL Burst Read Continues, Row Active When Done H XXXXXX

NOP Burst Read Continues, Row Active When Done L H H H X X X
BST Burst Interrupted, Row Active After Interrupt L H H L X X X
READ/READA Burst Interrupted, Read Restart After Interrupt

(16)

LHLHVVV

(18)

WRIT/WRITA Burst Interrupted Write Start After Interrupt

(11,16)

LHLLVVV

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Burst Read Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Write DESL Burst Write Continues, Write Recovery When Done H XXXXXX

NOP Burst Write Continues, Write Recovery When Done L H H H X X X
BST Burst Write Interrupted, Row Active After Interrupt L H H L X X X
READ/READA

Burst Write Interrupted, Read Start After Interrupt

(11,16)

LHLHVVV

(18)

WRIT/WRITA

Burst Write Interrupted, Write Restart After Interrupt

(16)

LHLLVVV

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Burst Write Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Read With DESL Burst Read Continues, Precharge When Done H XXXXXX
Auto- NOP Burst Read Continues, Precharge When Done L H H H X X X

Precharge BST Illegal L H H L X X X

READ/READA Illegal L H L H V V V

(18)

WRIT/WRITA Illegal L H L L V V V

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Illegal

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

IS42S16100 ISSI

®

16

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

09/29/00

OPERATION COMMAND TABLE

(1,2)

Current State Command Operation CS RAS CAS WE A11 A10 A9-A0

Write With DESL Burst Write Continues, Write Recovery And Precharge H XXXXXX
Auto-Precharge When Done

NOP Burst Write Continues, Write Recovery And Precharge L H H H X X X
BST Illegal L H H L X X X
READ/READA Illegal L H L H V V V

(18)

WRIT/WRITA Illegal L H L L V V V

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Illegal

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OPCODE

Row Precharge DESL No Operation, Idle State After tRP Has Elapsed H XXXXXX

NOP No Operation, Idle State After t

RP Has Elapsed L H H H X X X

BST No Operation, Idle State After t

RP Has Elapsed L H H L X X X

READ/READA Illegal

(10)

LHLHVVV

(18)

WRIT/WRITA Illegal

(10)

LHLLVVV

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL No Operation, Idle State After tRP Has Elapsed

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Immediately DESL No Operation, Row Active After tRCD Has Elapsed H XXXXXX
Following NOP No Operation, Row Active After tRCD Has Elapsed L H H H X X X

Row Active BST No Operation, Row Active After tRCD Has Elapsed L H H L X X X

READ/READA Illegal

(10)

LHLHVVV

(18)

WRIT/WRITA Illegal

(10)

LHLLVVV

(18)

ACT Illegal

(10,14)

LLHHVVV

(18)

PRE/PALL Illegal

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Write DESL No Operation, Row Active After tDPL Has Elapsed HXXXXXX
Recovery NOP No Operation, Row Active After tDPL Has Elapsed L H H H X X X

BST No Operation, Row Active After tDPL Has Elapsed L H H L X X X
READ/READA Read Start L H L H V V V

(18)

WRIT/WRITA Write Restart L H L L V V V

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Illegal

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

IS42S16100 ISSI

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Integrated Silicon Solution, Inc. — 1-800-379-4774

17

Rev. A

09/29/00

OPERATION COMMAND TABLE

(1,2)

Current State Command Operation CS RAS CAS WE A11 A10 A9-A0

Write Recovery DESL No Operation, Idle State After tDAL Has Elapsed H XXXXXX
With Auto- NOP No Operation, Idle State After tDAL Has Elapsed L H H H X X X

Precharge BST No Operation, Idle State After t

DAL Has Elapsed L H H L X X X

READ/READA Illegal

(10)

LHLHVVV

(18)

WRIT/WRITA Illegal

(10)

LHLLVVV

(18)

ACT Illegal

(10)

LLHHVVV

(18)

PRE/PALL Illegal

(10)

LLHLVVX
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Refresh DESL No Operation, Idle State After t

RP Has Elapsed HXXXXXX

NOP No Operation, Idle State After tRP Has Elapsed L H H H X X X
BST No Operation, Idle State After t

RP Has Elapsed L H H L X X X

READ/READA Illegal L H L H V V V

(18)

WRIT/WRITA Illegal L H L L V V V

(18)

ACT Illegal L L H H V V V

(18)

PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Mode Register DESL No Operation, Idle State After tMCD Has Elapsed H XXXXXX
Set NOP No Operation, Idle State After tMCD Has Elapsed L H H H X X X

BST No Operation, Idle State After tMCD Has Elapsed L H H L X X X
READ/READA Illegal L H L H V V V

(18)

WRIT/WRITA Illegal L H L L V V V

(18)

ACT Illegal L L H H V V V

(18)

PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal LLLL OP CODE

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input

2. All input signals are latched on the rising edge of the CLK signal.

3. Both banks must be placed in the inactive (idle) state in advance.

4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.

5. The row address is generated automatically internally at this time. The I/O pin and the address pin data is ignored.

6. During a self-refresh operation, all pin data (states) other than CKE is ignored.

7. The selected bank must be placed in the inactive (idle) state in advance.

8. The selected bank must be placed in the active state in advance.

9. This command is valid only when the burst length set to full page.

10. This is possible depending on the state of the bank selected by the A11 pin.

11. Time to switch internal busses is required.

12. The IS42S16100 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.

13. The IS42S16100 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idle state.
Input pins other than CKE are ignored at this time.

14. Possible if t

RRD is satisfied.

15. Illegal if tRAS is not satisfied.

16. The conditions for burst interruption must be observed. Also note that the IS42S16100 will enter the precharged state
immediately after the burst operation completes if auto-precharge is selected.

17. Command input becomes possible after the period t

RCD has elapsed. Also note that the IS42S16100 will enter the

precharged state immediately after the burst operation completes if auto-precharge is selected.

18. A8,A9 = don't care.

IS42S16100 ISSI

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Rev. A

09/29/00

CKE RELATED COMMAND TRUTH TABLE

(1)

CKE

Current State Operation n-1 n CS RAS CAS W E A11 A10 A9-A0

Self-Refresh Undefined H XXXXXXXX

Self-Refresh Recovery

(2)

LHHXXXXXX

Self-Refresh Recovery

(2)

LHLHHXXXX

Illegal

(2)

LHLHLXXXX

Illegal

(2)

LHL LXXXXX

Self-Refresh LLXXXXXXX

Self-Refresh Recovery Idle State After tRC Has Elapsed H H H XXXXXX

Idle State After t

RC Has Elapsed H H L H H XXXX

Illegal H H L H L XXXX
Illegal H H L L XXXXX
Power-Down on the Next Cycle H L H XXXXXX
Power-Down on the Next Cycle H L L H H XXXX
Illegal H L L H L XXXX
Illegal H L L L XXXXX
Clock Suspend Termination on the Next Cycle

(2)

LHXXXXXXX

Clock Suspend L L XXXXXXX

Power-Down Undefined H XXXXXXXX

Power-Down Mode Termination, Idle After L H XXXXXXX
That Termination

(2)

Power-Down Mode L L XXXXXXX

Both Banks Idle No Operation H H H XXXXXX

See the Operation Command Table H H L H XXXXX
Bank Active Or Precharge H H L L H XXXX
Auto-Refresh H H L L L H X X X
Mode Register Set H H LLLL OP CODE
See the Operation Command Table H L H XXXXXX
See the Operation Command Table H L L H XXXXX
See the Operation Command Table H L L L H XXXX
Self-Refresh

(3)

HLLLLHXXX
See the Operation Command Table H LLLLL OP CODE
Power-Down Mode

(3)

LXXXXXXXX

Other States See the Operation Command Table H H XXXXXXX

Clock Suspend on the Next Cycle

(4)

HLXXXXXXX
Clock Suspend Termination on the Next Cycle L H XXXXXXX
Clock Suspend Termination on the Next Cycle L L XXXXXXX

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input

2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The
minimum setup time (t

CKA) required before all commands other than mode termination must be satisfied.

3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.

4. The input must be command defined in the operation command table.

IS42S16100 ISSI

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Integrated Silicon Solution, Inc. — 1-800-379-4774

19

Rev. A

09/29/00

TWO BANKS OPERATION COMMAND TRUTH TABLE

(1,2)

Previous State Next State

Operation CS RAS CAS WE A11 A10 A9-A0 BANK 0 BANK 1 BANK 0 BANK 1

DESL H XXXXXX Any Any Any Any
NOP L H H H X X X Any Any Any Any
BST L H H L X X X R/W/A I/A A I/A

I I/A I I/A
I/A R/W/A I/A A
I/A I I/A I

READ/READA L H L H H H CA

(3)

I/A R/W/A I/A RP

HHCA

(3)

R/W A A RP

HLCA

(3)

I/A R/W/A I/A R

HLCA

(3)

R/W A A R

LHCA

(3)

R/W/A I/A RP I/A

LHCA

(3)

A R/W RP A

LLCA

(3)

R/W/A I/A R I/A

LLCA

(3)

A R/W R A

WRIT/WRITA L H L L H H CA

(3)

I/A R/W/A I/A WP

HHCA

(3)

R/W A A WP

HLCA

(3)

I/A R/W/A I/A W

HLCA

(3)

R/W A A W

LHCA

(3)

R/W/A I/A WP I/A

LHCA

(3)

A R/W WP A

LLCA

(3)

R/W/A I/A W I/A

LLCA

(3)

A R/W W A

ACT L L H H H RA RA Any I Any A

L RA RA I Any A Any

PRE/PALL L L H L X H X R/W/A/I I/A I I

X H X I/A R/W/A/I I I
H L X I/A R/W/A/I I/A I
H L X R/W/A/I I/A R/W/A/I I
L L X R/W/A/I I/A I I/A

L L X I/A R/W/A/I I R/W/A/I
REF LLLHXXX II II
MRS LLLL OPCODE I I I I

Notes:

1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column
Address

2. The device state symbols are interpreted as follows:

I Idle (inactive state)
A Row Active State
RRead
W Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State

3. CA: A8,A9 = don't care.

IS42S16100 ISSI

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Integrated Silicon Solution, Inc. — 1-800-379-4774

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09/29/00

SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)

SELF

REFRESH

AUTO

REFRESH

IDLE

POWER

DOWN

ACTIVE
POWER

DOWN

IDLE

MODE

REGISTER

SET

READ

BANK

ACTIVE

WRITE

CLOCK

SUSPEND

READ WITH

AUTO

PRECHARGE

PRE-

CHARGE

POWER ON

WRITE WITH

AUTO

PRECHARGE

CLOCK

SUSPEND

Transition due to command input.

Automatic transition following the
completion of command execution.

MRS

SREF entry

SREF exit

REF

CKE_

CKE

ACT

CKE_

CKE

BST BST

READ

CKE_

CKE

READA

CKE_

CKE

READ

READA

READ

WRITA

WRIT

WRIT

CKE_

CKE

WRITA

CKE_

CKE

WRIT

WRITA

PRE

PRE

READA

PRE

PRE

POWER APPLIED

IS42S16100 ISSI

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Rev. A

09/29/00

Input Pin Field

A11, A10, A9, A8 Mode Options

A6, A5, A4 CAS Latency

A3 Burst Type

A2, A1, A0 Burst Length

Device Initialization At Power-On

(Power-On Sequence)
As is the case with conventional DRAMs, the IS42S16100

product must be initialized by executing a stipulated
power-on sequence after power is applied.

After power is applied and VCC and VCCQ reach their
stipulated voltages, set and hold the CKE and DQM pins
HIGH for 100 µs. Then, execute the precharge command
to precharge both bank. Next, execute the auto-refresh
command twice or more and define the device operation
mode by executing a mode register set command.

The mode register set command can be also set before
auto-refresh command.

Mode Register Settings

The mode register set command sets the mode register.
When this command is executed, pins A0 to A9, A10, and
A11 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four fields as listed in the table below.

Note that the mode register set command can be executed
only when both banks are in the idle (inactive) state. Wait
at least two cycles after executing a mode register set
command before executing the next command.

CAS Latency

During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register set
command. The optimal CAS latency is determined by the
clock frequency and device speed grade (-10/12). See the
"Operating Frequency / Latency Relationships" item for
details on the relationship between the clock frequency
and the CAS latency. See the table on the next page for
details on setting the mode register.

Burst Length

When writing or reading, data can be input or output data
continuously. In these operations, an address is input only
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length field in
the mode register stipulates the number of data items
input or output in sequence. In the IS42S16100 product,
a burst length of 1, 2, 4, 8, or full page can be specified. See
the table on the next page for details on setting the mode
register.

Burst Type

The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
register set command. The IS42S16100 product supports
sequential mode and interleaved mode burst type settings.
See the table on the next page for details on setting the
mode register. See the "Burst Length and Column Address
Sequence" item for details on I/O data orders in these
modes.

Write Mode

Burst write or single write mode is selected by the OP code
(A11, A10, A9) of the mode register.

A burst write operation is enabled by setting the OP code
(A11, A10, A9) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specified by the column address and bank select address
at the write command set cycle.

A single write operation is enabled by setting OP code
(A11, A10, A9) to (1,0,0). In a single write operation, data
is only written to the column address and bank select
address specified by the write command set cycle without
regard to the bust length setting.

IS42S16100 ISSI

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09/29/00

MODE REGISTER

11109876543210

WRITE MODE LT MODE BT BL

M2 M1 M0 Sequential Interleaved

Burst Length 0 0 0 1 1

001 2 2
010 4 4
011 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved

M3 Type

Burst Type 0 Sequential

1 Interleaved

M6 M5 M4 CAS Latency

Latency Mode 0 0 0 Reserved

0 0 1 Reserved
010 2
011 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved

Address Bus
Mode Register (Mx)

M11 M10 M9 M8 M7 Write Mode

X X 0 0 0 Mode Register Set
X X 1 0 0 Burst Read & Single Write

00000 Reserved Test Set

IS42S16100 ISSI

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Integrated Silicon Solution, Inc. — 1-800-379-4774

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Rev. A

09/29/00

BURST LENGTH AND COLUMN ADDRESS SEQUENCE

Column Address Address Sequence

Burst Length A2 A1 A0 Sequential Interleaved

2 X X 0 0-1 0-1

X X 1 1-0 1-0

4 X 0 0 0-1-2-3 0-1-2-3

X 0 1 1-2-3-0 1-0-3-2
X 1 0 2-3-0-1 2-3-0-1
X 1 1 3-0-1-2 3-2-1-0

8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page n n n Cn, Cn+1, Cn+2 None

(256) Cn+3, Cn+4.....

...Cn-1(Cn+255),

Cn(Cn+256).....

Notes:

1. The burst length in full page mode is 256.

IS42S16100 ISSI

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Integrated Silicon Solution, Inc. — 1-800-379-4774

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09/29/00

BANK SELECT AND PRECHARGE ADDRESS ALLOCATION

Row X0 — Row Address

X1 — Row Address
X2 — Row Address
X3 — Row Address
X4 — Row Address
X5 — Row Address
X6 — Row Address
X7 — Row Address

X8 — Row Address
X9 — Row Address

X10 0 Precharge of the Selected Bank (Precharge Command) Row Address

1 Precharge of Both Banks (Precharge Command) (Active Command)

X11 0 Bank 0 Selected (Precharge and Active Command)

1 Bank 1 Selected (Precharge and Active Command)

Column Y0 — Column Address

Y1 — Column Address
Y2 — Column Address
Y3 — Column Address
Y4 — Column Address
Y5 — Column Address
Y6 — Column Address
Y7 — Column Address
Y8 — Don't Care
Y9 — Don't Care

Y10 0 Auto-Precharge - Disabled

1 Auto-Precharge - Enables

Y11 0 Bank 0 Selected (Read and Write Commands)

1 Bank 1 Selected (Read and Write Commands)