4400 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These
devices offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 2,048 or 4096
random accesses within a single row with access cycle
time as short as 20 ns per 4-bit word.
These features make the 4400 Series ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The 4400 Series is packaged in a 24-pin 300-mil SOJ with
JEDEC standard pinouts.
KEY TIMING PARAMETERS
Parameter-50-60Unit
RAS Access Time (tRAC)5060ns
CAS Access Time (tCAC)1315ns
Column Address Access Time (tAA)25 30 ns
EDO Page Mode Cycle Time (tPC)20 25 ns
Read/Write Cycle Time (tRC)84104ns
StandbyHHXXXHigh-Z
ReadLLHLROW/COLDOUT
Write: Word (Early Write)LLLXROW/COLDIN
Read-WriteLLH→LL→HROW/COLDOUT, DIN
EDO Page-Mode Read1st Cycle:LH→LHLROW/COLDOUT
2nd Cycle:LH→LHLNA/COLDOUT
EDO Page-Mode Write1st Cycle:LH→LLXROW/COLDIN
2nd Cycle:LH→LLXNA/COLDIN
EDO Page-Mode1st Cycle:LH→LH→LL→HROW/COLDOUT, DIN
Read-Write2nd Cycle:LH→LH→LL→HNA/COLDOUT, DIN
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
IS41C4400X
IS41LV4400X S ERIESISSI
®
Functional Description
The IS41C4400x and IS41LV4400x are CMOS
DRAMs optimized for high-speed bandwidth, low
power applications. During READ or WRITE cycles, each
bit is uniquely addressed through the 11 or 12 address
bits. These are entered 11 bits (A0-A10) at a time for the
2K refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time
specified by tAR. Data Out becomes valid only when tRAC,
tAA, tCAC and tOEA are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Auto Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in
each 64ms period. There are two ways to refresh the
memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through
A11) with RAS at least once every 32 ms or 64ms
respectively. Any read, write, read-modify-write or
RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of 200
µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a RAS
signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
3
IS41C4400X
IS41LV4400X S ERIESISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
SymbolParametersRatingUnit
VTVoltage on Any Pin Relative to GND5V–1.0 to +7.0V
3.3V–0.5 to +4.6
CCSupply Voltage5V–1.0 to +7.0V
V
3.3V–0.5 to +4.6
IOUTOutput Current50mA
PDPower Dissipation1W
ACommercial Operation Temperature0 to +70°C
T
Industrial Operation Temperature-40 to +85
TSTGStorage Temperature–55 to +125°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
REF refresh requirement is exceeded.
Integrated Silicon Solution, Inc. — 1-800-379-4774
tCASCAS Pulse Width
tCPCAS Precharge Time
tCSHCAS Hold Time
tRCDRAS to CAS Delay Time
tASRRow-Address Setup Time0—0—ns
tRAHRow-Address Hold Time8—10—ns
(20)
(20)
0—0—ns
8—10—ns
tASCColumn-Address Setup Time
tCAHColumn-Address Hold Time
tARColumn-Address Hold Time30—40—ns
(referenced to RAS)
tRADRAS to Column-Address Delay Time
(11)
10251230ns
tRALColumn-Address to RAS Lead Time25—30—ns
tRPCRAS to CAS Precharge Time5—5—ns
tRSHRAS Hold Time8—10—ns
tRHCPRAS Hold Time from CAS Precharge30—35—ns
(19, 24)
(15, 16)
(15, 24)
(21)
0—0—ns
5—5—ns
315315ns
—12—15ns
tCLZCAS to Output in Low-Z
tCRPCAS to RAS Precharge Time
tODOutput Disable Time
tOEOutput Enable Time
tOEDOutput Enable Data Delay (Write)12—15—ns
tOEHCOE HIGH Hold Time from CAS HIGH5—5—ns
tOEPOE HIGH Pulse Width10—10—ns
tOESOE LOW to CAS HIGH Setup Time5—5—ns
tRCSRead Command Setup Time
(17, 20)
0—0—ns
tRRHRead Command Hold Time0—0—ns
(referenced to RAS)
(12)
tRCHRead Command Hold Time0—0—ns
(referenced to CAS)
tWCHWrite Command Hold Time
(12, 17, 21)
(17)
8—10—ns
tWCRWrite Command Hold Time40—50—ns
(referenced to RAS)
tWPWrite Command Pulse Width
(17)
(17)
8—10—ns
tWPZWE Pulse Widths to Disable Outputs7—7—ns
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/24/01
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