ISSI IS41C4100, IS41LV4100 User Manual
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IS41C4100
IS41LV4100 ISSI
1Meg x 4 (4-MBIT) DYNAMIC RAM
PRELIMINARY INFORMATION
WITH EDO PAGE MODE
SEPTEMBER 2001
®
FEATURES
• TTL compatible inputs and outputs
• Refresh Interval: 1024 cycles/16 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single power supply
5V ± 10% (IS41C4100)
3.3V ± 10% (IS41LV4100)
• Industrail Temperature Range -40oC to 85oC
KEY TIMING PARAMETERS
Parameter -35 -60 Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
Max. Column Address Access Time (tAA)
Min. Fast Page Mode Cycle Time (tPC)
Min. Read/Write Cycle Time (tRC)
35 60 ns
10 15 ns
18 30 ns
12 25 ns
60 110 ns
PIN DESCRIPTIONS
DESCRIPTION
The ISSI IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access
Memory. Both products offer accelerated cycle access
EDO Page Mode. EDO Page Mode allows 512 random
accesses within a single row with access cycle time as
short as 10ns per 4-bit word.
These features make the IS41C4100 and IS41LV4100 ideally
suited for high
high-performance computing systems, and peripheral applications.
The IS41C4100 and IS41LV4100 are available in a 20-pin,
300-mil SOJ package.
band-width
graphics,
digital signal processing,
PIN CONFIGURATION
20-Pin SOJ
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
20
19
18
17
16
GND
I/O3
I/O2
CAS
OE
A0-A9 Address Inputs
I/O0-I/O3 Data Inputs/Outputs
15
14
13
12
11
A8
A7
A6
A5
A4
WE Write Enable
OE Output Enable
RAS Row Address Strobe
CAS Column Address Strobe
VCC Power
GND Ground
NC No Connection
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
A0
A1
A2
A3
Vcc
6
7
8
9
10
1
IS41C4100
E
IS41LV4100 ISSI
FUNCTIONAL BLOCK DIAGRAM
O
WE
®
CAS
RAS
A0-A9
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
WE
CAS WE
RAS
CONTROL
LOGICS
COLUMN DECODERS
SENSE AMPLIFIERS
ROW DECODER
OE
CONTROL
LOGIC
OE
DATA I/O BUS
I/O0-I/O3
DATA I/O BUFFERS
MEMORY ARRAY
1,048,576 x 4
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
IS41C4100
IS41LV4100 ISSI
TRUTH TABLE
Function RAS CAS WE OE Address tR/tC I/O
Standby H H X X X High-Z
Read: Word L L H L ROW/COL DOUT
Read: Lower Byte L L H L ROW/COL Lower Byte, DOUT
Upper Byte, High-Z
Read: Upper Byte L H H L ROW/COL Lower Byte, High-Z
Upper Byte, DOUT
Write: Word (Early Write) L L L X ROW/COL DIN
Write: Lower Byte (Early Write) L L L X ROW/COL Lower Byte, DIN
Upper Byte, High-Z
Write: Upper Byte (Early Write) L H L X ROW/COL Lower Byte, High-Z
Upper Byte, DIN
Read-Write
EDO Page-Mode Read
DOUT
EDO Page-Mode Write
(1,2)
LLH→LL→H ROW/COL DOUT, DIN
(2)
1st Cycle: L H→ L H L ROW/COL
2nd Cycle: L H→ L H L NA/COL DOUT
Any Cycle: L L→ H H L NA/NA DOUT
(1)
1st Cycle: L H→ L L X ROW/COL, DIN
2nd Cycle: L H→ L L X NA/COL DIN
®
EDO Page-Mode 1st Cycle: L H→ LH→LL→H ROW/COL
DOUT, DIN
Read-Write
Hidden Refresh
(1,2)
2nd Cycle: L H→ LH→ LL→ H NA/COL DOUT, DIN
2)
Read L→H→L L H L ROW/COL
DOUT
Write L→H→L L L X ROW/COL
DOUT
RAS-Only Refresh L H X X ROW/NA High-Z
CBR Refresh
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. At least one of the two CAS signals must be active (LCAS or UCAS).
(3)
H→ L L X X X High-Z
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
3
IS41C4100
IS41LV4100 ISSI
®
Functional Description
The IS41C4100 and IS41LV4100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely
addressed through the 19 address bits. The first ten
address bits (A0-A9) are entered as row address and
latter nine bits nine address bits (A0-A8) are entered as
column address. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter nine bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA,
tCAC and tOEA are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 10-bit counter provides the row
addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write operations during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0
through A9) with RAS at least once every 16 ms. Any
read, write, read-modify-write or RAS-only cycle refreshes the addressed row.
4
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
IS41C4100
IS41LV4100 ISSI
®
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameters Rating Unit
VT Voltage on Any Pin Relative to GND 5V –1.0 to +7.0 V
3.3V -0.5 to 4.6 V
CC Supply Voltage 5V –1.0 to +7.0 V
V
3.3V -0.5 to 4.6 V
IOUT Output Current 50 mA
PD Power Dissipation 1 W
A Commercial Operation Temperature 0 to +70 °C
T
Industrail Temperature –40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 5V 4.5 5.0 5.5 V
3.3V 3.0 3.3 3.6
VIH Input High Voltage 5V 2.4 — VCC + 1.0 V
3.3V 2.0 — VCC + 0.3
VIL Input Low Voltage 5V –1.0 — 0.8 V
3.3V –0.3 — 0.8
TA Commercial Ambient Temperature 0 — 70 °C
Industrail Ambient Temperature –40 — 85 °C
CAPACITANCE
(1,2)
Symbol Parameter Max. Unit
CIN1 Input Capacitance: A0-A9 5 pF
CIN2 Input Capacitance: RAS, CAS, WE, OE 7pF
CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz,
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
5
IS41C4100
IS41LV4100 ISSI
®
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
IL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –55µA
I
Other inputs not under test = 0V
I
IO Output Leakage Current Output is disabled (Hi-Z) –55µA
0V ≤ VOUT ≤ Vcc
VOH Output High Voltage Level IOH = –2.5 mA 2.4 — V
VOL Output Low Voltage Level IOL = +2.1 mA — 0.4 V
I
CC1 Stand-by Current: TTL RAS, CAS ≥ VIH Commercial 5V — 2mA
Industrial 5V — 3
Commercial 3V — 1
Industrial 3V — 4
ICC2 Stand-by Current: CMOS RAS, CAS ≥ VCC – 0.2V 5V — 1mA
3V — 0.5
ICC3 Operating Current: RAS, CAS, -35 — 100 mA
Random Read/Write
Average Power Supply Current
ICC4 Operating Current: RAS = VIL, CAS, -35 — 120 mA
EDO Page Mode
Average Power Supply Current
(2,3,4)
(2,3,4)
Address Cycling, tRC = tRC (min.) -60 — 75
Cycling tPC = tPC (min.) -60 — 65
ICC5 Refresh Current: RAS Cycling, CAS ≥ VIH -35 — 100 mA
RAS-Only
(2,3)
tRC = tRC (min.) -60 — 75
Average Power Supply Current
ICC6 Refresh Current: RAS, CAS Cycling -35 — 100 mA
(2,3,5)
CBR
tRC = tRC (min.) -60 — 75
Average Power Supply Current
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
REF refresh requirement is exceeded.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A
09/10/01
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