l RoHS Compliant and Halogen Free
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Ultra Low Package Inductance
l Optimized for High Frequency Switching
l Ideal for CPU Core DC-DC Converters
l Optimized for Control FET application
l Low Conduction and Switching Losses
l Compatible with existing Surface Mount Techniques
l 100% Rg tested
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SXSTMQMXMTMP
Description
The IRF6721SPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve
the lowest on-state resistance in a package that has the footprint of a MICRO-8 and only 0.7 mm profile. The DirectFET package is
compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection
soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
Typical values (unless otherwise specified)
V
DSS
30V max ±20V max
Q
g tot
Q
V
gd
GS
R
DS(on)
R
5.1mΩ@ 10V 8.5mΩ@ 4.5V
Q
gs2
Q
rr
Q
oss Vgs(th)
DS(on)
11nC3.7nC1.3nC19nC7.9nC1.9V
SQ
DirectFET ISOMETRIC
The IRF6721SPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6721SPbF has been optimized for parameters that are critical in synchronous buck
operating from 12 volt bus converters including Rds(on) and gate charge to minimize losses.
Absolute Maximum Ratings
ParameterUnits
V
DS
V
GS
@ TA = 25°C
I
D
ID @ TA = 70°C
@ TC = 25°C
I
D
I
DM
E
AS
I
AR
25
)
20
Ω
m
(
)
n
15
o
(
S
D
R
10
l
a
c
i
p
5
y
T
Fig 1. Typical On-Resistance vs. Gate Voltage
Notes:
TJ = 25°C
0
05101520
Drain-to-Source VoltageV
Gate-to-Source Voltage
Continuous Drain Current, V
Continuous Drain Current, V
Continuous Drain Current, V
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
TJ = 125°C
V
Gate -to -Source Voltage (V)
GS,
g
g
@ 10V
GS
@ 10V
GS
@ 10V
GS
ID = 14A
h
Click on this section to link to the appropriate technical paper.
Click on this section to link to the DirectFET Website.
Surface mounted on 1 in. square Cu board, steady state.
eef
)
14.0
V
(
e
g
a
t
l
o
V
e
c
r
u
o
S
o
t
e
t
a
G
,
S
G
V
Fig 2. Typical Total Gate Charge vs. Gate-to-Source Voltage
T
ID= 11A
12.0
10.0
8.0
6.0
4.0
2.0
0.0
0 4 8 121620242832
QG, Total Gate Charge (nC)
measured with thermocouple mounted to top (Drain) of part.
C
Repetitive rating; pulse width limited by max. junction temperature.
Starting T
= 25°C, L = 1.1mH, RG = 25Ω, I
J
Max.
30
±20
14
11
60
110
62
11
VDS= 24V
VDS= 15V
AS
A
mJ
A
= 11A.
www.irf.com1
04/30/09
IRF6721SPbF
Static @ TJ = 25°C (unless otherwise specified)
ParameterMin.Typ. Max. Units
BV
DSS
∆ΒV
∆V
R
V
I
DSS
I
GSS
DS(on)
GS(th)
GS(th)
DSS
/∆T
/∆T
gfsForward Transconductance25––––––S
Q
g
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
Q
oss
R
G
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Diode Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
Drain-to-Source Breakdown Voltage30––––––V
Breakdown Voltage Temp. Coefficient–––22––– mV/°C
J
Static Drain-to-Source On-Resistance–––5.17.3
m
–––8.510.9
Gate Threshold Voltage1.41.92.4V
Gate Threshold Voltage Coefficient–––-6.3––– mV/°C
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
***
VGS=10V
V
DD
I
SD
G = GATE
D = DRAIN
S = SOURCE
DD
GS
DD
www.irf.com7
IRF6721SPbF
DirectFET
Outline Dimension, SQ Outline
(Small Size Can, Q-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes
all recommendations for stencil and substrate designs.