Datasheet IRF7821 Datasheet (IOR)

Applications
A
l High Frequency Point-of-Load
Synchronous Buck Converter for Applications in Networking & Computing Systems.
Benefits
DS(on)
at 4.5V V
GS
and Current
HEXFET® Power MOSFET
V
DSS
30V 9.1mW@V
1
S
2
S
3
S
4
Top View
8
7
6
5
R
DS(on)
A
D
D
D
DG
PD - 94579B
IRF7821
max Qg(typ.)
= 10V 9.3nC
GS
SO-8
Absolute Maximum Ratings
V
DS
V
GS
@ TA = 25°C
I
D
@ TA = 70°C
I
D
I
DM
PD @TA = 25°C
@TA = 70°C
P
D
T
J
T
STG
Parameter Units
Drain-to-Source Voltage V Gate-to-Source Voltage Continuous Drain Current, V Continuous Drain Current, V Pulsed Drain Current Power Dissipation Power Dissipation
Linear Derating Factor W/°C Operating Junction and °C
Storage Temperature Range
c f f
@ 10V
GS
@ 10V
GS
Max.
30
± 20
13.6 11
100
2.5
1.6
0.02
-55 to + 155
A
W
Thermal Resistance
Parameter Typ. Max. Units
R
θJL
R
θJA
Junction-to-Drain Lead Junction-to-Ambient
fg
g
––– 20 °C/W ––– 50
Notes through  are on page 10
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1/14/03
IRF7821
/
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS
∆ΒV
DSS
R
DS(on)
V
GS(th)
V
GS(th)
I
DSS
I
GSS
gfs Forward Transconductance 22 ––– ––– S Q
g
Q
gs1
Q
gs2
Q
gd
Q
godr
Q
sw
Q
oss
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Drain-to-Source Breakdown Voltage 30 ––– ––– V
T
Breakdown Voltage Temp. Coefficient ––– 0.025 ––– V/°C
J
Static Drain-to-Source On-Resistance ––– 7.0 9.1
––– 9.5 12.5 Gate Threshold Voltage 1.0 ––– ––– V Gate Threshold Voltage Coeffic i ent ––– - 4.9 ––– mV/°C Drain-to-Source Leakage Current ––– ––– 1.0 µA
––– ––– 150 Gate-to-Source Forward Leakage ––– ––– 100 nA Gate-to-Source Reverse Leakage ––– ––– -100
Total Gate Charge ––– 9.3 14 Pre-Vth Gate-to-Source Charge ––– 2.5 ––– Post-Vth Gate-to-Sourc e Charge ––– 0.8 ––– nC Gate-to-Drain Charge ––– 2.9 ––– Gate Charge Overdrive ––– 3.1 ––– See Fig. 16 Switch Charge (Q
gs2
+ Qgd)
––– 3.7 ––– Output Charge ––– 6.1 ––– nC Turn-On Delay Time ––– 6.3 ––– Rise Time ––– 2.7 ––– Turn-Off Delay Time ––– 9.7 ––– ns Fall Time ––– 7.3 ––– Input Capacitance ––– 1010 ––– Output Capacitance ––– 360 ––– pF Reverse Transfer Capacitance ––– 110 –––
VGS = 0V, ID = 250µA Reference to 25°C, I V
m
= 10V, ID = 13A
GS
= 4.5V, ID = 10A
V
GS
V
= VGS, ID = 250µA
DS
= 24V, VGS = 0V
V
DS
V
= 24V, VGS = 0V, TJ = 125°C
DS
V
= 20V
GS
V
= -20V
GS
V
= 15V, ID = 10A
DS
= 15V
V
DS
VGS = 4.5V
= 10A
I
D
V
= 10V, VGS = 0V
DS
V
= 15V, VGS = 4.5V
DD
ID = 10A Clamped Inductive Load
V
= 0V
GS
V
= 15V
DS
ƒ = 1.0MHz
Conditions
= 1mA
D
e
e
e
Avalanche Characteristics
E
AS
I
AR
Single Pulse Avalanche Energy Avalanche Current
c
dh
Parameter Units
Typ.
––– –––
Max.
44 10
mJ
A
Diode Characteristics
Parameter Min. Typ. Max. Units
I
S
Continuous Source Current ––– ––– 3.1 (Body Diode) A
I
SM
V
SD
t
rr
Q
rr
Pulsed Source Current ––– ––– 100 (Body Diode)
ch
Diode Forward Voltage ––– ––– 1.0 V Reverse Recovery Time ––– 28 42 ns Reverse Recovery Charge ––– 23 35 nC
MOSFET symbol showing the
integral reverse p-n junction diode.
TJ = 25°C, IS = 10A, VGS = 0V
= 25°C, IF = 10A, VDD = 10V
T
J
di/dt = 100A/µs
Conditions
e
e
2 www.irf.com
IRF7821
100
) A
(
t
n
e
r
10
r
u C e
c
r
u
o S
-
o
t
-
1
n
i
a
r D
,
D
I
2.5V
20µs PULSE WIDTH Tj = 25°C
0.1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
100.0
TJ = 150°C
)
Α
(
t
n
e
r
10.0
r
u C e
c
r
u
o S
-
o
t
-
1.0
n
i
a
r D
,
D
I
0.1
2.0 3.0 4.0 5.0 6.0
TJ = 25°C
V
= 15V
DS
20µs PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V BOTTOM 2.5V
100
) A
(
t
n
e
r
r
u C e
c
r
10
u
o S
-
o
t
-
n
i
a
r D
,
D
I
2.5V
20µs PULSE WIDTH
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V BOTTOM 2.5V
Tj = 150°C
1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
2.0
e
c
n
a
t
s
i
s
e R n O e
c
r
u
o S
-
o
t
-
n
i
a
r D
,
)
n
o
( S D
R
ID = 13A V
= 10V
GS
1.5
)
d
e
z
i
l
a m
r
o N
(
1.0
0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRF7821
) F
p
( e
c
n
a
t
i
c
a
p
a C
, C
10000
1000
100
10
1 10 100
V
= 0V, f = 1 MHZ
GS
C
= C
= C
= C
gs
gd
ds
Ciss
Coss
Crss
+ Cgd, C
+ C
iss
C
rss
C
oss
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
12
SHORTED
ds
gd
) V
( e
g
a
t
l
o V
e
c
r
u
o S
-
o
t
-
e
t
a G
, V
ID= 10A
10
8
6
4
S
2
G
0
0 5 10 15 20
Q
VDS= 24V VDS= 15V
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100.0
) A
(
t
n
e
r
10.0
r
u C n
i
a
r D e
s
r
e
v
1.0
e R
,
D S
I
0.1
TJ = 150°C
TJ = 25°C
0.0 0.5 1.0 1.5 VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
V
GS
= 0V
1000
) A
(
t
100
n
e
r
r
u C e
c
r
u
10
o S
-
o
t
-
n
i
a
r
1
D ,
D
I
Tc = 25°C Tj = 150°C Single Pulse
0.1
0.1 1.0 10.0 100.0 1000.0 V
OPERATION IN THIS AREA LIMITED BY RDS(on)
, Drain-toSource Voltage (V)
DS
100µsec
1msec
10msec
Fig 8. Maximum Safe Operating Area
Forward Voltage
4 www.irf.com
IRF7821
14
12
)
10
A
(
t
n
e
r
8
r
u C n
i
6
a
r D
,
4
D
I
2
0
25 50 75 100 125 150
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
2.6
) V
( e
g
2.2
a
t
l
o V
d
l
o
h
s
1.8
e
r
h
t e
t
a G
)
h
1.4
t
( S G
V
1.0
-75 -50 -25 0 25 50 75 100 125 150
TJ , Temperature ( °C )
ID = 250µA
Fig 10. Threshold Voltage Vs. Temperature
100
)
A
J
h
t
Z (
e
s
n
o
p
s
e R
l
a m
r
e
h T
D = 0.50
10
1
0.1
0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE ( THERMAL RESPONSE )
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7821
A
)
30
m
( e
c
n
25
a
t
s
i
s
e R
20
n O e
c
r
15
u
o S
­o
t
10
-
n
i
a
r D
5
,
)
n
o
(
S
0
D
R
2.0 4.0 6.0 8.0 10.0
VGS, Gate-to-Source Voltage (V)
ID = 13A
TJ = 125°C
TJ = 25°C
100
)
J m
( y
g
80
r
e
n E
e
h
c
60
n
a
l
a
v A
e
40
s
l
u P
e
l
g
n
i
20
S
, S A
E
0
25 50 75 100 125 150
Starting TJ, Junction Temperature (°C)
I
TOP
D
4.5A
8.0A 10A
BOTTOM
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
L
D.U.T
D
V
DD
15V
DRIVER
+
-
V
DD
R
V
20V
V
DS
G
GS
t
L
D.U.T
I
AS
0.01
p
Fig 13a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
V
DS
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 14a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
I
AS
Fig 13b. Unclamped Inductive Waveforms
t
t
d(on)
f
Fig 14b. Switching Time Waveforms
t
d(off)
t
r
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IRF7821
D.U.T
+
-
R
G
Current Regulator
Same Type as D.U.T.
+
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
-
Low Leakage Inductance Current Transformer
-
dv/dt controlled by R
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
G
Driver Gate Drive
P.W.
D.U.T. ISDWaveform
Reverse Recovery
+
-
Current
Re-Applied Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
GS
+
V
DD
Period
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple 5%
= 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Vds
D =
P.W.
Period
VGS=10V
V
DD
I
SD
*
Id
Vgs
12V
.2µF
50K
.3µF
D.U.T.
+
V
DS
-
Vgs(th)
V
GS
3mA
I
G
Current Sampling Resistors
I
Fig 16. Gate Charge Test Circuit
D
Qgs1
Qgs2 Qgd Qgodr
Fig 17. Gate Charge Waveform
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IRF7821
)
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the R MOSFET, but these conduction losses are only about one half of the total losses.
Power losses in the control switch Q1 are given by;
P
= P
loss
This can be expanded and approximated by;
P
loss
conduction
= I
()
rms
 
+ I ×
+ Qg× Vf
()
Q
+
This simplified loss equation includes the terms Q and Q
charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q Fig 16.
the gate driver between the time that the threshold voltage has been reached and the time the drain cur­rent rises to I gins to change. Minimizing Q reducing switching losses in Q1.
put capacitance of the MOSFET during every switch­ing cycle. Figure A shows how Q parallel combination of the voltage dependant (non­linear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
which are new to Power MOSFET data sheets.
oss
Q
is a sub element of traditional gate-source
gs2
Q
indicates the charge that must be supplied by
gs2
Q
is the charge that must be supplied to the out-
oss
+ P
2
× R
ds(on )
Q
gd
× Vin× f
i
g
oss
×Vin× f
2
at which time the drain voltage be-
dmax
switching
 
 
and Q
gs1
+ P
+ I ×
+ P
drive
Q
gs2
i
gs2
g
, can be seen from
gs2
is a critical factor in
is formed by the
oss
of the
ds(on)
output
× Vin× f
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
= P
loss
conduction
P
= I
loss
+ Qg× Vg× f
+
rms
()
Q
 
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R
portant characteristic; however, once again the im-
 
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the con­trol IC so the gate drive losses become much more significant. Secondly, the output charge Q verse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.
gs2
The drain of Q2 is connected to the switching node of the converter and therefore sees transitions be­tween ground and Vin. As Q1 turns on and of f there is a rate of change of drain voltage dV/dt which is ca­pacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Q potential for Cdv/dt turn on.
Figure A: Q
+ P
2
× R
ds(on)()
oss
×Vin× f
2
must be minimized to reduce the
gs1
Characteristic
oss
drive
*
+ P
output
+ Qrr× Vin× f
(
ds(on)
oss
is an im-
and re-
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SO-8 Package Details
IRF7821
D B
8X b
5
65
4312
e1
CAB
A1
H
0.25 [.010]
A
A
C
0.10 [.004]
A
87
6
E
e
6X
0.25 [.010]
NOTE S:
1. DIMENSIONING & TOLE RANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIME NS IONS ARE S HOWN IN MILL IMET ER S [INCHES ].
4. OUT LINE CONFORMS T O JEDEC OUTL INE MS-012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUS IONS NOT T O EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS. MOLD PROTRUS IONS NOT T O EXCEED 0.25 [.010].
7 DIMENS ION IS TH E L E NGTH OF L EAD FOR S OLDE RING TO A S U BS T RAT E .
y
3X 1.27 [.050]
DIM
MI N MAX
A
.0532
A1
b
c .0075 .0098 0.19 0.25
D
E
e
e1
H
K
L
y
K x 45°
8X L
7
6.46 [.255]
.0688
.0040
.0098
.013
.020
.189
.1968
.1497
.1574
.050 BASI C
.025 BASI C 0.635 BASIC
.2284
.2440
.0099
.0196
.016
.050
8X c
F OOT P R I NT
8X 0.72 [.028]
MI LL I ME T E R SINCHES
MI N MAX
1.35
1.75
0.10
0.25
0.33
0.51
4.80
5.00
3.80
4.00
1.27 BASI C
5.80
6.20
0.25
0.50
0.40
1.27
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSF ET )
DAT E CODE (YWW) Y = LAS T DIGIT OF T HE YEAR
YWW XXXX
INTERNATIONAL
F7101
RECT IFIER
LOGO
www.irf.com 9
WW = WEEK
LOT CODE
PART NUMBER
IRF7821
SO-8 Tape and Reel
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting T
RG = 25, I
= 25°C, L = 0.87mH
J
= 10A.
AS
Pulse width 400µs; duty cycle 2%.When mounted on 1 inch square copper board R
is measured at TJ approximately 90°C
θ
This product has been designed and qualified for the Industrial market.
FEED DIRECTION
14.40 ( .566 )
12.40 ( .488 )
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.1/04
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