intersil X5168, X5169 DATA SHEET

查询X5165V14Z供应商

®

X5168, X5169

(Replaces X25268, X25169)

Data Sheet September 16, 2005

CPU Supervisor with 16Kbit SPI EEPROM

These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.

Applying power to the device activates the power-on reset
circuit which holds RESET
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.

The device’s low V

CC

system from low voltage conditions by holding
RESET

/RESET active when VCC falls below a minimum VCC

trip point. RESET

/RESET remains asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard V

thresholds are available, however, Intersil’s

TRIP

unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.

/RESET active for a period of

detection circuitry protects the user’s

FN8130.1

Features

•Low VCC Detection and Reset Assertion

- Five standard reset threshold voltages

- Re-program low V
special programming sequence

- Reset signal valid to V

• Long Battery Life with Low Power Consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 16Kbits of EEPROM

• Built-in Inadvertent Write Protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

™

protection

Lock

- In circuit programmable ROM mode

• 2MHz SPI Interface Modes (0,0 & 1,1)

• Minimize EEPROM Programming Time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation

• Available Packages

- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-Free Plus Anneal Available (RoHS Compliant)

reset threshold voltage using

CC

= 1V

CC

Block Diagram

WP

SI

SO

SCK

CS

V

CC

1

Data

Register

Command

Decode &

Control

Logic

V

TRIP

Protect Logic

Status

Register

4Kbits
4Kbits

8Kbits

Reset

Timebase

Power-on and

Low Voltage

+

-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Reset

Generation

EEPROM Array

RESET/RESET

X5168 = RESET
X5169 = RESET

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

X5168, X5169

Ordering Information

PAR T N UM BE R

RESET

(ACTIVE LOW)

X5168P-4.5A X5168P AL X5169P-4.5A X5169P AL 4.5-5.5 4.5.4.75 0 to 70 8 Ld PDIP

- - X5169PZ-4.5A 8 Ld PDIP

X5168PI-4.5A X5169PI-4.5A -40 to 85 8 Ld PDIP

- - X5169PIZ-4.5A X5169P Z AM 8 Ld PDIP

X5168S8-4.5A X5168 AL X5169S8-4.5A X5169 AL 0 to 70 8 Ld SOIC

X5168S8Z-4.5A X5168 Z AL X5169S8Z-4.5A X5169 Z AL 8 Ld SOIC

X5168S8I-4.5A* X5168 AM X5169S8I-4.5A X5169 AM -40 to 85 8 Ld SOIC

X5168S8IZ-4.5A* X5168 Z AM X5169S8IZ-4.5A X5169 Z AM 8 Ld SOIC

X5168V14-4.5A X5169V14-4.5A 0 to 70 14 Ld TSSOP

X5168V14I-4.5A X5169V14I-4.5A -40 to 85 14 Ld TSSOP

X5168P X5168P X5169P X5169P 4.5-5.5 4.25.4.5 0 to 70 8 Ld PDIP

- - X5169PZ X5169P Z 8 Ld PDIP

X5168PI X5168P I X5169PI X5169P I -40 to 85 8 Ld PDIP

- - X5169PIZ X5169P Z I 8 Ld PDIP

X5168S8* X5168 X5169S8* X5169 0 to 70 8 Ld SOIC

X5168S8Z* X5168 Z X5169S8Z* X5169 Z 8 Ld SOIC

X5168S8I* X5168 I X5169S8I* X5169 I -40 to 85 8 Ld SOIC

X5168S8IZ* X5168 Z I X5169S8IZ* X5169 Z I 8 Ld SOIC

X5168V14* X5168V X5169V14* X5169V 0 to 70 14 Ld TSSOP

X5168V14I* X5169V14I* -40 to 85 14 Ld TSSOP

X5168P-2.7A X5169P-2.7A 2.7-5.5 2.85-3.0 0 to 70 8 Ld PDIP

- - X5169PZ-2.7A X5169P Z AN 8 Ld PDIP

X5168PI-2.7A X5169PI-2.7A -40 to 85 8 Ld PDIP

- - X5169PIZ-2.7A X5169P Z AP 8 Ld PDIP

X5168S8-2.7A* X5168 AN X5169S8-2.7A X5169 AN 0 to 70 8 Ld SOIC

X5168S8Z-2.7A* (Note) X5168 Z AN X5169S8Z-2.7A X5169 Z AN 8 Ld SOIC

X5168S8I-2.7A X5169S8I-2.7A -40 to 85 8 Ld SOIC

X5168S8IZ-2.7A X5168 Z AP X5169S8IZ-2.7A X5169 Z AP 8 Ld SOIC

X5168V14-2.7A X5169V14-2.7A 0 to 70 14 Ld TSSOP

X5168V14I-2.7A* X5169VI14-2.7A -40 to 85 14 Ld TSSOP

X5168P-2.7 X5169P-2.7 2.7-5.5 2.55-2.7 0 to 70 8 Ld PDIP

- - X5169PZ-2.7 X5169P Z F 8 Ld PDIP

X5168PI-2.7 X5169PI-2.7 -40 to 85 8 Ld PDIP

- - X5169PIZ-2.7 X5169P Z G 8 Ld PDIP

X5168S8-2.7* X5168 F X5169S8-2.7* X5169 F 0 to 70 8 Ld SOIC

X5168S8Z-2.7* X5168 Z F X5169S8Z-2.7* X5169 Z F 8 Ld SOIC

X5168S8I-2.7* X5168 G X5169S8I-2.7* X5169 G -40 to 85 8 Ld SOIC

X5168S8IZ-2.7* X5168 Z G X5169S8IZ-2.7* X5169 Z G 8 Ld SOIC

X5168V14-2.7* X5169V14-2.7* 0 to 70 14 Ld TSSOP

X5168V14I-2.7 X5169V14I-2.7* -40 to 85 14 Ld TSSOP

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add "-T1" suffix for tape and reel.

PAR T

MARKING

PART NUMBER

RESET

(ACTIVE HIGH)

PART

MARKING

V

CC

RANGE

(V)

V

TRIP

RANGE
(V)

TEMP RANGE

(°C) PACKAGE

Tape and Reel
(Pb-free)

2

FN8130.1

September 16, 2005

X5168, X5169

Pin Configuration

14 LD TSSOP

WP

V

CS
SO

SS

8 LD SOIC/PDIP

X5168/69

1

2
3

4

CS

V

SO
NC

NC
NC
WP

SS

8

7
6

5

V

CC

RESET/RESET

SCK
SI

1
2

3
4

5
6
7

X5168/69

Pin Description

PIN

(SOIC/PDIP) PIN TSSOP NAME FUNCTION

11CSChip Select Input.

pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS
to the start of any operation after power-up, a HIGH to LOW transition on CS

22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

58SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

69SCKSerial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.

36WPWrite Protect. The WP

of the watchdog timer control and the memory write protect bits.

47V

814V

7 13 RESET

RESET

Ground

SS

Supply Voltage

CC

/

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
the minimum V
enabled and CS
period. A falling edge of CS
up at about 1V and remains active for 200ms after the power supply stabilizes.

3-5,10-12 NC No internal connections

CS HIGH, deselects the device and the SO output

LOW enables the device, placing it in the active power mode. Prior

pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

falls below the minimum VCC sense level. It will remain active until VCC rises above

CC

sense level for 200ms. RESET/RESET goes active if the watchdog timer is

CC

remains either HIGH or LOW longer than the selectable watchdog time out

will reset the watchdog timer. RESET/RESET goes active on power-

14
13
12
11

10

V

CC

/RESET

RESET
NC
NC

NC
SCK

9

SI

8

is required.

3

FN8130.1

September 16, 2005

X5168, X5169

Principles of Operation

Power-on Reset

Application of power to the X5168, X5169 activates a power­on reset circuit. This circuit goes active at about 1V and pulls
the RESET
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscillator.
When V
(nominal) the circuit releases RESET
processor to begin executing code.

Low Voltage Monitoring

During operation, the X5168, X5169 monitors the VCC level
and asserts RESET
preset minimum V
the microprocessor from operating in a power fail or
brownout condition. The RESET
active until the voltage drops below 1V. It also remains active
until V

VCC Threshold Reset Procedure

The X5168, X5169 has a standard VCC threshold (V
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
the V
adjusted.

/RESET pin active. This signal prevents the

exceeds the device V

CC

value for 200ms

TRIP

/RESET, allowing the

/RESET if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

/RESET signal remains

returns and exceeds V

CC

is not exactly right, or for higher precision in

TRIP

value, the X5168, X5169 threshold may be

TRIP

for 200ms.

TRIP

TRIP

)

Resetting the V

This procedure sets the V
example, if the current V
the new V

is something less than 1.7V. This procedure

TRIP

TRIP

Voltage

to a “native” voltage level. For

TRIP

is 4.4V and the V

TRIP

must be used to set the voltage to a lower value.

To reset the V

5.5V to the Vcc pin. Tie the CS

pin HIGH. RESET
Then apply the programming voltage V
and pulse CS

voltage, apply a voltage between 2.7 and

TRIP

pin, the WP pin, and the SCK

/RESET and SO pins are left unconnected.

to the SI pin ONLY

P

LOW then HIGH. Remove VP and the

sequence is complete.

CS

V

SCK

CC

V

P

SI

FIGURE 2. RESET V

VOLTAGE

TRIP

TRIP

is reset,

Setting the V

This procedure sets the V
example, if the current V

TRIP

Voltage

TRIP

TRIP

to a higher voltage value. For

is 4.4V and the new V

TRIP

is

4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.

To set the new V
threshold to the V
HIGH. RESET
Then apply the programming voltage V
and pulse CS

voltage, apply the desired V

TRIP

pin and tie the CS pin and the WP pin

CC

TRIP

/RESET and SO pins are left unconnected.

to both SCK and SI

P

LOW then HIGH. Remove VP and the

sequence is complete.

CS

V

P

SCK

V

P

SI

FIGURE 1. SET V

VOLTAGE

TRIP

4

FN8130.1

September 16, 2005

X5168, X5169

V

Programming

TRIP

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

TRIP

New VCC Applied =

Old V

Applied + Error

CC

NO

Error ≥ Emax

Emax = Maximum Desired Error

Execute

Set V

Sequence

Apply 5V to V

Decrement V

(V

= VCC - 10mV)

CC

RESET pin

goes active?

Measured V

Desired V

DONE

TRIP

CC

CC

YES

TRIP

TRIP

Error = 0

New VCC Applied =

Applied - Error

Old V

CC

Execute

Reset V

TRIP

Sequence

-

Error > Emax

V

TRIP

Adj.

Program

4.7K

5

FIGURE 3. V

NC

+

FIGURE 4. SAMPLE V

PROGRAMMING SEQUENCE FLOW CHART

TRIP

1
2
3
4

X5168/

X5169

8
7
6
5

10K

RESET CIRCUIT

TRIP

10K

NC

NC

4.7K
RESET

Reset V
Test V
Set V

V

P

TRIP

TRIP

TRIP

FN8130.1

September 16, 2005

X5168, X5169

SPI Serial Memory

The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS

™

cell,

must be

Write Enable Latch

The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.

Status Register

The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:

7 65 4 3210

WPEN FLB 0 0 BL1 BL0 WEL WIP

LOW during the entire operation.

The Write-In-Progress (WIP) bit is a volatile, read only bit

All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS

goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume

and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.

operations where left off.

TABLE 1. INSTRUCTION SET

INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION

WREN 0000 0110 Set the write enable latch (enable write operations)

SFLB 0000 0000 Set flag bit

WRDI/RFLB 0000 0100 Reset the write enable latch/reset flag bit

RSDR 0000 0101 Read status register

WRSR 0000 0001 Write status register (watchdog, block lock, WPEN & flag bits)

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER

WPEN, BL0, BL1 WD0,

WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK

0 X X Protected Protected Protected

1 1 0 Protected Writable Protected

1 0 X Protected Writable Writable

1 X 1 Protected Writable Writable

6

WD1

September 16, 2005

FN8130.1

X5168, X5169

The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIGH and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.

STATUS

REGISTER BITS ARRAY ADDRESSES PROTECTED

BL1 BL0 X5168/X5169

0 0 None

0 1 $0600-$07FF

1 0 $0400-$07FF

1 1 $0000-$07FF

The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon power­up.

The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP

pin to

provide an in-circuit programmable ROM function (Table 2).

WP

is LOW and WPEN bit programmed HIGH disables all

status register write operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and watchdog bits
from inadvertent corruption.

In the locked state (programmable ROM mode) the WP
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s status register.

Setting the WP

pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the status register.

When WP

is HIGH, all functions, including nonvolatile writes
to the status register operate normally. Setting the WPEN bit
in the status register to “0” blocks the WP
allowing writes to the status register when WP
LOW. Setting the WPEN bit to “1” while the WP

pin function,

is HIGH or

pin is LOW
activates the programmable ROM mode, thus requiring a
change in the WP

pin prior to subsequent status register
changes. This allows manufacturing to install the device in a
system with WP

pin grounded and still be able to program
the status register. Manufacturing can then load
configuration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to be
protected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.

pin

CS

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30

Instruction 16 Bit Address

15 14 13 3 2 1 0

High Impedance

76543210

MSB

FIGURE 5. READ EEPROM ARRAY SEQUENCE

Data Out

7

FN8130.1

September 16, 2005

X5168, X5169

Read Sequence

When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted out.
When the highest address is reached, the address counter
rolls over to address $0000 allowing the read cycle to be
continued indefinitely. The read operation is terminated by
taking CS

high. Refer to the read EEPROM array sequence

(Figure 1).

To read the status register, the CS

line is first pulled low to
select the device followed by the 8-bit RDSR instruction.
After the RDSR opcode is sent, the contents of the status
register are shifted out on the SO line. Refer to the read status
register sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS
the user continues the write operation without taking CS
HIGH after issuing the WREN instruction, the write operation
will be ignored.

is first taken LOW, then the WREN

must then be taken HIGH. If

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS

is required to enter an

active state and receive an instruction.

• SO pin is high impedance.

• The write enable latch is reset.

• The flag bit is reset.

• Reset signal is active for t

PURST

.

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• A WREN instruction must be issued to set the write enable
latch.

must come HIGH at the proper clock count in order to

•CS
start a nonvolatile write cycle.

To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS

must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.

For the page write operation (byte or page write) to be
completed, CS

can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 4).

To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0 and
1 must be “0”.

While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.

8

FN8130.1

September 16, 2005

CS

SCK

X5168, X5169

01234567891011121314

Instruction

SI

CS

SO

High Impedance

FIGURE 6. READ STATUS REGISTER SEQUENCE

CS

SCK

SI

SO

High Impedance

FIGURE 7. WRITE ENABLE LATCH SEQUENCE

Data Out

76543210

MSB

01234567

SCK

CS

SCK

012345678910

Instruction 16 Bit Address

SI

32 33 34 35 36 37 38 39

Data Byte 2

SI

76543210

9

20 21 22 23 24 25 26 27 28 29 30 31

15 14 13 3 2 1 0

40 41 42 43 44 45 46 47

Data Byte 3

76543210

FIGURE 8. WRITE SEQUENCE

Data Byte 1

76543210

Data Byte N

654 3210

FN8130.1

September 16, 2005

CS

X5168, X5169

Symbol Table

WAVEFORM INPUTS OUTPUTS

0123456789

SCK

SI

SO

High Impedance

Must be
steady

May change
from LOW
to HIGH

May change
from HIGH
to LOW

Don’t Care:
Changes
Allowed

N/A Center Line

10 11 12 13 14 15

Instruction

76543210

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

Will be
steady

Will change
from LOW
to HIGH

Will change
from HIGH
to LOW

Changing:
State Not
Known

is High
Impedance

Data Byte

10

FN8130.1

September 16, 2005

X5168, X5169

Absolute Maximum Ratings Recommended Operating Conditions

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on any Pin with Respect to V

. . . . . . . . . . . . -1.0V to +7V

SS

DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability

DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB

I

LI

I

LO

V

(NOTE 1)

V

(NOTE 1)

V

OL1

V

OL2

V

OL3

V

OH1

V

OH2

V

OH3

V

OLS

VCC write current (active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,

SO = Open

VCC read current (active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,

SO = Open

VCC standby current WDT = OFF CS = VCC, VIN = VSS or VCC,

= 5.5V

V

CC

Input leakage current VIN = VSS to VCC 0.1 10 µA

Output leakage current V

Input LOW voltage -0.5 V

IL

Input HIGH voltage V

IH

= VSS to V

OUT

CC

Output LOW voltage VCC > 3.3V, IOL = 2.1mA 0.4 V

Output LOW voltage 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V

Output LOW voltage V

≤ 2V, IOL = 0.5mA 0.4 V

CC

Output HIGH voltage VCC > 3.3V, IOH = -1.0mA V

Output HIGH voltage 2V < VCC ≤ 3.3V, IOH = -0.4mA V

Output HIGH voltage V

Reset output LOW voltage I

≤ 2V, IOH = -0.25mA V

CC

= 1mA 0.4 V

OL

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage Limits

-2.7 or -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Blank or -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V-5.5V

LIMITS

UNITMIN TYP MAX

5mA

0.4 mA

1µA

0.1 10 µA

x 0.3 V

CC

x 0.7 V

CC

- 0.8 V

CC

- 0.4 V

CC

- 0.2 V

CC

+ 0.5 V

CC

Capacitance T

= +25°C, f = 1MHz, VCC = 5V.

A

SYMBOL TEST CONDITIONS MAX. UNIT

C

OUT

(NOTE 2)

C

(NOTE 2) Input capacitance (SCK, SI, CS, WP)V

IN

Output capacitance (SO, RESET

/RESET) V

= 0V 8 pF

OUT

= 0V 6 pF

IN

NOTES:

min. and VIH max. are for reference only and are not tested.

1. V

IL

2. This parameter is periodically sampled and not 100% tested.

11

September 16, 2005

FN8130.1

X5168, X5169

Equivalent A.C. Load Circuit at 5V V

5V

CC

5V

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

Input rise and fall times 10ns

Output

3.03kΩ

2.06kΩ

100pF

4.6kΩ

RESET/RESET

30pF

Input and output timing level V

AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.)

2.7-5.5V

SYMBOL PARAMETER

SERIAL INPUT TIMING

f

t

t

LEAD

t

t

t

t

RI

t

t

WC

SCK

CYC

LAG

WH

WL

t

SU

t

H

FI

t

CS

(3)

(3)

(4)

Clock frequency 0 2 MHz

Cycle time 500 ns

CS lead time 250 ns

CS lag time 250 ns

Clock HIGH time 200 ns

Clock LOW time 200 ns

Data setup time 50 ns

Data hold time 50 ns

Input rise time 100 ns

Input fall time 100 ns

CS deselect time 500 ns

Write cycle time 10 ms

CC

x 0.5

UNITMIN MAX

12

FN8130.1

September 16, 2005

Serial Input Timing

CS

X5168, X5169

t

CS

t

LEAD

SCK

SO

t

SU

SI

MSB IN

High Impedance

t

H

Serial Output Timing

SYMBOL PARAMETER

f

SCK

t

DIS

t

V

t

HO

(3)

t

RO

(3)

t

FO

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

write cycle.

Clock frequency 0 2 MHz

Output disable time 250 ns

Output valid from clock low 200 ns

Output hold time 0 ns

Output rise time 100 ns

Output fall time 100 ns

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

WC

t

LAG

t

RI

t

FI

LSB IN

2.7-5.5V

UNITMIN MAX

Serial Output Timing

CS

SCK

SO

SI

ADDR

LSB IN

t

CYC

t

V

t

HO

t

WH

t

WL

MSB Out MSB–1 Out LSB Out

t

LAG

t

DIS

13

FN8130.1

September 16, 2005

Power-Up and Power-Down Timing

X5168, X5169

V

V

CC

0 Volts

TRIP

t

PURST

t

PURST

t

R

V

TRIP

t

t

F

RPD

RESET (X5168)

RESET (X5169)

RESET

Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

V

TRIP

V

t

PURST

t

RPD

t

F

t

R

V

RVALID

TH

(5)

Reset trip point voltage, X5168-4.5A, X5168-4.5A
Reset trip point voltage, X5168, X5169
Reset trip point voltage, X5168-2.7A, X5169-2.7A
Reset trip point voltage, X5168-2.7, X5169-2.7

V

hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

4.5

4.25

2.85

2.55

voltage) 20 mV

TRIP

4.63

4.38

2.93

2.63

Power-up reset time out 100 200 280 ms

(5)

VCC detect to reset/output 500 ns

VCC fall time 100 µs

(5)

VCC rise time 100 µs

Reset valid V

CC

1V

4.75

4.5

3.0

2.7

V

Note: (5) This parameter is periodically sampled and not 100% tested.

V

Set Conditions

TRIP

V

CC

CS

V

TRIP

V

t

TSU

t

VPS

t

VPS

P

t

P

SCK

V

P

SI

t

THD

t

VPH

t

VPH

t

VPO

t

VPO

t

RP

14

FN8130.1

September 16, 2005

V

Reset Conditions

TRIP

VCC*

X5168, X5169

t

VPS

t

RP

t

t

P

VP1

CS

SCK

V

CC

V

P

t

VPS

t

VPH

t

t

VPO

VPO

SI

*VCC > Programmed V

V

Programming Specifications V

TRIP

TRIP

= 1.7-5.5V; Temperature = 0°C to 70°C

CC

PARAMETER DESCRIPTION MIN MAX UNIT

t

VPS

t

VPH

t

P

t

TSU

t

THD

t

WC

t

RP

t

VPO

V

P

V

TRAN

V

ta1

V

ta2

V

tr

V

tv

V

programming parameters are periodically sampled and are not 100% tested.

TRIP

SCK V

SCK V

V

TRIP

V

TRIP

V

TRIP

V

TRIP

V

TRIP

SCK V

program voltage setup time 1 µs

TRIP

program voltage hold time 1 µs

TRIP

program pulse width 1µs

level setup time 10 µs

level hold (stable) time 10 ms

write cycle time 10 ms

program cycle recovery period (between successive programming cycles) 10 ms

program voltage off time before next cycle 0 ms

TRIP

Programming voltage 15 18 V

V

programed voltage range 1.7 5.0 V

TRIP

Initial V

Subsequent V

V

TRIP

V

TRIP

program voltage accuracy (VCC applied-V

TRIP

program voltage accuracy [(VCC applied-V

TRIP

) (programmed at 25°C) -0.1 +0.4 V

TRIP

)-V

ta1

] (programmed at 25°C) -25 +25 mV

TRIP

program voltage repeatability (successive program operations) (programmed at 25°C) -25 +25 mV

Program variation after programming (0-75°C). (programmed at 25°C) -25 +25 mV

15

FN8130.1

September 16, 2005

Typical Performance

VCC Supply Current vs. Temperature (ISB)

X5168, X5169

t

PURST

vs. Temperature

18
16

Watchdog Timer On (V

CC

14
12

Watchdog Timer On (V

Isb (µA)

10

8
6
4

Watchdog Timer Off (V

2

CC

0

-40C 25C 90C

Temp (°C)

V

vs. Temperature (programmed at 25°C)

TRIP

5.025

5.000

4.975

3.525

3.500

= 5V)

= 3V, 5V)

V

TRIP

V

TRIP

= 5V)

CC

= 5V

= 3.5V

205
200
195
190
185

180
175

Time (ms)

170
165

160

-40 25 90

Degrees °C

Voltage

3.475

2.525

2.500

2.475

= 2.5V

V

TRIP

025 85

Temperature

16

FN8130.1

September 16, 2005

Packaging Information

All End Pins Optional

8-Lead Plastic Dual In-Line Package Type P

Pin 1 Index

Half Shoulder Width On

Seating
Plane

X5168, X5169

0.430 (10.92)

0.360 (9.14)

Pin 1

0.300

(7.62) Ref.

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

0.145 (3.68)

0.128 (3.25)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

.073 (1.84)

Max.

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.325 (8.25)

0.300 (7.62)

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

0°

15°

17

FN8130.1

September 16, 2005

Packaging Information

X5168, X5169

8-Lead Plastic Small Outline Gull Wing Package Type S

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

Pin 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050" Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

18

0.030"

Typical

8 PlacesFOOTPRINT

0.050"
Typical

FN8130.1

September 16, 2005

Packaging Information

X5168, X5169

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

0° - 8°

.0075 (.19)
.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

Detail A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

19

FN8130.1

September 16, 2005