Datasheet X5163, X5165 Datasheet (intersil)

®

X5163, X5165

Data Sheet May 16, 2005

CPU Supervisor with 16Kbit SPI EEPROM

Description

These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates the power-on reset
circuit which holds RESET
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval, the
device activates the RESET
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.

The device’s low V

CC

system from low voltage conditions, resetting the system when
V

falls below the minimum VCC trip point. RESET/RESET is

CC

asserted until V

returns to proper operating level and

CC

stabilizes. Five industry standard V
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom requirements
or to fine-tune the threshold for applications requiring higher
precision.

/RESET active for a period of

/RESET signal. The user selects

detection circuitry protects the user’s

thresholds are

TRIP

FN8128.1

Features

• Selectable watchdog timer

•Low V

- Five standard reset threshold voltages

- Re-program low V

- Reset signal valid to V

• Determine watchdog or low voltage reset with a volatile
flag bit

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 16Kbits of EEPROM

• Built-in inadvertent write protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

- In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 & 1,1)

• Minimize EEPROM programming time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply operation

• Available packages

- 14-lead TSSOP, 8-lead SOIC

detection and reset assertion

CC

reset threshold voltage using

CC

special programming sequence

= 1V

CC

™

protection

Lock

Pinouts

CS/WDI

SO

WP

V

14-LEAD TSSOP

8-LEAD SOIC/PDIP

X5163, X5165

1

2

X5163, X5165

3

SS

4

1

V

8

7
6

5

CC

RESET

/RESET

SCK

SI

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

CS/WDI

SO
NC

NC
NC

WP

V

SS

X5163, X5165

1
2

3
4

5
6

7

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2005. All Rights Reserved

V

14
13

12
11

10

9
8

CC

RESET
NC
NC
NC
SCK
SI

/RESET

Block Diagram

X5163, X5165

CS

WP

SO

SCK

/WDI

Watchdog Transition

Detector

Protect Logic

SI

Data

Register

Status

Register

Command
Decode &

Control

Logic

4K Bits

4K Bits

Watchdog

Timer Reset

Reset &

Watchdog

Timebase

VCC Threshold

Reset Logic

8K Bits

EEPROM Array

Power-on and

V

CC

V

TRIP

+

-

Low Voltage

Reset

Generation

Pin Description

PIN

(SOIC/PDIP) PIN TSSOP NAME FUNCTION

1 1 CS/WDI Chip Select Input.

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS

LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET

/RESET going active.

22SOSerial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

36WPWrite Protect. The WP

of the Watchdog Timer control and the memory write protect bits.

47V

SS

Ground

58SISerial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

69SCKSerial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.

7 13 RESET

RESET

/

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
the minimum V
RESET goes active if the Watchdog Timer is enabled and CS
than the selectable Watchdog time out period. A falling edge of CS
RESET

/RESET goes active on power-up at 1V and remains active for 200ms after the power

supply stabilizes.

814V

CC

Supply Voltage

3-5,10-12 NC No internal connections

CS HIGH, deselects the device and the SO output pin is at a high impedance

pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

falls below the minimum VCC sense level. It will remain active until VCC rises above

CC

sense level for 200ms. RESET/

CC

RESET/RESET

X5163 = RESET
X5165 = RESET

is required

remains either HIGH or LOW longer

will reset the Watchdog Timer.

2

FN8128.1

May 16, 2005

X5163, X5165

Principles Of Operation

Power-on Reset

Application of power to the X516, /X5165 activates a Power­on Reset Circuit. This circuit goes active at 1V and pulls the
RESET
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. When V
exceeds the device V
circuit releases RESET
begin executing code.

Low Voltage Monitoring

During operation, the X5163, X5165 monitors the VCC level
and asserts RESET/RESET
preset minimum V
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS
RESET
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP
the WPEN bit HIGH.

/RESET pin active. This signal prevents the system

value for 200ms (nominal) the

TRIP

CC

/RESET, allowing the processor to

if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

returns and exceeds V

CC

for 200ms.

TRIP

/WDI pin periodically to prevent a

/RESET signal. The CS/WDI pin must be toggled

pin LOW and setting

To set the new V
threshold to the V
pin HIGH. RESET
apply the programming voltage V
pulse CS

/WDI LOW then HIGH. Remove VP and the

voltage, apply the desired V

TRIP

pin and tie the CS/WDI pin and the WP

CC

TRIP

and SO pins are left unconnected. Then

to both SCK and SI and

P

sequence is complete.

CS

V

P

SCK

V

P

SI

FIGURE 1. SET V

Resetting the V

TRIP

Voltage

This procedure sets the V
example, if the current V
the new V

is something less than 1.7V. This procedure

TRIP

TRIP

TRIP

VOLTAGE

TRIP

to a “native” voltage level. For

is 4.4V and the V

TRIP

must be used to set the voltage to a lower value.

To reset the V

5.5V to the V
THE SCK pin HIGH. RESET

voltage, apply a voltage between 2.7 and

TRIP

pin. Tie the CS/WDI pin, the WP pin, AND

CC

and SO pins are left
unconnected. Then apply the programming voltage V
SI pin ONLY and pulse CS

/WDI LOW then HIGH. Remove VP

and the sequence is complete.

is reset,

to the

P

VCC Threshold Reset Procedure

The X5163, X5165 has a standard VCC threshold (V
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
the V

TRIP

is not exactly right, or for higher precision in

TRIP

value, the X5163, X5165 threshold may be

adjusted.

Setting the V

This procedure sets the V
example, if the current V

TRIP

Voltage

TRIP

TRIP

to a higher voltage value. For

is 4.4V and the new V

4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.

TRIP

TRIP

)

is

CS

V

SCK

CC

V

P

SI

FIGURE 2. RESET V

VOLTAGE

TRIP

3

FN8128.1

May 16, 2005

X5163, X5165

V

PROGRAMMING

TRIP

EXECUTE

RESET V

TRIP

SEQUENCE

SET VCC = VCC APPLIED =

DESIRED V

TRIP

NEW VCC APPLIED =

APPLIED + ERROR

OLD V

CC

NO

ERROR > -EMAX

EMAX = MAXIMUM DESIRED ERROR

EXECUTE
SET V

TRIP

SEQUENCE

APPLY 5V TO V

DECREMENT V

(V

= VCC - 50MV)

CC

RESET PIN

GOES ACTIVE?

YES

MEASURED V

DESIRED V

ERROR < EMAX

DONE

TRIP

TRIP

CC

CC

–

NEW VCC APPLIED =

APPLIED - ERROR

OLD V

CC

EXECUTE

RESET V

SEQUENCE

ERROR > EMAX

TRIP

V

TRIP

ADJ.

PROGRAM

4.7K

4

FIGURE 3. V

NC

+

FIGURE 4. SAMPLE V

PROGRAMMING SEQUENCE FLOW CHART

TRIP

X5163, X5165

1
2
3
4

8
7
6
5

10K

RESET CIRCUIT

TRIP

10K

NC

NC

4.7K
RESET

RESET V
TEST V
SET V

TRIP

TRIP

TRIP

V

P

May 16, 2005

FN8128.1

X5163, X5165

SPI Serial Memory

The memory portion of the device is a CMOS Serial EEPROM
array with Intersil’s block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS
LOW during the entire operation.

All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS

goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.

INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION

WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)

SFLB 0000 0000 Set Flag Bit

WRDI/RFLB 0000 0100 Reset the Write Enable Latch/Reset Flag Bit

RSDR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

READ 0000 0011 Read Data from Memory Array Beginning at Selected Address

WRITE 0000 0010 Write Data to Memory Array Beginning at Selected Address

NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

™

cell,

must be

TABLE 1. INSTRUCTION SET

Write Enable Latch

The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:

7 65 43210

WPEN FLB WD1 WD0 BL1 BL0 WEL WIP

The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER

WPEN, BL0, BL1, WD0,

WEL WPEN WP# PROTECTED BLOCK UNPROTECTED BLOCK

0 X X Protected Protected Protected

1 1 0 Protected Writable Protected

1 0 X Protected Writable Writable

1 X 1 Protected Writable Writable

5

WD1

FN8128.1

May 16, 2005

X5163, X5165

The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.

STATUS

REGISTER BITS ARRAY ADDRESSES PROTECTED

BL1 BL0 X516X

0 0 None

0 1 $0600-$07FF

1 0 $0400-$07FF

1 1 $0000-$07FF

The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.

STATUS REGISTER BITS

0 0 1.4 seconds

0 1 600 milliseconds

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

STATUS REGISTER BITS

1 0 200 milliseconds

1 1 disabled

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon power­up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.

The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP

pin to

provide an In-Circuit Programmable ROM function (Table

2). WP

is LOW and WPEN bit programmed HIGH disables

all Status Register Write Operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and Watchdog bits
from inadvertent corruption.

In the locked state (Programmable ROM Mode) the WP
is LOW and the nonvolatile bit WPEN is “1”. This mode
disables nonvolatile writes to the device’s Status Register.

Setting the WP

pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the Status Register.

pin

CS

SCK

SO

0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30

INSTRUCTION 16 BIT ADDRESS

SI

HIGH IMPEDANCE

FIGURE 5. READ EEPROM ARRAY SEQUENCE

6

15 14 13 3 2 1 0

DATA OUT

76543210

MSB

FN8128.1

May 16, 2005

X5163, X5165

When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting the
WPEN bit in the Status Register to “0” blocks the WP
function, allowing writes to the Status Register when WP
HIGH or LOW. Setting the WPEN bit to “1” while the WP
is LOW activates the Programmable ROM mode, thus
requiring a change in the WP
Register changes. This allows manufacturing to install the
device in a system with WP
to program the Status Register. Manufacturing can then
load Configuration data, manufacturing time and other
parameters into the EEPROM, then set the portion of
memory to be protected by setting the block lock bits, and
finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.

pin prior to subsequent Status

pin grounded and still be able

pin

is

pin

Read Sequence

When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The address
is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address is
reached, the address counter rolls over to address $0000
allowing the read cycle to be continued indefinitely. The read
operation is terminated by taking CS
EEPROM Array Sequence (Figure 5).

To read the Status Register, the CS
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the Status Register
are shifted out on the SO line. Refer to the Read Status
Register Sequence (Figure 6).

high. Refer to the Read

line is first pulled low to

Write Sequence

Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS
user continues the Write Operation without taking CS
after issuing the WREN instruction, the Write Operation will be
ignored.

is first taken LOW, then the WREN

must then be taken HIGH. If the

HIGH

To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes
32 clocks. CS
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.

For the Page Write Operation (byte or page write) to be
completed, CS
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 8).

To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 0 and
1 must be “0”.

While the write is in progress following a Status Register or
EEPROM Sequence, the Status Register may be read to
check the WIP bit. During this time the WIP bit will be high.

must go low and remain low for the duration of

can only be brought HIGH after bit 0 of the

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS

active state and receive an instruction.

• SO pin is high impedance.

• The Write Enable Latch is reset.

• The Flag Bit is reset.

• Reset Signal is active for t

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

• A WREN instruction must be issued to set the Write Enable

Latch.

must come HIGH at the proper clock count in order to

•CS

start a nonvolatile write cycle.

is required to enter an

.

PURST

7

FN8128.1

May 16, 2005

CS

SCK

X5163, X5165

01234567891011121314

INSTRUCTION

SI

CS

SO

HIGH IMPEDANCE

FIGURE 6. READ STATUS REGISTER SEQUENCE

CS

SCK

SI

SO

HIGH IMPEDANCE

FIGURE 7. WRITE ENABLE LATCH SEQUENCE

DATA OUT

76543210

MSB

01234567

SCK

CS

SCK

012345678910

INSTRUCTION 16 BIT ADDRESS

SI

32 33 34 35 36 37 38 39

DATA BYTE 2

76543210

SI

8

20 21 22 23 24 25 26 27 28 29 30 31

15 14 13

40 41 42 43 44 45 46 47

DATA BYTE 3

76543210

3

210

FIGURE 8. WRITE SEQUENCE

DATA BYTE 1

76543210

DATA BYTE N

654 321 0

FN8128.1

May 16, 2005

CS

X5163, X5165

SCK

SI

SO

HIGH IMPEDANCE

Symbol Table

WAVEFORM INPUTS OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM LOW TO
HIGH

MAY CHANGE
FROM HIGH TO
LOW

DON’T CARE:
CHANGES
ALLOWED

N/A CENTER LINE

0123456789

INSTRUCTION

6543210

7

FIGURE 9. STATUS REGISTER WRITE SEQUENCE

WILL BE
STEADY

WILL CHANGE
FROM LOW TO
HIGH

WILL CHANGE
FROM HIGH TO
LOW

CHANGING:
STATE NOT
KNOWN

IS HIGH
IMPEDANCE

10 11 12 13 14 15

DATA BYTE

9

FN8128.1

May 16, 2005

X5163, X5165

Absolute Maximum Ratings Recommended Operating Conditions

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . -65 to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C

Voltage on any pin with

respect to V

D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V

SS

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Specifications Over operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

I

CC1

I

CC2

I

SB1

I

SB2

I

SB3

I

V

V

V

V

V

V

V

V

V

VCC Write Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =

Open

VCC Read Current (Active) SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO =

Open

VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC=5.5V 1 µA

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC=5.5V 50 µA

VCC Standby Current WDT = ON CS = VCC, VIN = VSS or VCC, VCC=3.6V 20 µA

I

Input Leakage Current VIN = VSS to V

LI

Output Leakage Current V

LO

(1)

Input LOW Voltage -0.5 V

IL

(1)

Input HIGH Voltage V

IH

Output LOW Voltage VCC > 3.3V, IOL = 2.1mA 0.4 V

OL1

Output LOW Voltage 2V < VCC ≤ 3.3V, IOL = 1mA 0.4 V

OL2

Output LOW Voltage VCC ≤ 2V, IOL = 0.5mA 0.4 V

OL3

Output HIGH Voltage VCC > 3.3V, IOH = –1.0mA V

OH1

Output HIGH Voltage 2V < VCC ≤ 3.3V, IOH = –0.4mA V

OH2

Output HIGH Voltage VCC ≤ 2V, IOH = –0.25mA V

OH3

Reset Output LOW Voltage I

OLS

= VSS to V

OUT

= 1mA 0.4 V

OL

CC

CC

Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

LIMITS

UNITMIN TYP MAX

5mA

0.4 mA

0.1 10 µA

0.1 10 µA

x 0.3 V

CC

x 0.7 V

CC

- 0.8 V

CC

- 0.4 V

CC

- 0.2 V

CC

+ 0.5 V

CC

Capacitance TA = +25°C, f = 1MHz, VCC = 5V

SYMBOL TEST MAX. UNIT CONDITIONS

(2)

C

OUT

C

IN

NOTES:

1. V

min. and VIH max. are for reference only and are not tested.

IL

2. This parameter is periodically sampled and not 100% tested.

Output Capacitance (SO, RESET, RESET) 8 pF V

(2)

Input Capacitance (SCK, SI, CS, WP)6pFV

OUT

IN

10

= 0V

= 0V

FN8128.1

May 16, 2005

X5163, X5165

5V

5V

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

1.64kΩ

OUTPUT

1.64kΩ

RESET/RESET

100pF

FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

3.3kΩ

30pF

CC

Input rise and fall times 10ns

Input and output timing level V

CC

AC Electrical Specifications Serial Input Timing (Over operating conditions unless otherwise specified.)

2.7-5.5V

SYMBOL PARAMETER

f

SCK

t

CYC

t

LEAD

t

LAG

t

t

t

t

RI

t

FI

t

t

WC

WH

WL

SU

t

CS

H

(3)

(3)

(4)

Clock Frequency 0 2 MHz

Cycle Time 500 ns

CS Lead Time 250 ns

CS Lag Time 250 ns

Clock HIGH Time 200 ns

Clock LOW Time 200 ns

Data Setup Time 50 ns

Data Hold Time 50 ns

Input Rise Time 100 ns

Input Fall Time 100 ns

CS Deselect Time 500 ns

Write Cycle Time 10 ms

x0.5

UNITMIN MAX

CS

SCK

SO

t

CS

t

LEAD

t

SU

SI

MSB IN

HIGH IMPEDANCE

t

H

t

RI

t

FI

LSB IN

t

LAG

FIGURE 11. SERIAL INPUT TIMING

11

FN8128.1

May 16, 2005

X5163, X5165

AC Electrical Specifications Serial Output Timing(Over operating conditions unless otherwise specified.)

2.7-5.5V

SYMBOL PARAMETER

f

SCK

t

DIS

t

V

t

HO

(3)

t

RO

(3)

t

FO

NOTES:

3. This parameter is periodically sampled and not 100% tested.

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

4. t

WC

CS

Clock Frequency 0 2 MHz

Output Disable Time 250 ns

Output Valid from Clock Low 200 ns

Output Hold Time 0 ns

Output Rise Time 100 ns

Output Fall Time 100 ns

UNITMIN MAX

SCK

SO

t

CYC

t

V

MSB OUT MSB–1 OUT LSB OUT

SI

ADDR
LSB IN

t

HO

t

WH

t

WL

t

LAG

t

DIS

TABLE 3. SERIAL OUTPUT TIMING

V

TRIP

t

F

t

RPD

V

RESET (X5163)

CC

0 Volts

V

TRIP

t

PURST

t

PURST

t

R

RESET (X5165)

12

TABLE 4. POWER-UP AND POWER-DOWN TIMING

FN8128.1

May 16, 2005

X5163, X5165

RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

V

TRIP

Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7

V

t

PURST

t

RPD

t

F

t

R

V

RVALID

TH

(5)

(5)

(5)

V

Hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

Power-up Reset Time Out 100 200 280 ms

VCC Detect to Reset/Output 500 ns

VCC Fall Time 100 µs

VCC Rise Time 100 µs

Reset Valid V

CC

NOTES:

5. This parameter is periodically sampled and not 100% tested.

6. Typical values not tested.

CS/WDI

4.5

4.25

2.85

2.55

voltage) 20 mV

TRIP

4.63

4.38

2.92

2.63

1V

4.75

4.5

3.0

2.7

V

t

CST

RESET

RESET

t

WDO

t

RST

t

WDO

t

RST

FIGURE 12. CS/WDI VS. RESET/RESET TIMING

RESET/RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

t

WDO

t

CST

t

RST

Watchdog Time Out Period,

WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

1

200
600

1.4

300
800

2

CS Pulse Width to Reset the Watchdog 400 ns

Reset Time Out 100 200 300 ms

ms
ms

sec

13

FN8128.1

May 16, 2005

X5163, X5165

t

THD

V

CC

V

TRIP

t

t

VPS

TSU

t

t

P

VPH

t

RP

CS

t

VPS

V

P

t

VPH

t

VPO

SCK

V

P

t

VPO

SI

FIGURE 13. V

V

V

CC

CS

TRIP

t

VPS

t

t

VPS

TSU

SET CONDITIONS

TRIP

t

THD

t

t

P

t

VP1

VPH

t

t

RP

VPO

SCK

V

CC

V

P

t

VPO

SI

FIGURE 14. V

14

RESET CONDITIONS

TRIP

FN8128.1

May 16, 2005

X5163, X5165

V

Programming Specifications: VCC = 1.7-5.5V; Temperature = 0°C to 70°C

TRIP

PARAMETER DESCRIPTION MIN MAX UNIT

t

VPS

t

VPH

t

P

t

TSU

t

THD

t

WC

t

RP

t

VPO

V

P

V

TRAN

V

ta1

V

ta2

V

tr

V

tv

V

programming parameters are periodically sampled and are not 100% tested.

TRIP

SCK V

SCK V

V

TRIP

V

TRIP

V

TRIP

V

TRIP

V

TRIP

SCK V

Program Voltage Setup time 1 µs

TRIP

Program Voltage Hold time 1 µs

TRIP

Program Pulse Width 1µs

Level Setup time 10 µs

Level Hold (stable) time 10 ms

Write Cycle Time 10 ms

Program Cycle Recovery Period (Between successive programming cycles) 10 ms

Program Voltage Off time before next cycle 0 ms

TRIP

Programming Voltage 15 18 V

V

Programed Voltage Range 1.7 5.0 V

TRIP

Initial V

Subsequent V

V

TRIP

V

TRIP

Program Voltage accuracy (V

TRIP

Program Voltage accuracy [(V

TRIP

Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.) -25 +25 mV

Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV

applied-V

CC

applied-V

CC

) (Programmed at 25°C.) -0.1 +0.4 V

TRIP

)-V

ta1

] (Programmed at 25°C.) -25 +25 mV

TRIP

15

FN8128.1

May 16, 2005

X5163, X5165

18

WATCHDOG TIMER ON (V

16
14
12
10

8

ISB (µA)

6
4

WATCHDOG TIMER OFF (V

2
0

-40 25 90

WATCHDOG TIMER ON (V

TEMP (°C)

= 5V)

CC

= 3V, 5V)

CC

CC

= 5V)

FIGURE 15. VCC SUPPLY CURRENT VS. TEMPERATURE (ISB)

5.025
V

= 5V

V

V

TRIP

TRIP

TRIP

= 3.5V

= 2.5V

5.000

4.975

3.525

3.500

VOLTAGE

3.475

2.525

2.500

2.475

FIGURE 17. V

025 85

TEMPERATURE

vs. Temperature (programmed at 25°C)

TRIP

1.9

1.8

1.7

1.6

1.5

1.4

1.3

RESET (SECONDS)

1.2

1.1
1

1.7 2.4 3.1 3.8 4.5 5.2

FIGURE 16. t

0.8

0.75

0.7

0.65

0.6

0.55

RESET (SECONDS)

0.5

0.45

FIGURE 18. t

-40°C

25°C

90°C

VOLTAGE

VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)

WDO

-40°C

25°C

90°C

1.7 5.2

WDO

2.4 3.1 3.8 4.5
VOLTAGE

VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)

205
200
195
190
185

180

TIME (MS)

175
170
165

160

-40 25 90

FIGURE 19. t

VS. TEMPERATURE

PURST

DEGREES °C

205
200
195
190
185
180
175

170

RESET (SECONDS)

165
160

FIGURE 20. t

25°C

90°C

1.7 5.22.4 3.1 3.8 4.5
VOLTAGE

VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)

WDO

-40°C

16

FN8128.1

May 16, 2005

Packaging Information

X5163, X5165

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

PIN 1 INDEX

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

PIN 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050"TYPICAL

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

17

0.050"
TYPICAL

0.030"

TYPICAL

8 PLACESFOOTPRINT

FN8128.1

May 16, 2005

Packaging Information

X5163, X5165

14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V

.025 (.65) BSC

0° - 8°

.0075 (.19)
.0118 (.30)

.193 (4.9)
.200 (5.1)

.019 (.50)
.029 (.75)

DETAIL A (20X)

.169 (4.3)
.177 (4.5)

.047 (1.20)

.002 (.05)
.006 (.15)

.010 (.25)

GAGE PLANE

SEATING PLANE

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

SEE DETAIL “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

18

FN8128.1

May 16, 2005

Ordering Information

X5163, X5165

V

TRIP

VCC RANGE

4.5-5.5V 4.5.4.75 8-Pin PDIP 0°C - 70°C X5163P-4.5A

4.5-5.5V 4.25.4.5 8-Pin PDIP 0°C - 70°C X5163P X5165P

2.7-5.5V 2.85-3.0 8-Pin PDIP 0°C - 70°C X5163P-2.7A X5165P-2.7A

2.7-5.5V 2.55-2.7 8-Pin PDIP 0°C - 70°C X5163P-2.7 X5165P-2.7

RANGE PACKAGE

8L SOIC 0°C - 70°C X5163S8-4.5A X5165S8-4.5A

14L TSSOP 0°C - 70°C X5163V14-4.5A X5165V14-4.5A

8L SOIC 0°C - 70°C X5163S8 X5165S8

14L TSSOP 0°C - 70°C X5163V14 X5165V14

8L SOIC 0°C - 70°C X5163S8-2.7A X5165S8-2.7A

14L TSSOP 0°C - 70°C X5163V14-2.7A X5165V14-2.7A

8L SOIC 0°C - 70°C X5163S8-2.7 X5165S8-2.7

14L TSSOP 0°C - 70°C X5163V14-2.7 X5165V14-2.7

OPERATING TEMPERATURE

RANGE

-40°C - 85°C X5163PI-4.5A X5165PI-4.5A

-40°C - 85°C X5163S8I-4.5A X5165S8I-4.5A

-40°C - 85°C X5163V14I-4.5A X5165V14I-4.5A

-40°C - 85°C X5163PI X5165PI

0°C - 70°C X51638S8

0°C - 70°C X5163S8T1 X5165S8T1

0°C - 70°C X5163S8T2

-40°C - 85°C X5163S8I X5165S8I

-40°C - 85°C X5163S8IT1 X5165S8IT1

0°C - 70°C X5163V14T1 X5165V14T1

-40°C - 85°C X5163V14I X5165V14I

-40°C - 85°C X5163V14IT1 X5165V14IT1

-40°C - 85°C X5163PI-2.7A X5165PI-2.7A

0°C - 70°C X5163S8-2.7AT1

-40°C - 85°C X5163S8I-2.7A X5165S8I-2.7A

-40°C - 85°C X5163S8I-2.7AT1

-40°C - 85°C X5163V14I-2.7A X5165V14I-2.7A

-40°C - 85°C X5163V14I-2.7T1 X5165V14I-2.7T1

-40°C - 85°C X5163PI-2.7 X5165PI-2.7

0°C - 70°C X5163S8-2.7T1 X5165S8-2.7T1

-40°C - 85°C X5163S8I-2.7 X5165S8I-2.7

-40°C - 85°C X5165S8I-2.7T1

0°C - 70°C X5163V14-2.7T1 X5165V14-2.7T1

-40°C - 85°C X5163V14I-2.7 X5165V14I-2.7

PART NUMBER RESET

(ACTIVE LOW)

PART NUMBER RESET

(ACTIVE HIGH)

19

FN8128.1

May 16, 2005

Part Mark Information

X5163, X51665

W

X5163, X5165

Blank = 8-Lead SOIC

X

V = 14 Lead TSSOP

Blank = 5V ±10%, 0°C to +70°C, V
A = 5V±10%, 0°C to +70°C, V
I = 5V ±10%, -40°C to +85°C, V
IA = 5V ±10%, -40°C to +85°C, V
F = 2.7V to 5.5V, 0°C to +70°C, V
FA = 2.7V to 5.5V, 0°C to +70°C, V

= 4.5-4.75

TRIP

TRIP

TRIP

TRIP

TRIP

TRIP

G = 2.7V to 5.5V, -40°C to +85°C, V
GA = 2.7V to 5.5V, -40°C to +85°C, V

= 4.25-4.5

= 4.25-4.5

= 4.5-4.75

= 2.55-2.7

= 2.85-3.0

= 2.55-2.7

TRIP

= 2.85-3.0

TRIP

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

20

FN8128.1

May 16, 2005