intersil X5043, X5045 DATA SHEET

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X5043, X5045

4K, 512 x 8 Bit

Data Sheet September 16, 2005

CPU Supervisor with 4K SPI EEPROM

These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET time. This allows the power supply and oscillator to stabilize before the processor executes code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

system from low voltage conditions, resetting the system when V RESET

falls below the minimum VCC trip point.

/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard V thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

/RESET active for a period of

/RESET signal. The user

detection circuitry protects the user’s

TRIP

™

cell,

FN8126.1

Features

•Low VCC Detection and Reset Assertion

- Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

- Re-program low V

reset threshold voltage using

special programming sequence.

- Reset signal valid to V

= 1V

• Selectable Time Out Watchdog Timer

• Long Battery Life with Low Power Consumption

- <50µA max standby current, watchdog on

- <10µA max standby current, watchdog off

• 4Kbits of EEPROM–1M Write Cycle Endurance

™

• Save Critical Data with Block Lock

Memory

- Protect 1/4, 1/2, all or none of EEPROM array

• Built-in Inadvertent Write Protection

- Write enable latch

- Write protect pin

• SPI Interface - 3.3MHz Clock Rate

• Minimize Programming Time

- 16-byte page write mode

- 5ms write cycle time (typical)

• Available Packages

- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP

- 14 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Communications Equipment

- Routers, Hubs, Switches

- Set Top Boxes

• Industrial Systems

- Process Control

- Intelligent Instrumentation

• Computer Systems

- Desktop Computers

- Network Servers

• Battery Powered Equipment

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Typical Application

X5043, X5045

2.7-5.0V

Block Diagram

CS/WDI

SCK

TRIP

X5043

VCC

RESET

SCK

VSS

Watchdog

Transition

Command

Decode &

Protect Logic

10K

Detector

Control

Logic

VCC

RESET

SPI

VSS

POR and Low Voltage Reset

Generation

Reset & Watchdog

Timebase

Watchdog

Timer Reset

Status

EEPROM

Array

4Kbits

RESET (X5043) RESET (X5045)

STANDARD V

See “Ordering Information” on page 3. for more details For Custom Settings, call Intersil.

X5043, X5045

LEVEL SUFFIX

TRIP

4.63V (+/-2.5%) -4.5A

4.38V (+/-2.5%) -4.5

2.93V (+/-2.5%) -2.7A

2.63V (+/-2.5%) -2.7

FN8126.1

September 16, 2005

X5043, X5045

Ordering Information

PART NUMBER

RESET

(ACTIVE LOW)

X5043P-4.5A X5045P-4.5A 4.5-5.5V 4.5-4.75 0 to 70 8 Ld PDIP

X5043PZ-4.5A (Note) X5045PZ-4.5A (Note) 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-4.5A X5045PI-4.5A -40 to 85 8 Ld PDIP

X5043PIZ-4.5A (Note) X5045PIZ-4.5A (Note) X5045P Z AM -40 to 85 8 Ld PDIP (Pb-free)

X5043S8-4.5A X5043 AL X5045S8-4.5A X5045 AL 0 to 70 8 Ld SOIC

X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A

X5043S8I-4.5A* X5043 AM X5045S8I-4.5A* X5045 AM -40 to 85 8 Ld SOIC

X5043S8IZ-4.5A* (Note)

X5043M8-4.5A AEM X5045M8-4.5A AEV 0 to 70 8 Ld MSOP

X5043M8Z-4.5A (Note)

X5043M8I-4.5A* AEN X5045M8I-4.5A AEW -40 to 85 8 Ld MSOP

X5043M8IZ-4.5A (Note)

X5043V14I-4.5A X5045V14I-4.5A -40 to 85 14 Ld TSSOP

X5043P X5043P X5045P X5045P 4.25-4.5 0 to 70 8 Ld PDIP

X5043PZ (Note) X5043P Z X5045PZ (Note) X5045P Z 0 to 70 8 Ld PDIP (Pb-free)

X5043PI X5043P I X5045PI X5045P I -40 to 85 8 Ld PDIP

X5043PIZ (Note) X5043P Z I X5045PIZ (Note) X5045P Z I -40 to 85 8 Ld PDIP (Pb-free)

X5043ST1 - - 0 to 70 8 Ld SOIC Tape and

X5043ST2 - - 0 to 70

X5043S8* X5043 X5045S8* X5045 0 to 70 8 Ld SOIC

X5043S8Z* (Note) X5043 Z X5045S8Z* (Note) X5045 Z 0 to 70 8 Ld SOIC (Pb-free)

X5043S8I* X5043 I X5045S8I* X5045 I -40 to 85 8 Ld SOIC

X5043S8IZ* (Note) X5043 Z I X5045S8IZ* (Note) X5045 Z I -40 to 85 8 Ld SOIC (Pb-free)

X5043SM* - - 0 to 70 8 Ld SOIC

- - X5045SMT1 0 to 70 8 Ld SOIC Tape and

X5043M8 AEO X5045M8 AEX 0 to 70 8 Ld MSOP

X5043M8Z (Note) DBN X5045M8Z (Note) DBY 0 to 70 8 Ld MSOP (Pb-free)

X5043M8I AEP X5045M8I AEY -40 to 85 8 Ld MSOP

X5043M8IZ (Note) DBJ X5045M8IZ (Note) DBT -40 to 85 8 Ld MSOP (Pb-free)

X5043V - 0 to 70 14 Ld TSSOP

X5043V14I X5045V14I -40 to 85 14 Ld TSSOP

PART

MARKING

X5043 Z AM X5045S8IZ-4.5A*

DBS X5045M8Z-4.5A

DBM X5045M8IZ-4.5A

PART NUMBER

RESET

(ACTIVE HIGH)

(Note)

PART

MARKING

X5045 Z AL 0 to 70 8 Ld SOIC (Pb-free)

X5045 Z AM -40 to 85 8 Ld SOIC (Pb-free)

DCA 0 to 70 8 Ld MSOP (Pb-free)

DBX -40 to 85 8 Ld MSOP (Pb-free)

RANGE

TRIP

RANGE

TEMP

RANGE

(°C) PACKAGE

Reel

FN8126.1

September 16, 2005

X5043, X5045

Ordering Information (Continued)

PART NUMBER

RESET

(ACTIVE LOW)

X5043P-2.7A X5043P AN X5045P-2.7A X5045P AN 2.7-5.5V 2.85-3.0 0 to 70 8 Ld PDIP

X5043PZ-2.7A (Note) X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-2.7A X5043P AP X5045PI-2.7A X5045P AP -40 to 85 8 Ld PDIP

X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP -40 to 85 8 Ld PDIP (Pb-free)

X5043S8-2.7A* X5043 AN X5045S8-2.7A X5045 AN 0 to 70 8 Ld SOIC

X5043S8Z-2.7A* (Note)

X5043S8I-2.7A* X5043 AP X5045S8I-2.7A X5045 AP -40 to 85 8 Ld SOIC

X5043S8IZ-2.7A* (Note)

X5043M8-2.7A* AEQ X5045M8-2.7A AEZ 0 to 70 8 Ld MSOP

X5043M8Z-2.7A (Note)

X5043M8I-2.7A* AER X5045M8I-2.7A AFA -40 to 85 8 Ld MSOP

X5043M8IZ-2.7A* (Note)

X5043V14I-2.7A X5045V14I-2.7A -40 to 85 14 Ld TSSOP

X5043P-2.7 X5043P F X5045P-2.7 X5045P F 2.55-2.7 0 to 70 8 Ld PDIP

X5043PZ-2.7 (Note) X5043P Z F X5045PZ-2.7 (Note) X5045P Z F 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-2.7 X5043P G X5045PI-2.7 X5045P G -40 to 85 8 Ld PDIP

X5043PIZ-2.7 (Note) X5043P Z G X5045PIZ-2.7 (Note) X5045P Z G -40 to 85 8 Ld PDIP (pb-free)

- - X5045S-2.7* 0 to 70 8 Ld SOIC

- - X5045SI-2.7* -40 to 85 8 Ld SOIC

X5043S8-2.7* X5043 F X5045S8-2.7* X5045 F 0 to 70 8 Ld SOIC

X5043S8Z-2.7* (Note) X5043 Z F X5045S8Z-2.7* (Note) X5045 Z F 0 to 70 8 Ld SOIC (Pb-free)

X5043S8I-2.7* X5043 G X5045S8I-2.7* X5045 G -40 to 85 8 Ld SOIC

X5043S8IZ-2.7* (Note) X5043 Z G X5045S8IZ-2.7*

X5043M8-2.7 AES X5045M8-2.7 AFB 0 to 70 8 Ld MSOP

X5043M8Z-2.7 (Note) DBP X5045M8Z-2.7 (Note) DBZ 0 to 70 8 Ld MSOP (Pb-free)

X5043M8I-2.7* AET X5045M8I-2.7 AFC -40 to 85 8 Ld MSOP

X5043M8IZ-2.7* (Note)

X5043V14I-2.7 X5043V G X5045V14I-2.7 X5045V G -40 to 85 14 Ld TSSOP

*Add "-T1" suffix for tape and reel.

PART

MARKING

X5043 Z AN X5045S8Z-2.7A

X5043 Z AP X5045S8IZ-2.7A

DBR X5045M8Z-2.7A

DBL X5045M8IZ-2.7A

DBK X5045M8IZ-2.7*

PART NUMBER

RESET

(ACTIVE HIGH)

(Note)

PART

MARKING

X5045 Z AN 0 to 70 8 Ld SOIC (Pb-free)

X5045 Z AP -40 to 85 8 Ld SOIC

DCA 0 to 70 8 Ld MSOP (Pb-free)

DBW -40 to 85 8 Ld MSOP (Pb-free)

X5045 Z G -40 to 85 8 Ld SOIC (Pb-free)

DBU -40 to 85 8 Ld MSOP (Pb-free)

RANGE

TRIP

RANGE

TEMP

RANGE

(°C) PACKAGE

(Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8126.1

September 16, 2005

X5043, X5045

Pin Configuration

8 Ld SOIC/PDIP/MSOP

/WDI

CS SO NC

1 2

X5043, X5045

3 4

14 Ld TSSOP

1 2

X5043, X5045

4 5 6 7

14 13

12 11 10

8 7

6 5

9 8

RESET SCK SI

RESET NC NC

NC SCK SI

/RESET

Pin Descriptions

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.

Chip Select (CS/WDI)

When CS is high, the X5043, X5045 are deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043, X5045 will be in the standby power mode. CS placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS to the start of any operation.

Write Protect (WP)

When WP is low, nonvolatile writes to the X5043, X5045 are disabled, but the part otherwise functions normally. When WP

is held high, all functions, including non volatile writes operate normally. WP interrupt a write to the X5043, X5045. If the internal write

low enables the X5043, X5045,

is required prior

going low while CS is still low will

cycle has already been initiated, WP

going low will have no

affect on a write.

Reset (RESET, RESET)

X5043, X5045, RESET/RESET is an active low/HIGH, open drain output which goes active whenever V minimum V rises above the minimum V RESET enabled and CS

sense level. It will remain active until VCC

sense level for 200ms.

/RESET also goes active if the Watchdog timer is

remains either high or low longer than the

Watchdog time out period. A falling edge of CS

falls below the

will reset the

watchdog timer.

Pin Names

SYMBOL DESCRIPTION

/WDI Chip Select Input

SO Serial Output

SI Serial Input

SCK Serial Clock Input

WP Write Protect Input

RESET

/RESET Reset Output

Ground

Supply Voltage

Principles of Operation

Power-on Reset

Application of power to the X5043, X5045 activate a Poweron Reset Circuit. This circuit pulls the RESET active. RESET

/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V V

value for 200ms (nominal) the circuit releases

TRIP

RESET

/RESET, allowing the processor to begin executing

code.

Low Voltage Monitoring

During operation, the X5043, X5045 monitor the VCC level and asserts RESET preset minimum V

/RESET if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

the microprocessor from operating in a power fail or brownout condition. The RESET

/RESET signal remains active until the voltage drops below 1V. It also remains active until V

returns and exceeds V

for 200ms.

TRIP

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS RESET

/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With

/WDI pin periodically to prevent an active

/RESET pin

exceeds the device

FN8126.1

September 16, 2005

X5043, X5045

no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure.

VCC Threshold Reset Procedure

The X5043, X5045 are shipped with a standard VCC threshold (V normal operating and storage conditions. However, in applications where the standard V if higher precision is needed in the V X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.

Setting the V

This procedure is used to set the V value. For example, if the current V V

is 4.6V, this procedure will directly make the change. If

TRIP

the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.

To set the new V threshold voltage to the VCC pin and tie the WP pin to the programming voltage V followed by a write of Data 00h to address 01h. CS HIGH on the write operation initiates the V sequence. Bring WP

) voltage. This value will not change over

TRIP

is not exactly right, or

TRIP

value, the X5043,

TRIP

Voltage

TRIP

to a higher voltage

TRIP

is 4.4V and the new

TRIP

voltage, apply the desired V

TRIP

. Then send a WREN command,

programming

TRIP

LOW to complete the operation.

TRIP

going

address 03h. CS the V

TRIP

going HIGH on the write operation initiates

programming sequence. Bring WP LOW to

complete the operation.

Note: This operation also writes 00h to array address 03h.

Note: This operation also writes 00h to array address 01h.

Resetting the V

This procedure is used to set the V level. For example, if the current V V

must be 4.0V, then the V

TRIP

is reset, the new V

TRIP

Voltage

to a “native” voltage

TRIP

is 4.4V and the new

TRIP

must be reset. When

TRIP

is something less than 1.7V.

TRIP

This procedure must be used to set the voltage to a lower value.

To reset the V and tie the WP

voltage, apply at least 3V to the V

TRIP

pin to the programming voltage VP. Then

send a WREN command, followed by a write of Data 00h to

01234567

SCK

06h

WREN Write Address Data

012345678910 12 1314 15

VP = 15-18V

02h

8 Bits

01h

00h

FIGURE 1. SET V

LEVEL SEQUENCE (V

TRIP

= DESIRED V

TRIP

VAL U E.)

FN8126.1

September 16, 2005

X5043, X5045

SCK

TRIP

Adj.

VP = 15-18V

01234567

012345678910 12 13 14 15

8 Bits

06h

WREN

FIGURE 2. RESET V

TRIP

02h

Write

03h

Address Data

LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)

00h

4.7K

Adjust

Run

1 2 3 4

X5043 X5045

8 7 6 5

RESET

µC

SCK SI

FIGURE 3. SAMPLE V

RESET CIRCUIT

TRIP

FN8126.1

September 16, 2005

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