intersil X5043, X5045 DATA SHEET

查询X5043供应商

X5043, X5045

4K, 512 x 8 Bit

Data Sheet September 16, 2005

CPU Supervisor with 4K SPI EEPROM

These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power-on reset circuit which holds RESET time. This allows the power supply and oscillator to stabilize before the processor executes code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

system from low voltage conditions, resetting the system when V RESET

falls below the minimum VCC trip point.

/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard V thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.

/RESET active for a period of

/RESET signal. The user

detection circuitry protects the user’s

TRIP

™

cell,

FN8126.1

Features

•Low VCC Detection and Reset Assertion

- Four standard reset threshold voltages

4.63V, 4.38V, 2.93V, 2.63V

- Re-program low V

reset threshold voltage using

special programming sequence.

- Reset signal valid to V

= 1V

• Selectable Time Out Watchdog Timer

• Long Battery Life with Low Power Consumption

- <50µA max standby current, watchdog on

- <10µA max standby current, watchdog off

• 4Kbits of EEPROM–1M Write Cycle Endurance

™

• Save Critical Data with Block Lock

Memory

- Protect 1/4, 1/2, all or none of EEPROM array

• Built-in Inadvertent Write Protection

- Write enable latch

- Write protect pin

• SPI Interface - 3.3MHz Clock Rate

• Minimize Programming Time

- 16-byte page write mode

- 5ms write cycle time (typical)

• Available Packages

- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP

- 14 Ld TSSOP

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Communications Equipment

- Routers, Hubs, Switches

- Set Top Boxes

• Industrial Systems

- Process Control

- Intelligent Instrumentation

• Computer Systems

- Desktop Computers

- Network Servers

• Battery Powered Equipment

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Typical Application

X5043, X5045

2.7-5.0V

Block Diagram

CS/WDI

SCK

TRIP

X5043

VCC

RESET

SCK

VSS

Watchdog

Transition

Command

Decode &

Protect Logic

10K

Detector

Control

Logic

VCC

RESET

SPI

VSS

POR and Low Voltage Reset

Generation

Reset & Watchdog

Timebase

Watchdog

Timer Reset

Status

EEPROM

Array

4Kbits

RESET (X5043) RESET (X5045)

STANDARD V

See “Ordering Information” on page 3. for more details For Custom Settings, call Intersil.

X5043, X5045

LEVEL SUFFIX

TRIP

4.63V (+/-2.5%) -4.5A

4.38V (+/-2.5%) -4.5

2.93V (+/-2.5%) -2.7A

2.63V (+/-2.5%) -2.7

FN8126.1

September 16, 2005

X5043, X5045

Ordering Information

PART NUMBER

RESET

(ACTIVE LOW)

X5043P-4.5A X5045P-4.5A 4.5-5.5V 4.5-4.75 0 to 70 8 Ld PDIP

X5043PZ-4.5A (Note) X5045PZ-4.5A (Note) 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-4.5A X5045PI-4.5A -40 to 85 8 Ld PDIP

X5043PIZ-4.5A (Note) X5045PIZ-4.5A (Note) X5045P Z AM -40 to 85 8 Ld PDIP (Pb-free)

X5043S8-4.5A X5043 AL X5045S8-4.5A X5045 AL 0 to 70 8 Ld SOIC

X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A

X5043S8I-4.5A* X5043 AM X5045S8I-4.5A* X5045 AM -40 to 85 8 Ld SOIC

X5043S8IZ-4.5A* (Note)

X5043M8-4.5A AEM X5045M8-4.5A AEV 0 to 70 8 Ld MSOP

X5043M8Z-4.5A (Note)

X5043M8I-4.5A* AEN X5045M8I-4.5A AEW -40 to 85 8 Ld MSOP

X5043M8IZ-4.5A (Note)

X5043V14I-4.5A X5045V14I-4.5A -40 to 85 14 Ld TSSOP

X5043P X5043P X5045P X5045P 4.25-4.5 0 to 70 8 Ld PDIP

X5043PZ (Note) X5043P Z X5045PZ (Note) X5045P Z 0 to 70 8 Ld PDIP (Pb-free)

X5043PI X5043P I X5045PI X5045P I -40 to 85 8 Ld PDIP

X5043PIZ (Note) X5043P Z I X5045PIZ (Note) X5045P Z I -40 to 85 8 Ld PDIP (Pb-free)

X5043ST1 - - 0 to 70 8 Ld SOIC Tape and

X5043ST2 - - 0 to 70

X5043S8* X5043 X5045S8* X5045 0 to 70 8 Ld SOIC

X5043S8Z* (Note) X5043 Z X5045S8Z* (Note) X5045 Z 0 to 70 8 Ld SOIC (Pb-free)

X5043S8I* X5043 I X5045S8I* X5045 I -40 to 85 8 Ld SOIC

X5043S8IZ* (Note) X5043 Z I X5045S8IZ* (Note) X5045 Z I -40 to 85 8 Ld SOIC (Pb-free)

X5043SM* - - 0 to 70 8 Ld SOIC

- - X5045SMT1 0 to 70 8 Ld SOIC Tape and

X5043M8 AEO X5045M8 AEX 0 to 70 8 Ld MSOP

X5043M8Z (Note) DBN X5045M8Z (Note) DBY 0 to 70 8 Ld MSOP (Pb-free)

X5043M8I AEP X5045M8I AEY -40 to 85 8 Ld MSOP

X5043M8IZ (Note) DBJ X5045M8IZ (Note) DBT -40 to 85 8 Ld MSOP (Pb-free)

X5043V - 0 to 70 14 Ld TSSOP

X5043V14I X5045V14I -40 to 85 14 Ld TSSOP

PART

MARKING

X5043 Z AM X5045S8IZ-4.5A*

DBS X5045M8Z-4.5A

DBM X5045M8IZ-4.5A

PART NUMBER

RESET

(ACTIVE HIGH)

(Note)

PART

MARKING

X5045 Z AL 0 to 70 8 Ld SOIC (Pb-free)

X5045 Z AM -40 to 85 8 Ld SOIC (Pb-free)

DCA 0 to 70 8 Ld MSOP (Pb-free)

DBX -40 to 85 8 Ld MSOP (Pb-free)

RANGE

TRIP

RANGE

TEMP

RANGE

(°C) PACKAGE

Reel

FN8126.1

September 16, 2005

X5043, X5045

Ordering Information (Continued)

PART NUMBER

RESET

(ACTIVE LOW)

X5043P-2.7A X5043P AN X5045P-2.7A X5045P AN 2.7-5.5V 2.85-3.0 0 to 70 8 Ld PDIP

X5043PZ-2.7A (Note) X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-2.7A X5043P AP X5045PI-2.7A X5045P AP -40 to 85 8 Ld PDIP

X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP -40 to 85 8 Ld PDIP (Pb-free)

X5043S8-2.7A* X5043 AN X5045S8-2.7A X5045 AN 0 to 70 8 Ld SOIC

X5043S8Z-2.7A* (Note)

X5043S8I-2.7A* X5043 AP X5045S8I-2.7A X5045 AP -40 to 85 8 Ld SOIC

X5043S8IZ-2.7A* (Note)

X5043M8-2.7A* AEQ X5045M8-2.7A AEZ 0 to 70 8 Ld MSOP

X5043M8Z-2.7A (Note)

X5043M8I-2.7A* AER X5045M8I-2.7A AFA -40 to 85 8 Ld MSOP

X5043M8IZ-2.7A* (Note)

X5043V14I-2.7A X5045V14I-2.7A -40 to 85 14 Ld TSSOP

X5043P-2.7 X5043P F X5045P-2.7 X5045P F 2.55-2.7 0 to 70 8 Ld PDIP

X5043PZ-2.7 (Note) X5043P Z F X5045PZ-2.7 (Note) X5045P Z F 0 to 70 8 Ld PDIP (Pb-free)

X5043PI-2.7 X5043P G X5045PI-2.7 X5045P G -40 to 85 8 Ld PDIP

X5043PIZ-2.7 (Note) X5043P Z G X5045PIZ-2.7 (Note) X5045P Z G -40 to 85 8 Ld PDIP (pb-free)

- - X5045S-2.7* 0 to 70 8 Ld SOIC

- - X5045SI-2.7* -40 to 85 8 Ld SOIC

X5043S8-2.7* X5043 F X5045S8-2.7* X5045 F 0 to 70 8 Ld SOIC

X5043S8Z-2.7* (Note) X5043 Z F X5045S8Z-2.7* (Note) X5045 Z F 0 to 70 8 Ld SOIC (Pb-free)

X5043S8I-2.7* X5043 G X5045S8I-2.7* X5045 G -40 to 85 8 Ld SOIC

X5043S8IZ-2.7* (Note) X5043 Z G X5045S8IZ-2.7*

X5043M8-2.7 AES X5045M8-2.7 AFB 0 to 70 8 Ld MSOP

X5043M8Z-2.7 (Note) DBP X5045M8Z-2.7 (Note) DBZ 0 to 70 8 Ld MSOP (Pb-free)

X5043M8I-2.7* AET X5045M8I-2.7 AFC -40 to 85 8 Ld MSOP

X5043M8IZ-2.7* (Note)

X5043V14I-2.7 X5043V G X5045V14I-2.7 X5045V G -40 to 85 14 Ld TSSOP

*Add "-T1" suffix for tape and reel.

PART

MARKING

X5043 Z AN X5045S8Z-2.7A

X5043 Z AP X5045S8IZ-2.7A

DBR X5045M8Z-2.7A

DBL X5045M8IZ-2.7A

DBK X5045M8IZ-2.7*

PART NUMBER

RESET

(ACTIVE HIGH)

(Note)

PART

MARKING

X5045 Z AN 0 to 70 8 Ld SOIC (Pb-free)

X5045 Z AP -40 to 85 8 Ld SOIC

DCA 0 to 70 8 Ld MSOP (Pb-free)

DBW -40 to 85 8 Ld MSOP (Pb-free)

X5045 Z G -40 to 85 8 Ld SOIC (Pb-free)

DBU -40 to 85 8 Ld MSOP (Pb-free)

RANGE

TRIP

RANGE

TEMP

RANGE

(°C) PACKAGE

(Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8126.1

September 16, 2005

X5043, X5045

Pin Configuration

8 Ld SOIC/PDIP/MSOP

/WDI

CS SO NC

1 2

X5043, X5045

3 4

14 Ld TSSOP

1 2

X5043, X5045

4 5 6 7

14 13

12 11 10

8 7

6 5

9 8

RESET SCK SI

RESET NC NC

NC SCK SI

/RESET

Pin Descriptions

Serial Output (SO)

SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input.

Chip Select (CS/WDI)

When CS is high, the X5043, X5045 are deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043, X5045 will be in the standby power mode. CS placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS to the start of any operation.

Write Protect (WP)

When WP is low, nonvolatile writes to the X5043, X5045 are disabled, but the part otherwise functions normally. When WP

is held high, all functions, including non volatile writes operate normally. WP interrupt a write to the X5043, X5045. If the internal write

low enables the X5043, X5045,

is required prior

going low while CS is still low will

cycle has already been initiated, WP

going low will have no

affect on a write.

Reset (RESET, RESET)

X5043, X5045, RESET/RESET is an active low/HIGH, open drain output which goes active whenever V minimum V rises above the minimum V RESET enabled and CS

sense level. It will remain active until VCC

sense level for 200ms.

/RESET also goes active if the Watchdog timer is

remains either high or low longer than the

Watchdog time out period. A falling edge of CS

falls below the

will reset the

watchdog timer.

Pin Names

SYMBOL DESCRIPTION

/WDI Chip Select Input

SO Serial Output

SI Serial Input

SCK Serial Clock Input

WP Write Protect Input

RESET

/RESET Reset Output

Ground

Supply Voltage

Principles of Operation

Power-on Reset

Application of power to the X5043, X5045 activate a Poweron Reset Circuit. This circuit pulls the RESET active. RESET

/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V V

value for 200ms (nominal) the circuit releases

TRIP

RESET

/RESET, allowing the processor to begin executing

code.

Low Voltage Monitoring

During operation, the X5043, X5045 monitor the VCC level and asserts RESET preset minimum V

/RESET if supply voltage falls below a

. The RESET/RESET signal prevents

TRIP

the microprocessor from operating in a power fail or brownout condition. The RESET

/RESET signal remains active until the voltage drops below 1V. It also remains active until V

returns and exceeds V

for 200ms.

TRIP

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS RESET

/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With

/WDI pin periodically to prevent an active

/RESET pin

exceeds the device

FN8126.1

September 16, 2005

X5043, X5045

no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure.

VCC Threshold Reset Procedure

The X5043, X5045 are shipped with a standard VCC threshold (V normal operating and storage conditions. However, in applications where the standard V if higher precision is needed in the V X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal.

Setting the V

This procedure is used to set the V value. For example, if the current V V

is 4.6V, this procedure will directly make the change. If

TRIP

the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value.

To set the new V threshold voltage to the VCC pin and tie the WP pin to the programming voltage V followed by a write of Data 00h to address 01h. CS HIGH on the write operation initiates the V sequence. Bring WP

) voltage. This value will not change over

TRIP

is not exactly right, or

TRIP

value, the X5043,

TRIP

Voltage

TRIP

to a higher voltage

TRIP

is 4.4V and the new

TRIP

voltage, apply the desired V

TRIP

. Then send a WREN command,

programming

TRIP

LOW to complete the operation.

TRIP

going

address 03h. CS the V

TRIP

going HIGH on the write operation initiates

programming sequence. Bring WP LOW to

complete the operation.

Note: This operation also writes 00h to array address 03h.

Note: This operation also writes 00h to array address 01h.

Resetting the V

This procedure is used to set the V level. For example, if the current V V

must be 4.0V, then the V

TRIP

is reset, the new V

TRIP

Voltage

to a “native” voltage

TRIP

is 4.4V and the new

TRIP

must be reset. When

TRIP

is something less than 1.7V.

TRIP

This procedure must be used to set the voltage to a lower value.

To reset the V and tie the WP

voltage, apply at least 3V to the V

TRIP

pin to the programming voltage VP. Then

send a WREN command, followed by a write of Data 00h to

01234567

SCK

06h

WREN Write Address Data

012345678910 12 1314 15

VP = 15-18V

02h

8 Bits

01h

00h

FIGURE 1. SET V

LEVEL SEQUENCE (V

TRIP

= DESIRED V

TRIP

VAL U E.)

FN8126.1

September 16, 2005

X5043, X5045

SCK

TRIP

Adj.

VP = 15-18V

01234567

012345678910 12 13 14 15

8 Bits

06h

WREN

FIGURE 2. RESET V

TRIP

02h

Write

03h

Address Data

LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)

00h

4.7K

Adjust

Run

1 2 3 4

X5043 X5045

8 7 6 5

RESET

µC

SCK SI

FIGURE 3. SAMPLE V

RESET CIRCUIT

TRIP

FN8126.1

September 16, 2005

Programming

TRIP

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

TRIP

X5043, X5045

SPI Serial Memory

The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock is internally organized as 512 x 8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.

The device utilizes Intersil’s proprietary Direct Write providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.

protection. The array

™

cell,

New VCC Applied

Applied

Old V

- Error

Error ≤ -Emax

Execute

Set V

TRIP

Sequence

Apply 5V to V

Decrement V

= VCC–10mV)

RESET pin

goes active?

Measured V

-Desired V

Emax = Maximum Desired Error

YES

TRIP

-Emax < Error < Emax

DONE

New V

Applied

Old V

- Error

Execute

Reset V

TRIP

Sequence

Error ≥ Emax

The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families.

The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first.

Clock and Data Timing

Data input on the SI line is latched on the first rising edge of SCK after CS the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS

goes LOW. Data is output on the SO line by

must be LOW during the entire operation.

FIGURE 4. V

INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION

WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)

WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)

RSDR 0000 0101 Read Status Register

WRSR 0000 0001 Write Status Register (Watchdog and Block Lock)

READ 0000 A

WRITE 0000 A

Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

PROGRAMMING SEQUENCE

TRIP

011 Read Data from Memory Array Beginning at Selected Address

010 Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)

TABLE 1. INSTRUCTION SET

FN8126.1

September 16, 2005

X5043, X5045

Write Enable Latch

The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 5). This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycle. The latch is also reset if WP is brought LOW.

When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data.

01234567

SCK

FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE

High Impedance

(WREN/WRDI INSTRUCTION)

Status Register

The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The Status Register is formatted as shown in “Status Register”.

Status Register: (Default = 30H)

7 6543210

00WD1WD0BL1BL0WELWIP

The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.

the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory.

STATUS REG BITS ARRAY ADDRESSES PROTECTED

BL1 BL0 X5043, X5045

0 0 None

0 1 $180–$1FF

1 0 $100–$1FF

1 1 $000–$1FF

The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction.

STATUS REGISTER BITS

0 0 1.4 seconds

0 1 600 milliseconds

1 0 200 milliseconds

1 1 disabled (factory default)

WATCHDOG TIME OUT

(TYPICAL)WD1 WD0

Read Status Register

To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence (Figure

6). The Status Register may be read at any time, even during a Write Cycle.

Write Status Register

Prior to any attempt to write data into the status register, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS the WREN instruction into the device and pull CS Then bring CS

LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS

going HIGH. If CS does not go HIGH between WREN

and WRSR, the WRSR instruction is ignored.

LOW, then clock

HIGH.

The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit.

The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of

FN8126.1

September 16, 2005

X5043, X5045

TABLE 2. DEVICE PROTECT MATRIX

WREN CMD

(WEL) DEVICE PIN (WP)

0 x Protected Protected Protected

x 0 Protected Protected Protected

1 1 Protected Writable Writable

PROTECTED AREA UNPROTECTED AREA (BL0, BL1, WD0, WD1)

MEMORY BLOCK STATUS REGISTER

SCK

01234567891011121314

Instruction

High Impedance

FIGURE 6. READ STATUS REGISTER SEQUENCE

0123456789

Instruction

76543210

MSB

76543210

Data Out

10 11 12 13 14 15

Data Byte

High Impedance

FIGURE 7. WRITE STATUS REGISTER SEQUENCE

FN8126.1

September 16, 2005

X5043, X5045

Read Memory Array

When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 8-bit address. Bit 3 of the READ instruction selects the upper or lower half of the device. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address 000h allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS

high. Refer to the Read EEPROM Array

Sequence (Figure 8).

Write Memory Array

Prior to any attempt to write data into the memory array, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS the WREN instruction into the device and pull CS Then bring CS

LOW again and enter the WRITE instruction followed by the 8-bit address and then the data to be written. Bit 3 of the WRITE instruction contains address bit A selects the upper or lower half of the array. If CS HIGH between WREN and WRITE, the WRITE instruction is ignored.

LOW, then clock

HIGH.

, which

does not go

For the write operation (byte or page write) to be completed, CS

must be brought HIGH after bit 0 of the last complete data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 9).

While the write is in progress following a status register or memory array write sequence, the Status Register may be read to check the WIP bit. WIP is HIGH while the nonvolatile write is in progress.

The WRITE operation requires at least 16 clocks. CS

must go low and remain low for the duration of the operation. The host may continue to write up to 16 bytes of data. The only restriction is that the 16 bytes must reside within the same page. A page address begins with address [x xxxx 0000] and ends with [x xxxx 1111]. If the by t e a d d r e s s reaches the last byte on the page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that has been previously written.

0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22

SCK

Instruction 8 Bit Address

765 3210

9th Bit of Address

High Impedance

FIGURE 8. READ EEPROM ARRAY SEQUENCE

Data Out

76543210

MSB

FN8126.1

September 16, 2005

X5043, X5045

012345678910

SCK

Instruction 8 Bit Address

24 25 26 27 28 29 30 31

SCK

Data Byte 2

76543210

Operational Notes

The device powers-up in the following state:

12 13 14 15 16 17 18 19 20 21 22 23

9th Bit of Address

FIGURE 9. WRITE MEMORY SEQUENCE

765 3210

32 33 34 35 36 37 38 39

Data Byte 3

76543210

Data Byte 1

76543210

Data Byte N

654 3210

1. The device is in the low power standby state.

2. A HIGH to LOW transition on CS

is required to enter an

active state and receive an instruction.

3. SO pin is high impedance.

4. The Write Enable Latch is reset.

5. The Flag Bit is reset.

6. Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent inadvertent writes:

• A WREN instruction must be issued to set the Write

Enable Latch.

•CS

must come HIGH at the proper clock count in order to

start a nonvolatile write cycle.

• Block Protect bits provide additional level of write

protection for the memory array.

•The WP

pin LOW blocks nonvolatile write operations.

FN8126.1

September 16, 2005

X5043, X5045

Absolute Maximum Ratings Recommended Operating Conditions

Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on any pin with respect to V

D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)

SYMBOL PARAMETER TEST CONDITIONS/COMMENTS

(3)

; SO, RESET, RESET = Open 3 mA

(3)

; SI = VSS, RESET, RESET =

CC1

CC2

SB1

SB2

OH1

OH2

OH3

OLRS

VCC Write Current (Active) SCK = 3.3MHz

VCC Read Current (Active) SCK = 3.3MHz

Open

VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC=5.5V 10 µA

VCC Standby Current WDT = ON CS = VCC, SCK, SI = VSS, VCC=5.5V 50 µA

Input Leakage Current SCK, SI, WP = VSS to VCC 0.1 10 µA

Output Leakage Current SO, RESET, RESET = VSS to V

(1)

Input LOW Voltage SCK, SI, WP, CS -0.5 V

(1)

Input HIGH Voltage SCK, SI, WP, CS V

Output LOW Voltage (SO) IOL = 2mA @ VCC = 2.7V

= 0.5mA @ VCC = 1.8V

Output HIGH Voltage (SO) VCC > 3.3V, IOH = –1.0mA V

Output HIGH Voltage (SO) 2V < VCC ≤ 3.3V, IOH = –0.4mA V

Output HIGH Voltage (SO) VCC ≤ 2V, IOH = –0.25mA V

Output LOW Voltage (RESET,

= 1mA 0.4 V

RESET)

Temperature:

Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage:

-2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

LIMITS

(2)

MAX

UNITMIN TYP

2mA

x 0.7 V

0.1 10 µA

x 0.3 V

+ 0.5 V

0.4 V

- 0.8 V

- 0.4 V

- 0.2 V

Capacitance T

= +25°C, f = 1MHz, VCC = 5V

SYMBOL TEST CONDITIONS MAX UNIT

(2)

OUT

Output Capacitance (SO, RESET, RESET) V

(2)

Input Capacitance (SCK, SI, CS, WP)V

= 0V 8 pF

OUT

= 0V 6 pF

NOTES:

min. and VIH max. are for reference only and are not tested.

1. V

2. This parameter is periodically sampled and not 100% tested.

3. SCK frequency measured from V

x 0.1/VCC x 0.9

September 16, 2005

FN8126.1

X5043, X5045

Equivalent A.C. Load Circuit at 5V V

A.C. Test Conditions

Input pulse levels VCC x 0.1 to VCC x 0.9

Output

1.64kΩ

RESET/RESET

30pF

4.6kΩ

30pF

Input rise and fall times 10ns

Input and output timing level V

AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)

SYMBOL PARAMETER

DATA INPUT TIMING

SCK

CYC

LEAD

LAG

(4)

(5)

Clock Frequency 0 3.3 MHz

Cycle Time 300 ns

CS Lead Time 150 ns

CS Lag Time 150 ns

Clock HIGH Time 130 ns

Clock LOW Time 130 ns

Data Setup Time 30 ns

Data Hold Time 30 ns

Input Rise Time 2µs

Input Fall Time 2µs

CS Deselect Time 100 ns

Write Cycle Time 10 ms

2.7V–5.5V

x 0.5

UNITMIN MAX

Data Output Timing

2.7–5.5V

SYMBOL PARAMETER

SCK

DIS

NOTES:

4. This parameter is periodically sampled and not 100% tested.

5. t

Clock Frequency 0 3.3 MHz

Output Disable Time 150 ns

Output Valid from Clock Low 120 ns

Output Hold Time 0 ns

(4)

Output Rise Time 50 ns

(4)

Output Fall Time 50 ns

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

UNIT MIN MAX

FN8126.1

September 16, 2005

Serial Output Timing

X5043, X5045

SCK

Serial Input Timing

SCK

ADDR

LSB IN

CYC

MSB Out MSB–1 Out LSB Out

LEAD

tFI

LSB In

MSB In

LAG

DIS

LAG

Symbol Table

WAVEFORM INPUTS OUTPUTS

High Impedance

Must be steady

May change from LOW to HIGH

May change from HIGH to LOW

Don’t Care: Changes Allowed

Will be steady

Will change from LOW to HIGH

Will change from HIGH to LOW

Changing: State Not Known

N/A Center Line

is High Impedance

FN8126.1

September 16, 2005

Power-Up and Power-Down Timing

X5043, X5045

0 Volts

TRIP

PURST

TRIP

RPD

RESET (X5043)

RESET (X5045)

RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

PURST

RPD

RVALID

TRIP

(6)

Reset Trip Point Voltage, (-4.5A) Reset Trip Point Voltage, (Blank) Reset Trip Point Voltage, (-2.7A) Reset Trip Point Voltage, (-2.7)

4.5

4.25

2.85

2.55

4.62

4.38

2.92

2.62

Power-up Reset Time Out 100 200 400 ms

(6)

VCC Detect to Reset/Output 500 ns

VCC Fall Time 10 µs

VCC Rise Time 0.1 ns

Reset Valid V

4.75

4.5

3.0

2.7

NOTE:

6. This parameter is periodically sampled and not 100% tested.

CS/WDI vs. RESET/RESET Timing

CS/WDI

CST

RESET (5043)

RESET (5045)

WDO

RST

WDO

RST

RESET/RESET Output Timing

SYMBOL PARAMETER MIN TYP MAX UNIT

WDO

CST

RST

Watchdog Time Out Period,

WD1 = 1, WD0 = 1 (default)

WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0

100 450

OFF

200 600

1.4

300 800

CS Pulse Width to Reset the Watchdog 400 ns

Reset Time Out 100 200 400 ms

ms ms

sec

FN8126.1

September 16, 2005

Programming Timing Diagram

TRIP

)

TRIP

X5043, X5045

TRIP

TSU

THD

VPH

VPO

VPS

PCS

SCK

01h or 03h

Programming Parameters

TRIP

02h 06h

PARAMETER DESCRIPTION MIN MAX UNIT

VPS

VPH

PCS

TSU

THD

VPO

TRAN

programming parameters are periodically sampled and are not 100% tested.

TRIP

Program Enable Voltage Setup time 1 µs

TRIP

Program Enable Voltage Hold time 1 µs

TRIP

Programming CS inactive time 1 µs

TRIP

Setup time 1µs

TRIP

Hold (stable) time 10 ms

TRIP

Write Cycle Time 10 ms

TRIP

Program Enable Voltage Off time (Between successive adjustments) 0 µs

TRIP

Program Recovery Period (Between successive adjustments) 10 ms

TRIP

Programming Voltage 15 18 V

Programmed Voltage Range 1.7 4.75 V

TRIP

Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV

TRIP

FN8126.1

September 16, 2005

Packaging Information

8-Lead Miniature Small Outline Gull Wing Package Type M

0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05)

0.118 ± 0.002 (3.00 ± 0.05)

0.030 (0.76)

X5043, X5045

0.118 ± 0.002 (3.00 ± 0.05)

0.0256 (0.65) Typ.

R 0.014 (0.36)

0.0216 (0.55)

0.007 (0.18)

0.005 (0.13)

0.036 (0.91)

0.032 (0.81)

0.040 ± 0.002 (1.02 ± 0.05)

0.150 (3.81) Ref.

0.193 (4.90) Ref.

7° Typ.

0.008 (0.20)

0.004 (0.10)

0.220"

0.0256" Typical

0.025" Typical

0.020"

Typical

8 PlacesFOOTPRINT

NOTE:

1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

FN8126.1

September 16, 2005

Packaging Information

8-Lead Plastic Dual In-Line Package Type P

Pin 1 Index

Half Shoulder Width On

All End Pins Optional

Seating Plane

X5043, X5045

0.430 (10.92)

0.360 (9.14)

Pin 1

0.300

(7.62) Ref.

0.260 (6.60)

0.240 (6.10)

0.060 (1.52)

0.020 (0.51)

0.145 (3.68)

0.128 (3.25)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

.073 (1.84)

Max.

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.325 (8.25)

0.300 (7.62)

0.025 (0.64)

0.015 (0.38)

0.065 (1.65)

0.045 (1.14)

0.020 (0.51)

0.016 (0.41)

0°

15°

FN8126.1

September 16, 2005

Packaging Information

X5043, X5045

8-Lead Plastic Small Outline Gull Wing Package Type S

Pin 1 Index

(4X) 7°

0.050 (1.27)

0.010 (0.25)

0.020 (0.50)

Pin 1

X 45°

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

0.150 (3.80)

0.158 (4.00)

0.004 (0.19)

0.010 (0.25)

0.228 (5.80)

0.244 (6.20)

0.053 (1.35)

0.069 (1.75)

0.050"Typical

0° - 8°

0.0075 (0.19)

0.010 (0.25)

0.016 (0.410)

0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.030"

Typical

8 PlacesFOOTPRINT

0.050" Typical

FN8126.1

September 16, 2005

Packaging Information

X5043, X5045

14-Lead Plastic, TSSOP, Package Type V

.025 (.65) BSC

0° - 8°

.0075 (.19) .0118 (.30)

.193 (4.9) .200 (5.1)

.019 (.50) .029 (.75)

Detail A (20X)

.169 (4.3) .177 (4.5)

.047 (1.20)

.002 (.05) .006 (.15)

.010 (.25)

Gage Plane

Seating Plane

.252 (6.4) BSC

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8126.1

September 16, 2005

intersil X5043, X5045 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual