intersil X4163, X4165 DATA SHEET

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X4163, X4165

16K, 2K x 8 Bit

Data Sheet April 13, 2005

CPU Supervisor with 16K EEPROM

FEATURES

• Selectable watchdog timer

•Low V —Four standard reset threshold voltages —Adjust low V

special programming sequence

—Reset signal valid to V

• Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current

• 16Kbits of EEPROM —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)

• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block Lock (1, 2, 4, 8 pages, all, none)

• 400kHz 2-wire interface

• 2.7V to 5.5V power supply operation

• Available Packages —8-lead SOIC —8-lead TSSOP

detection and reset assertion

reset threshold voltage using

= 1V

FN8120.0

DESCRIPTION

The X4163/5 combines four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability.

Applying power to the device activates the power on reset circuit which holds RESET

/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET

/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power.

The device’s low V

detection circuitry protects the

user’s system from low voltage conditions, resetting the system when V point. RESET

falls below the set minimum VCC trip

/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard V

thresholds are available, however, Inter-

TRIP

sil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.

BLOCK DIAGRAM

SDA

SCL

S0 S1

Watchdog Transition

Data

Command

Decode &

Control

Logic

VCC Threshold

Reset logic

Detector

Protect Logic

Status

EEPROM Array

Block Lock Control

TRIP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

2Kb

Watchdog

Timer Reset

RESET (X4163) RESET (X4165)

Reset &

Watchdog

Timebase

Power on and

Low Voltage

Reset

Generation

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PIN CONFIGURATION

8-Pin JEDEC SOIC

X4163, X4165

SCL

SDA

SCL

SDA

7 6

RESET

/RESET

RESET

S S

/RESET

3 4

8 Pin TSSOP

1 2 3

PIN FUNCTION

(SOIC)

(TSSOP) Name Function

13 S0Device Select Input 24 S 35

RESET/

RESET

Device Select Input Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which

goes active whenever V active until V RESET

/RESET goes active if the Watchdog Timer is enabled and SDA remains

rises above the minimum VCC sense level for 250ms.

falls below the minimum VCC sense level. It will remain

either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes active on power up and remains active for 250ms after the power supply stabilizes.

46 V

Ground

57SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET

/RESET going active. 68 SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output. 71 WPWrite Protect. WP HIGH used in conjunction with WPEN bit prevents writes to

the control register.

82 V

Supply Voltage

/RESET

FN8120.0

April 13, 2005

X4163, X4165

PRINCIPLES OF OPERATION

Power On Reset

Application of power to the X4163/5 activates a Power On Reset Circuit that pulls the RESET

/RESET pin

active. This signal provides several benefits. – It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to sta -

bilization of the oscillator.

– It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

When V

exceeds the device V

threshold value

TRIP

for 200ms (nominal) the circuit releases RESET

/RESET allowing the system to begin operation.

LOW VOLTAGE MONITORING

During operation, the X4163/5 monitors the V and asserts RESET below a preset minimum V

/RESET if supply voltage falls

. The RESET/RESET

TRIP

level

signal prevents the microprocessor fro m operating in a power fail or brownout condition. The RESET

/RESET signal remains active until the voltage drops below 1V. It also remains active until V V

for 200ms.

TRIP

returns and exceeds

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproce ssor activity by monitoring the SDA and SCL pins. The microprocessor must toggle the SDA pin HIGH to LOW periodically, while SCL is HIGH (this is a start bit) prior to the expiration of the watchdog time out period to prevent a RESET

/RESET signal. The state of two nonvolatile control bits in the Status Register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH.

EEPROM INADVERTENT WRITE PROTECTION

When RESET

/RESET goes active as a result of a low voltage condition or Watchdog Timer Time Out, any inprogress communications are terminated. While RESET

/RESET is active, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET

/RESET

goes active are allowed to finish. Additional protection mechanisms are provided with

memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document.

THRESHOLD RESET PROCEDURE

The X4163/5 is shipped with a standard V (V

) voltage. This value will not change over normal

TRIP

threshold

operating and storage conditions. However, in applications where the standard V higher precision is needed in the V

is not exactly right, or if

TRIP

value, the

TRIP

X4163/5 threshold may be adjusted. The procedure is described below, and uses the application of a nonvolatile control signal.

Figure 1. Set V

01234567

SCL

SDA

Level Sequence (V

TRIP

A0h

= desired V

= 12-15V

01234567

00h

values WEL bit set)

TRIP

01234567

01h

01234567

00h

FN8120.0

April 13, 2005

X4163, X4165

Setting the V

This procedure is used to set the V

TRIP

Voltage

to a higher or

TRIP

lower voltage value. It is necessary to reset the trip point before setting the new value.

To set the new V bit in the control register, then apply the desired V

voltage, start by setting the WEL

TRIP

threshold voltage to the VCC pin and the programming voltage, V

to the WP pin and 2 byte addr ess and 1

byte of “00” data. The stop bit following a valid write operation initiates the V Bring WP

Figure 2. Reset V

SCL

LOW to complete the operation.

TRIP

01234567

programming sequence.

TRIP

Level Sequence (VCC > 3V. WP = 12–15V, WEL bit set)

= 12-15V

01234567

Resetting the V

This procedure is used to set th e V

TRIP

Voltage

to a “native”

TRIP

voltage level. For example, if the current V and the new V be reset. When V

must be 4.0V, then the V

TRIP

is reset, the new V

TRIP

thing less than 1.7V. This procedure must be used to set the voltage to a lower value.

To reset the new V WEL bit in the control register, apply V gramming voltage, V

voltage start by setting the

TRIP

, to the WP pin and 2 byte

address and 1 byte of “00” data. The stop bit of a valid write operation initiates the V sequence. Bring WP

01234567

LOW to complete the operation.

01234567

programming

TRIP

is 4.4V

TRIP

must

TRIP

is some-

and the pro-

SDA

Figure 3. Sample V

TRIP

Adj.

A0h

Reset Circuit

TRIP

RESET

4.7K

00h

1 2 3 4

SOIC

X4163

03h

Adjust

8 7 6 5

Run

00h

µC

SCL SDA

FN8120.0

April 13, 2005

X4163, X4165

Figure 4. V

Programming Sequence

TRIP

New VCC Applied =

Old V

Applied + Error

Programming

TRIP

Execute

Reset V

TRIP

Sequence

Set VCC = VCC Applied =

Desired V

Apply 5V to V

Decrement V

TRIP

Execute

Set V

TRIP

Sequence

= VCC - 50mV)

New VCC Applied =

Old V

Applied - Error

Execute

Reset V

TRIP

Sequence

Error ≤ –Emax

Emax = Maximum Allowed V

TRIP

Error

Measured V

Control Register

The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed.

The Control Register is accessed at address FFFFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register" below.

RESET pin

goes active?

YES

Desired V

TRIP

–Emax < Error < Emax

DONE

The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, and WD0. The X4163/5 will not acknowledge any data bytes written after the first byte is entered.

The state of the Control Register can be read at any time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4163/5 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation.

Error ≥ Emax

76543210

WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2

FN8120.0

April 13, 2005

X4163, X4165

BP2, BP1, BP0: Block Protect Bits (Nonvolatile)

The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to the following segments of the array.

Protected Addresses

BP2

BP1

BP0

0 0 0 None (factory setting) None 0 0 1 None None 0 1 0 None None 0 1 1 0000h - 7FFh 1 0 0 000h - 03Fh 1 0 1 000h - 07Fh 1 1 0 000h - 0FFh (256 bytes) First 4 pgs (P4) 1 1 1 000h - 1FFh

(Size) Array Lock

(2K bytes) Full Array (All)

(64 bytes) First Page (P1)

(128 bytes) First 2 pgs (P2)

(512 bytes) First 8 pgs (P8)

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the Control Register.

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a n onvolatile write cycle, so the device is ready for the next operation immediately after the stop condition.

WD1, WD0: Watchdog Timer Bits

The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below.

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory setting)

Write Protect Enable

These devices have an advanced Block Lock scheme that protects one of five blocks of the array when enabled. It provides hardware write protection through the use of a WP pin and a nonvolatile Write Protect Enable (WPEN) bit.

The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the programmable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin and the WPEN bit are HIGH and disabled when either the WP pin or the WPEN bit is LOW. When the chip is Hardware Write Protected, nonvolatile writes to the block protected sections in the memory array cannot be written and the block protect bits cannot be changed. Only the sections of the memory array that are not block protected can be written. Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH.

Table 1. Write Protect Enable Bit and WP Pin Function

Memory Array not

WP WPEN

LOW X Writes OK Writes Blocked Writes OK Software HIGH 0 Writes OK Writes Blocked Writes OK Software HIGH 1 Writes OK Writes Blocked Writes Blocked Hardware

Block Protected

Memory Array Block

Protected WPEN Bit Protection

FN8120.0

April 13, 2005

X4163, X4165

Writing to the Control Register

Changing any of the nonvolatile bits of the control register requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop).

– Write a 06H to the Control Register to set both the

Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop).

– Write a value to the Control Register that has all the

control bits set to the desired state. This can be represented as 0xys t01r in binary, wher e xy ar e th e WD bits. (Operation preceeded by a start and ended with a stop). Since this is a nonvolatile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xys t11r) then the RWEL bit is set, but the BP2, BP1, BP0, WD1 and WD0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block.

To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains se t.

SERIAL INTERFACE

Serial Interface Conventions

The device supports a bidirectional bus orie nted protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 5.

Figure 5. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable Data Change Data Stable

FN8120.0

April 13, 2005

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