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X4163, X4165
16K, 2K x 8 Bit
Data Sheet April 13, 2005
CPU Supervisor with 16K EEPROM
FEATURES
• Selectable watchdog timer
•Low V
—Four standard reset threshold voltages
—Adjust low V
special programming sequence
—Reset signal valid to V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 16Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
—8-lead SOIC
—8-lead TSSOP
detection and reset assertion
CC
reset threshold voltage using
CC
= 1V
CC
FN8120.0
DESCRIPTION
The X4163/5 combines four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET
/RESET active for a
period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable
time out interval, the device activates the
RESET
/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V
point. RESET
falls below the set minimum VCC trip
CC
/RESET is asserted until VCC returns to
proper operating level and stabilizes. Four industry
standard V
thresholds are available, however, Inter-
TRIP
sil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SDA
SCL
S0
S1
V
CC
Watchdog Transition
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
1
Detector
Protect Logic
Status
Register
EEPROM Array
Block Lock Control
+
V
TRIP
-
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
2Kb
Watchdog
Timer Reset
RESET (X4163)
RESET (X4165)
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
PIN CONFIGURATION
8-Pin JEDEC SOIC
X4163, X4165
V
8
CC
7
WP
6
SCL
5
SDA
SCL
8
SDA
7
6
V
SS
5
RESET
/RESET
RESET
S
S
/RESET
V
SS
WP
V
CC
S
S
1
0
2
1
3
4
8 Pin TSSOP
1
2
3
0
4
1
PIN FUNCTION
Pin
(SOIC)
Pin
(TSSOP) Name Function
13 S0Device Select Input
24 S
35
1
RESET/
RESET
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
active until V
RESET
/RESET goes active if the Watchdog Timer is enabled and SDA remains
rises above the minimum VCC sense level for 250ms.
CC
falls below the minimum VCC sense level. It will remain
CC
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET
goes active on power up and remains active for 250ms after the power supply stabilizes.
46 V
SS
Ground
57SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET
/RESET going active.
68 SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output.
71 WPWrite Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
82 V
CC
Supply Voltage
/RESET
2
FN8120.0
April 13, 2005
X4163, X4165
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4163/5 activates a Power
On Reset Circuit that pulls the RESET
/RESET pin
active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta -
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
exceeds the device V
CC
threshold value
TRIP
for 200ms (nominal) the circuit releases
RESET
/RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4163/5 monitors the V
and asserts RESET
below a preset minimum V
/RESET if supply voltage falls
. The RESET/RESET
TRIP
CC
level
signal prevents the microprocessor fro m operating in a
power fail or brownout condition. The RESET
/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V
V
for 200ms.
TRIP
returns and exceeds
CC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproce ssor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET
/RESET signal. The state of two nonvolatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET
/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any inprogress communications are terminated. While
RESET
/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET
/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
THRESHOLD RESET PROCEDURE
CC
The X4163/5 is shipped with a standard V
(V
) voltage. This value will not change over normal
TRIP
threshold
CC
operating and storage conditions. However, in applications where the standard V
higher precision is needed in the V
is not exactly right, or if
TRIP
value, the
TRIP
X4163/5 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvolatile control signal.
Figure 1. Set V
WP
01234567
SCL
SDA
Level Sequence (V
TRIP
A0h
3
= desired V
CC
V
= 12-15V
P
01234567
00h
values WEL bit set)
TRIP
01234567
01h
01234567
00h
FN8120.0
April 13, 2005
X4163, X4165
Setting the V
This procedure is used to set the V
TRIP
Voltage
to a higher or
TRIP
lower voltage value. It is necessary to reset the trip
point before setting the new value.
To set the new V
bit in the control register, then apply the desired V
voltage, start by setting the WEL
TRIP
TRIP
threshold voltage to the VCC pin and the programming
voltage, V
to the WP pin and 2 byte addr ess and 1
P,
byte of “00” data. The stop bit following a valid write
operation initiates the V
Bring WP
Figure 2. Reset V
WP
SCL
LOW to complete the operation.
TRIP
01234567
programming sequence.
TRIP
Level Sequence (VCC > 3V. WP = 12–15V, WEL bit set)
V
= 12-15V
P
01234567
Resetting the V
This procedure is used to set th e V
TRIP
Voltage
to a “native”
TRIP
voltage level. For example, if the current V
and the new V
be reset. When V
must be 4.0V, then the V
TRIP
is reset, the new V
TRIP
TRIP
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V
WEL bit in the control register, apply V
gramming voltage, V
voltage start by setting the
TRIP
, to the WP pin and 2 byte
P
CC
address and 1 byte of “00” data. The stop bit of a valid
write operation initiates the V
sequence. Bring WP
01234567
LOW to complete the operation.
01234567
programming
TRIP
is 4.4V
TRIP
must
TRIP
is some-
and the pro-
SDA
Figure 3. Sample V
V
TRIP
Adj.
A0h
Reset Circuit
TRIP
RESET
4.7K
00h
1
2
3
4
SOIC
X4163
03h
Adjust
8
7
6
5
Run
00h
V
P
µC
SCL
SDA
4
FN8120.0
April 13, 2005
X4163, X4165
Figure 4. V
Programming Sequence
TRIP
New VCC Applied =
Old V
Applied + Error
CC
V
Programming
TRIP
Execute
Reset V
TRIP
Sequence
Set VCC = VCC Applied =
Desired V
Apply 5V to V
Decrement V
(V
CC
TRIP
Execute
Set V
TRIP
Sequence
CC
= VCC - 50mV)
CC
New VCC Applied =
Old V
Applied - Error
CC
Execute
Reset V
TRIP
Sequence
NO
Error ≤ –Emax
Emax = Maximum Allowed V
TRIP
Error
Measured V
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write operation directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
RESET pin
goes active?
YES
Desired V
TRIP
TRIP
–Emax < Error < Emax
DONE
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, and WD0. The X4163/5 will not acknowledge
any data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4163/5 resets itself after the first byte is read.
The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required
to end this operation.
Error ≥ Emax
-
76543210
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
5
FN8120.0
April 13, 2005
X4163, X4165
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block protect bits will prevent write operations to the following
segments of the array.
Protected Addresses
BP2
BP1
BP0
0 0 0 None (factory setting) None
0 0 1 None None
0 1 0 None None
0 1 1 0000h - 7FFh
1 0 0 000h - 03Fh
1 0 1 000h - 07Fh
1 1 0 000h - 0FFh (256 bytes) First 4 pgs (P4)
1 1 1 000h - 1FFh
(Size) Array Lock
(2K bytes) Full Array (All)
(64 bytes) First Page (P1)
(128 bytes) First 2 pgs (P2)
(512 bytes) First 8 pgs (P8)
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a n onvolatile
write cycle, so the device is ready for the next operation immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1 WD0 Watchdog Time Out Period
0 0 1.4 seconds
0 1 600 milliseconds
1 0 200 milliseconds
1 1 disabled (factory setting)
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of five blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hardware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes to the
block protected sections in the memory array cannot be
written and the block protect bits cannot be changed.
Only the sections of the memory array that are not
block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed
back to a LOW state; so write protection is enabled as
long as the WP pin is held HIGH.
Table 1. Write Protect Enable Bit and WP Pin Function
Memory Array not
WP WPEN
LOW X Writes OK Writes Blocked Writes OK Software
HIGH 0 Writes OK Writes Blocked Writes OK Software
HIGH 1 Writes OK Writes Blocked Writes Blocked Hardware
Block Protected
6
Memory Array Block
Protected WPEN Bit Protection
FN8120.0
April 13, 2005
X4163, X4165
Writing to the Control Register
Changing any of the nonvolatile bits of the control register requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be represented as 0xys t01r in binary, wher e xy ar e th e
WD bits. (Operation preceeded by a start and ended
with a stop). Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xys t11r) then the
RWEL bit is set, but the BP2, BP1, BP0, WD1 and
WD0 bits remain unchanged. Writing a second byte
to the control register is not allowed. Doing so aborts
the write operation and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains se t.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus orie nted protocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this family operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
7
FN8120.0
April 13, 2005
Figure 6. Valid Start and Stop Conditions
SCL
SDA
X4163, X4165
Start Stop
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Serial Acknowledge
Acknowledge is a software convention used to indicate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
Figure 7. Acknowledge Response From Receiver
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent e ight bit word. Th e device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
SCL from
Master
Data Output
from
Transmitter
Data Output
from Receiver
81 9
Start Acknowledge
8
FN8120.0
April 13, 2005
Figure 8. Byte Write Sequence
X4163, X4165
Signals from
the Master
SDA Bus
Signals from
the S lave
S
t
a
Slave
Address
r
t
0101
Word Address
0
A
C
K
Serial Write Operations
B
YTE WRITE
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits
the next eight bits of data. After receiving the 8 bits of
the Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile memory. During this internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA
output is at high impedance. See Figure 8.
A write to a protected block of memory will suppress
the acknowledge bit.
Byte 1
Word Address
Byte 0
A
C
K
Data
A
C
K
S
t
o
p
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowledge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writin g
at location 60, and loads 12-bytes, then the first 4bytes are written to locations 60 through 63, and the
last 8-bytes are written to locations 0 through 7. Afterwards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64-bytes of data, then new data over-writes
the previous data, one byte at a time.
Figure 9. Page Write Operation
S
Signals from
the Master
SDA Bus
Signals from
the Slave
t
a
Slave
r
Address
t
1010
9
0
A
C
K
Word Address
Byte 1
Word Address
A
C
K
Byte 0
(1 < n < 64)
S
Data
(1)
A
C
K
Data
(n)
A
C
K
t
o
p
A
C
K
April 13, 2005
FN8120.0
X4163, X4165
Figure 10. Writing 12-bytes to a 64-byte page starting at location 60.
8 Bytes
Address
= 7
Address Pointer
Ends Here
Addr = 8
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the
device initiates the internal nonvolatile cycle. Acknowledge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.
4 Bytes
Address
60
Address
n-1
Figure 11. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
ACK
returned?
YES
Nonvolatile Cycle
complete. Continue
command sequence?
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Issue STOP
NO
NO
Issue STOP
10
FN8120.0
April 13, 2005
Figure 12. Current Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
X4163, X4165
S
t
a
r
t
Slave
Address
0101
S
t
o
p
1
A
C
K
Data
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W
bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Re fer to Figure 12
for the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W
bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W
bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Figure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Figure 13. Random Address Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
Slave
r
Address
t
0101
Word Address
0
A
C
K
Byte 1
11
Word Address
Byte 0
A
C
K
S
t
Slave
a
Address
r
t
1
A
C
K
A
C
K
Data
S
t
o
p
FN8120.0
April 13, 2005
Figure 14. Sequential Read Sequence
X4163, X4165
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
Address
1
A
C
K
A
C
K
Data
(1)
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000
and the device continues
H
to output data for each acknowledge received. Refer
to Figure 14 for the acknowledge and data transfer
sequence.
S
t
o
p
Data
(2)
A
C
K
Data
(n-1)
(n is any integer greater than 1)
A
C
K
Data
(n)
X4163/5 Addressing
S
LAVE ADDRESS BYTE
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array.
– one bits of ‘0’.
– next two bits are the device address.
– one bit of the slave command byte is a R/W
R/W
bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W
bit. The
bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
12
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal co unter
is undefined on a power up condition.
FN8120.0
April 13, 2005
Figure 15. X4163/5 Addressing
X4163, X4165
Device Identifier Device Select
R/WS0S100101
Slave Address Byte
High Order Word Address
Word Address Byte 0–16K
Low Order Word Address
A7
(X1)
A5
A6
(X0)
(Y5)
Word Address Byte 0 for all options
A4
(Y4)
Data Byte for all options
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET
/RESET Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
–T
he proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
00000
A3
(Y3)
(X4) (X3) (X2)
(Y2) (Y1) (Y0)
A8A9A10
A0A1A2
D0D1D2D3D4D5D6D7
– Communication to the device is inhibited while
RESET
/RESET is active and any in-progress com-
munication is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
SYMBOL TABLE
WAVEFORM INPUTS OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A Center Line
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
is High
Impedance
13
FN8120.0
April 13, 2005
X4163, X4165
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................-65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current...............................................5mA
Lead temperature (soldering, 10 seconds)........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max.
Commercial 0°C 70°C
Industrial -40°C +85°C
Option Supply Voltage Limits
-2.7 and -2.7A 2.7V to 5.5V
Blank and -4.5A 4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
= 2.7 to 5.5V
V
CC
Symbol Parameter
(1)
I
CC1
I
CC2
I
SB
I
SB
I
LI
I
LO
V
IL
V
IH
V
HYS
V
OL
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Active Supply Current Read 1.0 mA VIL = VCC x 0.1, VIH = VCC x 0.9
(1)
Active Supply Current Write 3.0 mA
(2)
Standby Current DC (WDT off) 1 µA V
(2)
Standby Current DC (WDT on) 20 µA V
Input Leakage Current 10 µA VIN = GND to V
Output Leakage Current 10 µA V
(3)
Input LOW Voltage -0.5 VCC x 0.3 V
(3)
Input nonvolatile VCC x 0.7 V
+ 0.5 V
CC
Schmitt Trigger Input Hysteresis
Fixed input level
related level
V
CC
0.2
.05 x V
CC
Output LOW Voltage 0.4 V IOL = 3.0mA (2.7- 5.5V)
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
Min. and VIH Max. are for reference only and are not tested.
IL
Unit Test ConditionsMin Max
= 400kHz, SDA = Commands
f
SCL
= V
SDA
SCL
Others = GND or V
SDA=VSCL=VSB
Others = GND or V
= GND to V
SDA
Device is in Standby
V
V
after a stop ending a write operation.
WC
WC
= V
SB
SB
SB
CC
CC
(2)
after a stop that initiates a
14
FN8120.0
April 13, 2005
X4163, X4165
CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V)
Symbol Parameter Max. Unit Test Conditions
(4)
C
OUT
(4)
C
IN
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS
Output Capacitance (SDA, RST/RST)8pFV
OUT
= 0V
Input Capacitance (SCL, WP) 6 pF VIN = 0V
5V
Input pulse levels 0.1VCC to 0.9V
Input rise and fall times 10ns
Input and output timing levels 0.5V
CC
Output load Standard output load
SDA
RESET
1533Ω
or
100pF
For VOL= 0.4V
= 3 mA
and I
OL
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol Parameter Min. Max. Unit
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
t
SU:WP
t
HD:WP
SCL Clock Frequency 0 400 kHz
Pulse width Suppression Time at inputs 50 ns
SCL LOW to SDA Data Out Valid 0.1 0.9 µs
Time the bus free before start of new transmission 1.3 µs
Clock LOW Time 1.3 µs
Clock HIGH Time 0.6 µs
Start Condition Setup Time 0.6 µs
Start Condition Hold Time 0.6 µs
Data In Setup Time 100 ns
Data In Hold Time 0 µs
Stop Condition Setup Time 0.6 µs
Data Output Hold Time 50 ns
SDA and SCL Rise Time 20 + .1Cb 300 ns
SDA and SCL Fall Time 20 + .1Cb 300 ns
WP Setup Time 0.6 µs
WP Hold Time 0 µs
Cb Capacitive load for each bus line 400 pF
CC
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
15
FN8120.0
April 13, 2005
TIMING DIAGRAMS
Bus Timing
X4163, X4165
SCL
SDA IN
SDA OUT
WP Pin Timing
SDA IN
t
SU:STA
SCL
WP
t
F
t
HD:STA
t
START
SU:DAT
t
SU:WP
t
HIGH
t
LOW
t
HD:DAT
t
Clk 1 Clk 9
Slave Address Byte
R
t
SU:STO
t
t
DH
AA
t
HD:WP
t
BUF
Write Cycle Timing
SCL
SDA
8th bit of Last Byte ACK
Stop
Condition
t
WC
Start
Condition
Nonvolatile Write Cycle Timing
Symbol Parameter Min. Typ.
(1)
t
WC
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Write Cycle Time 5 10 ms
(1)
Max. Unit
16
FN8120.0
April 13, 2005
Power-Up and Power-Down Timing
V
V
CC
RESET
(X4165)
RESET
(X4163)
0 Volts
TRIP
t
PURST
t
R
X4163, X4165
t
PURST
t
RPD
t
V
RVALID
V
F
RVALID
RESET
Output Timing
Symbol Parameter Min. Typ. Max. Unit
V
TRIP
t
PURST
(8)
t
RPD
(8)
t
F
(8)
t
R
V
RVALID
Notes: (8) This parameter is periodically sampled and not 100% tested.
Reset Trip Point Voltage, X4163/5-4.5A
Reset Trip Point Voltage, X4163/5
Reset Trip Point Voltage, X4163/5-2.7A
Reset Trip Point Voltage, X4163/5-2.7
4.5
4.25
2.85
2.55
4.62
4.38
2.92
2.62
4.75
4.5
3.0
2.7
Power-up Reset Time Out 100 250 400 ms
VCC Detect to Reset/Output 500 ns
VCC Fall Time 100 µs
VCC Rise Time 100 µs
Reset Valid V
CC
1V
SDA vs. RESET Timing
SCL
t
RSP
t
RSP<tWDO
t
RSP>tWDO
t
RST
t
RSP>tWDO
t
RST
V
SDA
RESET
Note: All inputs are ignored during the active reset period (t
17
RST
).
FN8120.0
April 13, 2005
X4163, X4165
RESET Output Timing
Symbol Parameter Min. Typ. Max. Units
t
WDO
t
RST
Programming Timing Diagram (WEL = 1)
V
TRIP
V
CC
(V
)
TRIP
V
P
WP
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
100
450
1
OFF
250
650
1.5
400
850
2
Reset Time Out 100 250 400 ms
V
TRIP
t
TSU
t
THD
ms
ms
sec
t
VPS
SCL
SDA
A0h
Programming Parameters
V
TRIP
00h
01h or 03h
00h
t
VPH
t
VPO
t
RP
Parameter Description Min. Max. Unit
t
t
t
t
t
V
V
V
VPS
VPH
TSU
THD
t
WC
VPO
t
RP
V
P
TRAN
ta1
ta2
V
Program Enable Voltage Setup time 1 µs
TRIP
V
Program Enable Voltage Hold time 1 µs
TRIP
V
Setup time 1 µs
TRIP
V
Hold (stable) time 10 ms
TRIP
V
Write Cycle Time 10 ms
TRIP
V
Program Enable Voltage Off time (Between successive adjustments) 0 µs
TRIP
V
Program Recovery Period (Between successive adjustments) 10 ms
TRIP
Programming Voltage 15 18 V
V
Programmed Voltage Range 2.55 4.75 V
TRIP
Initial V
Subsequent V
Program Voltage accuracy (VCC applied - V
TRIP
Program Voltage accuracy [(VCC applied - V
TRIP
) (Programmed at 25°C.) -0.1 +0.4 V
TRIP
ta1
) - V
TRIP
.
-25 +25 mV
Programmed at 25°C.]
V
tr
V
Program Voltage repeatability (Successive program operations. Programmed
TRIP
-25 +25 mV
at 25°C.)
V
tv
V
programming parameters are periodically sampled and are not 100% tested.
TRIP
V
Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 m V
TRIP
18
FN8120.0
April 13, 2005
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
X4163, X4165
Pin 1 Index
(4X) 7°
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
Pin 1
X 45°
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
0.150 (3.80)
0.158 (4.00)
0.004 (0.19)
0.010 (0.25)
0.228 (5.80)
0.244 (6.20)
0.053 (1.35)
0.069 (1.75)
0.050"Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)
0.250"
19
0.050"
Typical
0.030"
Typical
8 PlacesFOOTPRINT
FN8120.0
April 13, 2005
PACKAGING INFORMATION
X4163, X4165
8-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
0° - 8°
.019 (.50)
.029 (.75)
Detail A (20X)
.114 (2.9)
.122 (3.1)
.0075 (.19)
.0118 (.30)
.010 (.25)
.169 (4.3)
.177 (4.5)
.002 (.05)
.006 (.15)
Gage Plane
Seating Plane
.252 (6.4) BSC
.047 (1.20)
(4.16)
(7.72)
See Detail “A”
(1.78)
.031 (.80)
.041 (1.05)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
(0.42)
All Measurements Are Typical
20
(0.65)
FN8120.0
April 13, 2005
X4163, X4165
Ordering Information
V
CC
Range
4.5-5.5V 4.5-4.75 8L SOIC 0°C - 70°C X4163S8–4.5A X4165S8–4.5A
4.5-5.5V 4.25-4.5 8L SOIC 0°C - 70°C X4163S8 X4165S8
2.7-5.5V 2.85-3.0 8L SOIC 0°C - 70°C X4163S8–2.7A X4165S8–2.7A
2.7-5.5V 2.55-2.7 8L SOIC 0°C - 70°C X4163S8–2.7 X4165S8–2.7
V
TRIP
Range Package
8L TSSOP 0°C - 70°C X4163V8–4.5A X4165V8–4.5A
8L TSSOP 0°C - 70°C X4163V8 X4165V8
8LTSSOP 0°C - 70°C X4163V8–2.7A X4165V8–2.7A
8L TSSOP 0°C - 70°C X4163V8–2.7 X4165V8–2.7
Operating
Temperature Range
Part Number RESET
(Active LOW)
Part Number RESET
(Active HIGH)
-40°C - 85°C X4163S8I–4.5A X4165S8I–4.5A
-40°C - 85°C X4163V8I–4.5A X4165V8I–4.5A
-40°C - 85°C X4163S8I X4165S8I
-40°C - 85°C X4163V8I X4165V8I
-40°C - 85°C X4163S8I–2.7A X4165S8I–2.7A
-40°C - 85°C X4163V8I–2.7A X4165V8I–2.7A
-40°C - 85°C X4163S8I–2.7 X4165S8I–2.7
-40°C - 85°C X4163V8I–2.7 X4165V8I–2.7
Part Mark Information
8-Lead TSSOP
EYWW
XXXXX
ADB/ADK = -4.5A (0 to +70°C)
ADD/ADM = No Suffix (0 to +70°C)
ADF/ADO = -2.7A (0 to +70°C)
ADH/ADQ= -2.7 (0 to +70°C)
4163/4165
8-Lead SOIC
X4163/5 X
Blank = 8-Lead SOIC
XX
AL = -4.5A (0 to +70°C)
AM = -4.5A (-40 to +85°C)
Blank = No Suffix (0 to +70°C)
I = No Suffix (-40 to +85°C)
AN = -2.7A (0 to +70°C)
AP = -2.7A (-40 to +85°C)
F = -2.7 (0 to +70°C)
G = -2.7 (-40 to +85°C)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8120.0
April 13, 2005
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