intersil ISL95711 DATA SHEET

®

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ISL95711

Digitally Controlled Potentiometer (XDCP™)

Data Sheet September 5, 2006

Terminal Voltage ±2.7V or ±5V, 128 Taps
I2C Serial Interface

The Intersil ISL95711 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a I

The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. The wiper terminal can be connected to either end
of the resistor array or at any one of the Tap Positions in
between, providing 128 steps of resolution between R
R

. The “position” of the wiper is determined by the value

H

assigned to the volatile Wiper Register (WR). This register
has an associated non-volatile Initial Value Register (IVR).
The value stored in the IVR will be written into the WR at
power-up, allowing wiper position recall after power
interruption. The WR and the IVR can be directly written to
and read from using standard I
device is available in either a 10kΩ or 50kΩ version.

The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:

• Industrial and automotive control

• Parameter and bias adjustments

• Amplifier bias and control

Pinout

(10 LD MSOP)

2

C interface.

2

C interface protocol. The

ISL95711

TOP VIEW

and

L

FN8241.3

Features

• Non-V ol a ti l e So li d - State Po te nt io meter

2

•I

C Serial Interface with Hardwire Slave Address Allows

Up to Four Devices per bus

• DCP Terminal Voltage, from V- to V

• 128 Wiper Tap Points

- Wiper position can be stored in nonvolatile memory and
recalled on power-up

• 127 Resistive Elements

- Typical Rtotal tempco ±50ppm/°C

- Ratiometric Tempco ±4ppm/°C

- End to end resistance range ±20%

• Low Power CMOS

- Standby current, 1µA

- Active current, 200µA max

= 2.7V to 5.5V

-V

CC

- V- = -2.7V to -5.5V

• High Reliability

- Endurance, 200,000 data changes per bit

- Register data retention, 50 years

•R

Values = 10kΩ, 50kΩ

TOTAL

• Package

-10 Ld MSOP

- Pb-free plus anneal (RoHS compliant)

CC

SDA

GND

A1

A0

1

V-

2

3

4

5

SCL

10

V

9

CC

R

8

L

R

W

7

R

6

H

Ordering Information

PART NUMBER (Notes 1, 2) PART MARKING RESISTANCE OPTION (Ω) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. #

ISL95711WIU10Z AKO 10k -40 to +85 10 Ld MSOP M10.118
ISL95711UIU10Z AKQ 50k -40 to +85 10 Ld MSOP M10.118

NOTES:

1. Add “-T” suffix for tape and reel.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

V

CC

GND

SDA

SCL

ISL95711

7-BIT

WIPER

REGISTER

(VOLATILE)

127

126

R

H

SDA

SCL

CONTROL

A1

A0

SIMPLE BLOCK DIAGRAM

AND

MEMORY

V-

R

H

7-BIT

R

W

R

L

A1

A0

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

SLAVE

ADDRESS

DECODE

DECODER

DETAILED BLOCK DIAGRAM

Pin Descriptions

PIN NUMBER SYMBOL DESCRIPTION

2

1 SDA Open drain Data I/O for I
2 V- Negative supply voltage for the potentiometer wiper control
3 GND Ground
4 A1 A1 and A0 are address select pins used to set the slave address for the I
5 A0 A1 and A0 are address select pins used to set the slave address for the I2C serial interface
6R
7R
8R
9V

H
W

L

CC

A fixed terminal for one end of the potentiometer resistor.
The wiper terminal which is equivalent to the movable terminal of a potentiometer.
A fixed terminal for one end of the potentiometer resistor.
Positive logic supply voltage

10 SCL Clock input for the I

C serial interface

2

C serial interface

ONE

OF

128

125

124

TRANSFER

GATES

2

1

0

2

C serial interface

RESISTOR

ARRAY

R

L

R

W

2

FN8241.3

September 5, 2006

ISL95711

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SDA, SCL, A0, and A1

with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V

Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V

∆V = |V

(RH)-V(RL)

Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.03V to 6V

V

CC

, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V

R

H

ESD (Mil-Std 883, Method 3015). . . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

CC

+0.3V

CC

Thermal Resistance (Typical, Note 3) θ

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170

Recommended Operating Conditions

Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.7V to -5.5V

Analog Specifications Over recommended operating conditions unless otherwise stated.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

TC

(Notes 12, 13)

R

H,RL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = V

INL

(Note 6)

DNL

(Note 5)
ZSerror

(Note 3)

FSerror
(Note 4)

TC

(Notes 7, 13)

RESISTOR MODE (Measurements between R

RINL

(Note 11)

RDNL

(Note 10)

Roffset

(Note 9)

RH to RL resistance W option 10 kΩ

U option 50 kΩ

to RL resistance tolerance -20 +20 %

R

H

Resistance Temperature Coefficient I

R

RH,RL terminal voltage V- V
Wiper resistance V- = -5.5V; VCC = +5.5V,

Potentiometer Capacitance (Note 13) 10/10/

Leakage on RH, RL, RW pins Voltage at pins; V- to V

Integral non-linearity -1 1 LSB

Differential non-linearity W, U options -0.5 0.5 LSB

Zero-scale error W option 0 1 4 LSB

Full-scale error W option -4 -1 0 LSB

Ratiometric Temperature Coefficient DCP Register set at 63d,

V

and RL with RH not connected, or between RW and RH with RL not connected)

W

Integral non-linearity DCP register set between 20 hex and 7F hex.

Differential non-linearity W and U options -0.5 0.5 MI

Offset DCP Register set to 00 hex, W option 0 2 5 MI

= 1mA

DCP

T = -40°C to +85°C

RW

-V-)/R

CC

CC

unloaded)

TOTAL

wiper current = (V

U option 0 0.5 2

U option -2 -1 0

T = -40°C to +85°C

Monotonic over all tap positions

DCP Register set to 00 hex, U option 0 0.5 2

(Note 1) MAX UNIT

±50 ppm/°C

70 200 Ω

25

0.1 1 µA

±4 ppm/°C

-1 1 MI

CC

(°C/W)

JA

V

pF

(Note 6)

(Note 2)

(Note 2)

(Note 2)

(Note 8)

(Note 8)

(Note 8)

3

FN8241.3

September 5, 2006

ISL95711

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

V-1

I

CC2

I

V-2

I

CCSB

I

V-SB

I

LkgDig

t

DCP

(Note 13)

Vpor Power-on recall for both V- and V

V-Ramp V- ramp rate 0.2 V/ms

t

D

(Note 13)

EEPROM SPECS

SERIAL INTERFACE SPECS

V

V

IH

Hysteresis SDA and SCL input buffer hysteresis 0.05*

V

OL

Cpin

(Note 15)

f

SCL

t

IN

t

AA

t

BUF

t

LOW

t

HIGH

t

SU:STA

VCC supply current, volatile write/read f

V- supply current, volatile write/read f

VCC supply current, non volatile write f

V- supply current, nonvolatile write f

VCC current (standby) V

V- current (standby) V- = -5.5V, I2C Interface in Standby State -5 µA

Leakage current, at pins SDA, SCL,
A0, and A1

DCP wiper response time SCL falling edge of last bit of DCP Data Byte to

CC

Power-up delay VCC above Vpor, to DCP Initial Value Register

EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years

A0, A1, SDA, and SCL input buffer

IL

LOW voltage
A0, A1, SDA, and SCL input buffer

HIGH voltage

SDA output buffer LOW voltage,
sinking 4mA

A0, A1, SDA, and SCL pin capacitance 10 pF

SCL frequency 400 kHz
Pulse width suppression time at SDA

and SCL inputs
SCL falling edge to SDA output data

valid
Time the bus must be free before the

start of a new transmission

Clock LOW time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH time Measured at the 70% of VCC crossing. 600 ns
START condition setup time SCL rising edge to SDA falling edge. Both

= 400kHz;SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= 400kHz;SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Nonvolatile Write State only)

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Nonvolatile Write State only)

= +5.5V, I2C Interface in Standby State 1 µA

CC

= +3.6V, I2C Interface in Standby State 1 µA

V

CC

= -3.6V, I2C Interface in Standby State -2 µA

V­Voltage at pin from GND to V

wiper change
V- -2.5 V
V

CC

recall completed, and I
state

Any pulse narrower than the max spec is
suppressed.

SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of V
the following START condition.

crossing 70% of V

CC

CC

2

C Interface in standby

window.

CC

CC

.

during

-100 µA

-3 mA

-10 10 µA

-0.3 0.3*V

0.7*V

V

CC

00.4V

1300 ns

600 ns

TYP

(Note 1) MAX UNITS

200 µA

200 µA

1µs

2.5 V

3ms

CC

CC

VCC+

0.3

50 ns

900 ns

V

V

V

4

FN8241.3

September 5, 2006

ISL95711

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

t

HD:STA

t

SU:DAT

t

HD:DAT

t

SU:STO

t

HD:STO

t

DH

t

R

(Note 15)

t

F

(Note 15)

Cb

START condition hold time From SDA falling edge crossing 30% of VCC to

SCL falling edge crossing 70% of V

CC

.

Input data setup time From SDA exiting the 30% to 70% of VCC

window, to SCL rising edge crossing 30% of V

CC

Input data hold time From SCL rising edge crossing 70% of VCC to

SDA entering the 30% to 70% of V

window.

CC

STOP condition setup time From SCL rising edge crossing 70% of VCC, to

SDA rising edge crossing 30% of V

CC

.

STOP condition setup time From SDA rising edge to SCL falling edge. Both

crossing 70% of V

CC

.

Output data hold time From SCL falling edge crossing 30% of VCC, until

SDA enters the 30% to 70% of V

SDA and SCL rise time From 30% to 70% of V

CC

window.

CC

0.1 * Cb

SDA and SCL fall time From 70% to 30% of V

CC

0.1 * Cb

Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF

(Note 15)

Rpu

(Note 15)

SDA and SCL bus pull-up resistor off­chip

Maximum is determined by t
For Cb = 400pF, max is about 2~2.5kΩ.

and tF.

R

For Cb = 40pF, max is about 15~20kΩ.

t

WC

(Notes 14)

t

SU:A

t

HD:A

Non-volatile Write cycle time 12 20 ms

A0, A1 setup time Before START condition 600 ns
A0, A1 hold time After STOP condition 600 ns

NOTES:

1. Typical values are for T

2. LSB: [V(RW)
incremental voltage when changing from one tap to an adjacent tap.

127

3. ZS error = (V(RW)

4. FS error = [V(RW)

5. DNL = [V(RW)

6. INL = V(RW)

7.

TC

V

– V(RW)

i

– (i • LSB – V(RW)0)/LSB for i = 1 to 127.

i

Max V RW()

()Min V RW()

----------------------------------------------------------------------------------------------

Max V RW()

()Min V RW()

= +25°C and ±5V supply voltage.

A

– V(RW)0]/127. V(RW)

– V-)/LSB.

0

– VCC]/LSB.

127

]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

i

()+[]2⁄

i

127

()–

i

and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

6

10

i

---------------- -

×=

125°C

for i = 16 to 120 decimal. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.

|R

– R

8. MI =

127

9. Roffset = R
Roffset = R

10. RDNL = (R

11. RINL = [R

----------------------------------------------------------------

TC

12.

R

|/127. R

0

/MI, when measuring between R

0

/MI, when measuring between R

127

– R

)/MI - 1, for i = 16 to 127.

i

i-1

– (MI • i) – R0]/MI, for i = 16 to 127.

i

Max Ri()Min Ri()–[]

Max Ri()Min Ri()+[]2⁄

and R0 are the measured resistances for the DCP register set to 127d and 0 respectively.

127

and RL.

W

and RH.

W

6

10

---------------- -

×=

125°C

for i = 16 to 127d. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range.

13. This parameter is not 100% tested.
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a

14. t

WC

valid STOP condition at the end of a Write sequence of a I

2

C serial interface Write operation, to the end of the self-timed internal non-volatile

write cycle.

2

15. These are I

C specific parameters and are not directly tested, however they are used during device testing to validate device specification.

(Note 1) MAX UNITS

600 ns

100 ns

0ns

600 ns

600 ns

0ns

20 +

20 +

250 ns

250 ns

1kΩ

5

FN8241.3

September 5, 2006

SDA vs SCL Timing

www.BDTIC.com/Intersil

ISL95711

t

F

t

HIGH

t

LOW

t

R

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

t

SU:STA

t

HD:STA

t

SU:DAT

t

HD:DAT

t

t

DH

AA

A0, A1 Pin Timing

STOP

t

HD:A

A0, A1

SCL

SDA IN

START

t

SU:A

Clk 1

Test Circuit Equivalent Circuit

TEST POINT

R

W

FORCE
CURRENT

R

H

C

H

R

TOTAL

t

SU:STO

t

BUF

R

C

W

L

C

L

Pin Descriptions

Potentiometer Pins

RH AND R

The high (RH) and low (RL) terminals of the ISL95711 are
equivalent to the fixed terminals of a mechanical
potentiometer. R
position of the wiper and not the voltage potential on the
terminals. With WR set to 127, the wiper will be closest to
R

, and with the WR set to 00, the wiper is closest to RL

H

R

W

Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR.

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

The SDA is a bidirectional serial data input/output pin for the
I2C interface. It receives device address, operation code,

L

and RH are referenced to the relative

H

6

R

W

wiper register address and data from a I

2

C external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.

SDA requires an external pull-up resistor, since it’s an open
drain input/output.

SERIAL CLOCK (SCL)

This input is the serial clock of the I

2

C serial interface.

SCL requires an external pull-up resistor, since it’s an open
drain input.

DEVICE ADDRESS (A1-A0)

The Address inputs are used to set the least significant 2 bits
of the 7-bit I

2

C interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the
ISL95711. A maximum of 4 ISL95711 devices may occupy

2

the I

C serial bus.

FN8241.3

September 5, 2006

Typical Performance Curves

C

k

www.BDTIC.com/Intersil

120

Irw=0.6m A

100

80

T= 85ºC

ISL95711

0.6

T = 85º C

60

40

WIPER RESISTANCE (Ω)

20

0

020406080100120

TAP POS I TI O N (DE CI MAL)

FIGURE 1. WIPER RESISTANCE vs T AP POSITION

0.2

0.1

0

DNL (LSB)

-0. 1

-0. 2

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

[I(RW) = V

0 20 40 60 80 100 120

MODE FOR 10kΩ (W)

CC/RTOTAL

Vrh=2.7V, Vrl=-2.7V

TAP PO S I T I O N (D E C I MAL)

] for 10kΩ (W)

Vrh=5.5V, Vrl=-5.5V

T=25ºC

T= -40ºC

0.5

Isb (µA)

0.4

0.3

2.7 3 .2 3.7 4.2 4.7 5.2

Vcc, V

FIGURE 2. STANDBY I

0.2

0.1

0

INL (LSB)

-0. 1

Vrh=2.7V, Vrl=-2.7V

-0. 2
0 20406080100120

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOL TAGE DIVIDER

MODE FOR 10kΩ (W)

CC

Vrh=5.5V, Vrl=-5.5V

vs V

T = 25º C
T = -40º

CC

1.6
Vrh= 2.7V, Vrl=-2.7V, 1 0k

1.2

0.8
Vrh=5.5V, Vrl=-5.5V, 10k

ZSerror (LSB)

0.4

0

-40-200 20406080

TEMPERATURE ( C)

FIGURE 5. ZSerror vs TEMPERATURE

0

-0. 4

-0. 8

-1. 2

FSerror (LSB)

-1. 6

-2

-40 -20 0 20 40 60 80

FIGURE 6. FSerror vs TEMPERATURE

7

Vrh=5.5V, Vrl=-5.5V, 10

Vrh=2.7V, Vrl=-2.7V, 10k

TEMPERATURE (C)

FN8241.3

September 5, 2006

Typical Performance Curves (Continued)

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ISL95711

0.1
T=25ºC

0.05

0

RDNL (LSB)

-0.05

-0.1
0 20406080100120

FIGURE 7. DNL vs TAP POSITION IN RHEOST A T MODE FOR

10kΩ (W)

1

Idcp= 0.57m A

0.5

CHANGE (%)

0

TOTAL

-0. 5

END TO END R

FIGURE 9. END TO END R

Idcp= 1.16m A

-1

-40 -2 0 0 20 40 60 80

TEMPERATURE

Vcc=2.7V, V-= -2.7V

Vcc=5.5V, V-= -5.5V

TAP PO SIT I ON ( DECI MAL )

TEMPERATURE (ºC)

% CHANGE vs

TOTAL

1

T=25ºC

0.8

0.6

0.4

0.2

RINL (LSB)

0

-0. 2
0 20 40 60 80 100 120

TAP PO S I T I O N ( DECI MAL)

FIGURE 8. INL vs TAP POSITION IN RHEOST AT MODE FOR

100

80

60

40

TCv (ppm/°C)

20

0

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

10kΩ (W)

16 36 56 76 96 116

TAP PO SI TIO N ( D E C IMAL)

Vcc=2.7V, V-=-2.7V

Vcc=5 .5 V, V-=-5.5V

10k

50k

200

10k

150

100

TCr (ppm/°C)

50

50k

0

16 36 56 76 96

TAP PO S IT IO N (D E CI MAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

FIGURE 12. FREQUENCY RESPONSE (1.8MHz)

8

FN8241.3

September 5, 2006

Typical Performance Curves (Continued)

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ISL95711

FIGURE 13. WIPER MOVEMENT

Principles of Operation

The ISL95711 is an integrated circuit incorporating one DCP
with it’s associated register, non-volatile memory, and the

2

I

C serial interface providing direct communication between
a host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.

The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.

When the device is powered-down, the last value stored in
the IVR will be maintained in the nonvolatile memory. When
power is restored, the contents of the IVR are recalled and
the wiper is set to that value.

The ISL95711 has dual supplies, V
operation of the chip, it is recommended both power
supplies ramp up simultaneously to their final values within
20ms. The chip design gives priority to the V- supply
stabilization and then looks at V
supply goes below -2.5V, the R
code of 64. As V
R

pin goes to the code stored in the EEPROM memory

W

value (this is referred as power on recall).

also exceeds 2.5V (after V- < -2.5V), the

CC

and V-. For proper

CC

stabilization. As the V-

CC

pin goes to the default

W

FIGURE 14. LARGE SIGNAL SETTLING TIME

DCP Description

The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal is controlled by a 7-bit volatile Wiper Register (WR).
When the WR contains all zeroes (00h), the wiper terminal
(R

) is closest to its “Low” terminal (RL). When the WR

W

contains all ones (7Fh), the wiper terminal (R
its “High” terminal (R
from all zeroes (00h) to all ones (7Fh), the wiper moves
monotonically from the position closest to R
closest to R
and R

increases monotonically, while the resistance

L

between R
While the ISL95711 is being powered up, the WR is reset to

40h (64 decimal), which locates the R
between R
becomes large enough for reliable non-volatile memory
reading (~ ±2.5V), the ISL95711 reads the value stored on a
non-volatile Initial Value Register (IVR) and loads it into the
WR.

The WR and IVR can be read or written directly using the

2

I

C serial interface as described in the following sections.

H

L

and RL pins). The RW pin is connected to

H

) is closest to

). As the value of the WR increases

H

. At the same time, the resistance between RW

H

and RW decreases monotonically.

and RH. Soon after the power supply voltage

W

to the position

L

at the center

W

Memory Description

The ISL95711 contains 1 non-volatile byte know as the Initial
Value Register (IVR). It is accessed by the I
operations with Address 00h. The IVR contains the value
which is loaded into the Volatile Wiper Register (WR) at
power-up.

2

C interface

The volatile WR, and the non-volatile IVR of a DCP are
accessed with the same address.

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The Access Control Register (ACR) determines which byte
at address 00h is accessed (IVR or WR). The volatile ACR
must be set as follows:

When the ACR is all zeroes, which is the default at
power-up:

• A read operation to address 0 outputs the value of the

non-volatile IVR.

• A write operation to address 0 writes the same value to

the WR and IVR of the corresponding DCP.

When the ACR is 80h:

• A read operation to address 0 outputs the value of the

volatile WR.

• A write operation to address 0 only writes to the

corresponding volatile WR.

It is not possible to write to an IVR without writing the same
value to its corresponding WR.

00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.

TABLE 1. MEMORY MAP

ADDRESS NON-VOLATILE VOLATILE

2-ACR
1 Reserved
0IVRWR

WR: Wiper Register, IVR: Initial value Register.

The ISL95711 is pre-programmed with 40h in the IVR.

I2C Serial Interface

The ISL95711 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95711
operates as a slave device in all applications.

All communication over the I
sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL95711 the SDA pin is in
the input mode.

2

All I

C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL9571 1 continuously moni tors the SDA

2

C interface is conducted by

and SCL lines for the START condition and does not respond
to any command until this condition is met (See Figure 15). A
ST AR T condi tion is igno red during the po wer-u p sequence
and during internal non-volatile write cycles.

2

All I

C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.

An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).

The ISL95711 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95711 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1, and A0. The LSB is in the Read/Write
value is “1” for a Read operation, and “0” for a Write
operation. (See Table 2.)

TABLE 2. IDENTIFICATION BYTE FORMAT

Logic values at pins A1, and A0 respectively

01010A1A0R/W

(MSB) (LSB)

bit. Its

Write Operation

A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95711 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL9571 1 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
ISL95711 enters its standby state (See Figure 17).

The byte at address 02h determines if the Data Byte is to be
written to volatile or both volatile and non-volatile. (See
“Memory Description” on page 9.)

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Data Protection

A STOP condition acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0 or 2, the Data Byte is
transferred to the Wiper Register (WR) or to the Access
Control Register respectively, at the falling edge of the SCL
pulse that loads the last bit (LSB) of the Data Byte. If the
Address Byte is 0, and the Access Control Register is all
zeros (default), then the STOP condition initiates the internal
write cycle to non-volatile memory.

SCL

SDA

Read Operation

A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 18). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W

bit set to “1”. After each of
the three bytes, the ISL95711 responds with an ACK; then
the ISL95711 transmits the Data Byte. The master then
terminates the read operation (issuing a STOP condition)
following the last bit of the Data Byte (See Figure 18).

The byte at address 02h determines if the Data Bytes being
read are from volatile or non-volatile memory. (See “Memory
Description”.)

bit

SCL FROM

MASTER

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

SIGNALS FROM

START DATA DATA STOP

FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS

HIGH IMPEDANCE

START ACK

FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER

S

THE MASTER

T
A
R
T

STABLE CHANGE

WRITE

IDENTIFICATION

BYTE

DATA

STABLE

ADDRESS

BYTE

81 9

DATA

BYTE

HIGH IMPEDANCE

S

T
O
P

SIGNAL AT SDA

SIGNALS FROM

THE ISL95711

00011

FIGURE 17. BYTE WRITE SEQUENCE

A

A

1

0

A
C
K

000000000

0

11

A
C
K

A
C
K

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ISL95711

www.BDTIC.com/Intersil

SIGNALS

FROM THE

MASTER

SIGNAL AT SDA

SIGNALS FROM

THE SLAVE

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

00011

ADDRESS

=0

A

A

00000 00

0

1

A
C
K

BYTE

FIGURE 18. READ SEQUENCE

0

A
C
K

Communicating with the ISL95711

There are 3 register addresses in the ISL95711, of which two
can be used. Address 00h and address 02h are used to
control the device. Address 01h is reserved and should not
be used. Address 00h contains the non-volatile Initial Value
Register (IVR), and the volatile Wiper Register (WR).
Address 02h contains only a volatile word and is used as a
pointer to either the IVR or WR. See Table 1.

Register Descriptions: Access Control

The Access Control Register (ACR) is volatile and is at
address 02h. It is 8-bits, and only the MSB is significant, all
other bits should be zero (0). The ACR controls which word
is accessed at register 00h as follows:

00h = Nonvolatile IVR
80h = Volatile WR
All other bits of the ACR should be written to as zeros. Only

the MSB can be either 0 or 1. Power-up default for this
address is 00h.

S
T
A

IDENTIFICATION

R

BYTE WITH

T

R/W

01011

A
C

=1

0

A1A

0

A
C

FIRST READ

K

DATA BYTE

K

A
C
K

LAST READ
DATA BYTE

S
T
O
P

Register Description: IVR and WR

The ISL95711 has a single potentiometer . The wiper of the
potentiometer is controlled dire ctl y by th e WR. Writes and
reads can be made directly to this register to control and
monitor the wiper position without any non-volatile memory
changes. This is done by setting address 02h to data 80h,
then writing the data.

The non-volatile IVR stores the power-up value of the wiper.
On power-up, the contents of the IVR are transferred to the
WR.

To write to the IVR, first address 02h is set to data 00h, then
the data is written. Writing a new value to the IVR register
will set a new power-up position for the wiper. Also, writing to
this register will load the same value into the WR as the IVR.
So, if a new value is loaded into the IVR, not only will the
non-volatile IVR change, but the WR will also contain the
same value after the write, and the wiper position will
change. Reading from the IVR will not change the WR, if its
contents are different.

Example 1
Writing a new value (77h) to the IVR:

Write to ACR first

01010000A00000010A00000000A

Then, write to IVR

01010000A00000000A01110111A

NOTE: The WR will also reflect this new value since both registers get written to at the same time)

Example 2
Reading from the WR:

Write to the ACR first (to index the WR)

01010000A00000010A10000000A

Then, Set the WR address

01010000A00000000A

Read from the WR

01010001Axxxxxxx

NOTE: A = acknowledge, x = data bit read

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Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only

-B-

0.20 (0.008) A

GAUGE

PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o

θ

α

5

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 0 12/02

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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