intersil ISL95711 DATA SHEET

®

www.BDTIC.com/Intersil

ISL95711

Digitally Controlled Potentiometer (XDCP™)

Data Sheet September 5, 2006

Terminal Voltage ±2.7V or ±5V, 128 Taps
I2C Serial Interface

The Intersil ISL95711 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a I

The potentiometer is implemented by a resistor array
composed of 127 resistive elements and a wiper switching
network. The wiper terminal can be connected to either end
of the resistor array or at any one of the Tap Positions in
between, providing 128 steps of resolution between R
R

. The “position” of the wiper is determined by the value

H

assigned to the volatile Wiper Register (WR). This register
has an associated non-volatile Initial Value Register (IVR).
The value stored in the IVR will be written into the WR at
power-up, allowing wiper position recall after power
interruption. The WR and the IVR can be directly written to
and read from using standard I
device is available in either a 10kΩ or 50kΩ version.

The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:

• Industrial and automotive control

• Parameter and bias adjustments

• Amplifier bias and control

Pinout

(10 LD MSOP)

2

C interface.

2

C interface protocol. The

ISL95711

TOP VIEW

and

L

FN8241.3

Features

• Non-V ol a ti l e So li d - State Po te nt io meter

2

•I

C Serial Interface with Hardwire Slave Address Allows

Up to Four Devices per bus

• DCP Terminal Voltage, from V- to V

• 128 Wiper Tap Points

- Wiper position can be stored in nonvolatile memory and
recalled on power-up

• 127 Resistive Elements

- Typical Rtotal tempco ±50ppm/°C

- Ratiometric Tempco ±4ppm/°C

- End to end resistance range ±20%

• Low Power CMOS

- Standby current, 1µA

- Active current, 200µA max

= 2.7V to 5.5V

-V

CC

- V- = -2.7V to -5.5V

• High Reliability

- Endurance, 200,000 data changes per bit

- Register data retention, 50 years

•R

Values = 10kΩ, 50kΩ

TOTAL

• Package

-10 Ld MSOP

- Pb-free plus anneal (RoHS compliant)

CC

SDA

GND

A1

A0

1

V-

2

3

4

5

SCL

10

V

9

CC

R

8

L

R

W

7

R

6

H

Ordering Information

PART NUMBER (Notes 1, 2) PART MARKING RESISTANCE OPTION (Ω) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. #

ISL95711WIU10Z AKO 10k -40 to +85 10 Ld MSOP M10.118
ISL95711UIU10Z AKQ 50k -40 to +85 10 Ld MSOP M10.118

NOTES:

1. Add “-T” suffix for tape and reel.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Block Diagram

www.BDTIC.com/Intersil

V

CC

GND

SDA

SCL

ISL95711

7-BIT

WIPER

REGISTER

(VOLATILE)

127

126

R

H

SDA

SCL

CONTROL

A1

A0

SIMPLE BLOCK DIAGRAM

AND

MEMORY

V-

R

H

7-BIT

R

W

R

L

A1

A0

NONVOLATILE

MEMORY

STORE AND

RECALL

CONTROL

CIRCUITRY

SLAVE

ADDRESS

DECODE

DECODER

DETAILED BLOCK DIAGRAM

Pin Descriptions

PIN NUMBER SYMBOL DESCRIPTION

2

1 SDA Open drain Data I/O for I
2 V- Negative supply voltage for the potentiometer wiper control
3 GND Ground
4 A1 A1 and A0 are address select pins used to set the slave address for the I
5 A0 A1 and A0 are address select pins used to set the slave address for the I2C serial interface
6R
7R
8R
9V

H
W

L

CC

A fixed terminal for one end of the potentiometer resistor.
The wiper terminal which is equivalent to the movable terminal of a potentiometer.
A fixed terminal for one end of the potentiometer resistor.
Positive logic supply voltage

10 SCL Clock input for the I

C serial interface

2

C serial interface

ONE

OF

128

125

124

TRANSFER

GATES

2

1

0

2

C serial interface

RESISTOR

ARRAY

R

L

R

W

2

FN8241.3

September 5, 2006

ISL95711

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on SDA, SCL, A0, and A1

with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to V

Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V

∆V = |V

(RH)-V(RL)

Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-.03V to 6V

V

CC

, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V

R

H

ESD (Mil-Std 883, Method 3015). . . . . . . . . . . . . . . . . . . . . . . .>2kV

ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V

CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

NOTE:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. θ

JA

|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

CC

+0.3V

CC

Thermal Resistance (Typical, Note 3) θ

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . +170

Recommended Operating Conditions

Temperature Range (Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.7V to -5.5V

Analog Specifications Over recommended operating conditions unless otherwise stated.

TYP

SYMBOL PARAMETER TEST CONDITIONS MIN

R

TOTAL

TC

(Notes 12, 13)

R

H,RL

R

W

C

H/CL/CW

I

LkgDCP

VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = V

INL

(Note 6)

DNL

(Note 5)
ZSerror

(Note 3)

FSerror
(Note 4)

TC

(Notes 7, 13)

RESISTOR MODE (Measurements between R

RINL

(Note 11)

RDNL

(Note 10)

Roffset

(Note 9)

RH to RL resistance W option 10 kΩ

U option 50 kΩ

to RL resistance tolerance -20 +20 %

R

H

Resistance Temperature Coefficient I

R

RH,RL terminal voltage V- V
Wiper resistance V- = -5.5V; VCC = +5.5V,

Potentiometer Capacitance (Note 13) 10/10/

Leakage on RH, RL, RW pins Voltage at pins; V- to V

Integral non-linearity -1 1 LSB

Differential non-linearity W, U options -0.5 0.5 LSB

Zero-scale error W option 0 1 4 LSB

Full-scale error W option -4 -1 0 LSB

Ratiometric Temperature Coefficient DCP Register set at 63d,

V

and RL with RH not connected, or between RW and RH with RL not connected)

W

Integral non-linearity DCP register set between 20 hex and 7F hex.

Differential non-linearity W and U options -0.5 0.5 MI

Offset DCP Register set to 00 hex, W option 0 2 5 MI

= 1mA

DCP

T = -40°C to +85°C

RW

-V-)/R

CC

CC

unloaded)

TOTAL

wiper current = (V

U option 0 0.5 2

U option -2 -1 0

T = -40°C to +85°C

Monotonic over all tap positions

DCP Register set to 00 hex, U option 0 0.5 2

(Note 1) MAX UNIT

±50 ppm/°C

70 200 Ω

25

0.1 1 µA

±4 ppm/°C

-1 1 MI

CC

(°C/W)

JA

V

pF

(Note 6)

(Note 2)

(Note 2)

(Note 2)

(Note 8)

(Note 8)

(Note 8)

3

FN8241.3

September 5, 2006

ISL95711

www.BDTIC.com/Intersil

Operating Specifications Over the recommended operating conditions unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS MIN

I

CC1

I

V-1

I

CC2

I

V-2

I

CCSB

I

V-SB

I

LkgDig

t

DCP

(Note 13)

Vpor Power-on recall for both V- and V

V-Ramp V- ramp rate 0.2 V/ms

t

D

(Note 13)

EEPROM SPECS

SERIAL INTERFACE SPECS

V

V

IH

Hysteresis SDA and SCL input buffer hysteresis 0.05*

V

OL

Cpin

(Note 15)

f

SCL

t

IN

t

AA

t

BUF

t

LOW

t

HIGH

t

SU:STA

VCC supply current, volatile write/read f

V- supply current, volatile write/read f

VCC supply current, non volatile write f

V- supply current, nonvolatile write f

VCC current (standby) V

V- current (standby) V- = -5.5V, I2C Interface in Standby State -5 µA

Leakage current, at pins SDA, SCL,
A0, and A1

DCP wiper response time SCL falling edge of last bit of DCP Data Byte to

CC

Power-up delay VCC above Vpor, to DCP Initial Value Register

EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years

A0, A1, SDA, and SCL input buffer

IL

LOW voltage
A0, A1, SDA, and SCL input buffer

HIGH voltage

SDA output buffer LOW voltage,
sinking 4mA

A0, A1, SDA, and SCL pin capacitance 10 pF

SCL frequency 400 kHz
Pulse width suppression time at SDA

and SCL inputs
SCL falling edge to SDA output data

valid
Time the bus must be free before the

start of a new transmission

Clock LOW time Measured at the 30% of VCC crossing. 1300 ns
Clock HIGH time Measured at the 70% of VCC crossing. 600 ns
START condition setup time SCL rising edge to SDA falling edge. Both

= 400kHz;SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= 400kHz;SDA = Open; (for I2C, Active,

SCL

Read and Volatile Write States only)

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Nonvolatile Write State only)

= 400kHz; SDA = Open; (for I2C, Active,

SCL

Nonvolatile Write State only)

= +5.5V, I2C Interface in Standby State 1 µA

CC

= +3.6V, I2C Interface in Standby State 1 µA

V

CC

= -3.6V, I2C Interface in Standby State -2 µA

V­Voltage at pin from GND to V

wiper change
V- -2.5 V
V

CC

recall completed, and I
state

Any pulse narrower than the max spec is
suppressed.

SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of V

SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of V
the following START condition.

crossing 70% of V

CC

CC

2

C Interface in standby

window.

CC

CC

.

during

-100 µA

-3 mA

-10 10 µA

-0.3 0.3*V

0.7*V

V

CC

00.4V

1300 ns

600 ns

TYP

(Note 1) MAX UNITS

200 µA

200 µA

1µs

2.5 V

3ms

CC

CC

VCC+

0.3

50 ns

900 ns

V

V

V

4

FN8241.3

September 5, 2006