Datasheet ISL9012 Datasheet (intersil)

®

www.BDTIC.com/Intersil

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Data Sheet March 11, 2008

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SIGN

ISL9012

FN9220.3

Dual LDO with Low Noise, Low IQ, and
High PSRR

ISL9012 is a high performance dual LDO capable of
sourcing 150mA current from Channel 1, and 300mA from
Channel 2. The device has a low standby current and
high-PSRR and is stable with output capacitance of 1µF to
10µF with ESR of up to 200mΩ.

The device integrates a Power-On-Reset (POR) function for
the VO2 output. The POR delay for VO2 can be externally
programmed by connecting a timing capacitor to the CPOR
pin. A reference bypass pin is also provided for connecting a
noise-filtering capacitor for low noise and high PSRR
applications.

The quiescent current is typically only 45µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.

Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to

3.3V. Other output voltage options are available on request.

Pinout

ISL9012

(10 LD 3X3 DFN)

TOP VIEW

VIN
EN1
EN2

CBYP

CPOR

1
2
3
4
5

VO1

10

VO2

9

POR

8

NC

7

GND

6

Features

• Integrates two high performance LDOs

- VO1 - 150mA output

- VO2 - 300mA output

• Excellent transient response to large current steps

• Excellent load regulation:
1% voltage change across full range of load current

• High PSRR: 70dB @ 1kHz

• Wide input voltage capability: 2.3V to 6.5V

• Extremely low quiescent current: 45µA (both LDOs on)

• Low dropout voltage: typically 120mV @ 150mA

• Low output noise: typically 30µV

• Stable with 1 to10µF ceramic capacitors

• Separate enable pins for each LDO

• POR output, with adjustable delay time indicates when the
VO2 output is good

• Soft-start to limit input current surge during enable

• Current limit and overheat protection

• ±1.8% accuracy over all operating conditions

• Tiny 10 Ld 3x3mm DFN package

• -40°C to +85°C operating temperature range

• Pin compatible with Micrel MIC2212

• Pb-free (RoHS compliant)

@ 100µA (1.5V)

RMS

Applications

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3 Players

• Handheld Devices including Medical Handhelds

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2005, 2006. 2008. All Rights Reserved.

All other trademarks mentioned are the property of their respective owners.

www.BDTIC.com/Intersil

Ordering Information

ISL9012

PART NUMBER

(Notes 1, 2, 3) PART MARKING

ISL9012IRNNZ DCTA 3.3 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRNJZ DAPA 3.3 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRNFZ DARA 3.3 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMNZ DCYA 3.0 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMMZ DAAK 3.0 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRMGZ DCBC 3.0 2.7 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRLLZ DAAJ 2.9 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKKZ DASA 2.85 2.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKJZ DATA 2.85 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKFZ DAVA 2.85 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRKCZ DAAB 2.85 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJNZ DCBD 2.8 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJMZ DAAH 2.8 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJRZ DAAG 2.8 2.6 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJCZ DAAF 2.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRJBZ DAWA 2.8 1.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRGCZ DAAE 2.7 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFJZ DAYA 2.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFDZ DCBK 2.5 2.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRFCZ DCBL 2.5 2.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRPLZ DAAD 1.85 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRCJZ DCBN 1.8 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRCCZ DCBP 1.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
ISL9012IRBJZ DAAC 1.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. For other output voltages, contact Intersil Marketing.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

VO1 VOLTAGE

(V)

VO2 VOLTAGE

(V)

TEMP RANGE

(°C)

PACKAGE

(Pb-free) PKG. DWG. #

2

FN9220.3

March 11, 2008

ISL9012

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V

V

O1, VO2

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V

Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V

+ 0.3)V

IN

Recommended Operating Conditions

Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

4. θ

JA

Tech Brief TB379.

, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

5. θ

JC

Thermal Resistance (Notes 4, 5) θ

3x3 DFN Package . . . . . . . . . . . . . . . . 50 10

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows:

= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;

T

A

= 0.01µF; C

C

BYP

PARAMETER SYMBOL TEST CONDITIONS

DC CHARACTERISTICS

Supply Voltage V
Ground Current Quiescent condition: I

Shutdown Current I
UVLO Threshold V

Regulation Voltage Accuracy Variation from nominal voltage output, V

Line Regulation V
Load Regulation I

Maximum Output Current I

Internal Current Limit I
Dropout Voltage (Note 7) V

Thermal Shutdown Temperature T

AC CHARACTERISTICS

Ripple Rejection I

IN

I

DD1

I

DD2

DDS

UV+

V

UV-

MAX

LIM

DO1IO

V

DO2IO

V

DO3IO

V

DO4IO
SD+

T

SD-

One LDO active 25 40 µA
Both LDO active 45 60 µA
@+25°C 0.1 1.0 µA

T

J
IN

OUT

I

OUT

VO1: Continuous 150 mA
VO2: Continuous 300 mA

O

@ 1kHz 70 dB
@ 10kHz 55 dB
@ 100kHz 40 dB

= 0.01µF

POR

MIN

(Note 8) TYP

2.3 6.5 V

= 0µA; IO2 = 0µA

O1

1.9 2.1 2.3 V

1.6 1.8 2.0 V

= VO + 0.5 to 5.5V,

= -40°C to +125°C

= (V

= 150mA; VO > 2.1V (VO1) 125 200 mV
= 300mA; VO < 2.5V (VO2) 300 500 mV
= 300mA; 2.5V ≤ VO ≤ 2.8V (VO2) 250 400 mV
= 300mA; VO > 2.8V (VO2) 200 325 mV

= 10mA, VIN = 2.8V(min), VO = 1.8V, C

+ 1.0V relative to highest output voltage) to 5.5V -0.2 0 0.2 %/V

OUT

= 100µA to 150mA (VO1 and VO2) 0.1 0.7 %
= 100µA to 300mA (VO2) 1.0 %

IN

BYP

= 0.1µF

-1.8 +1.8 %

350 475 600 mA

(°C/W) θJC (°C/W)

JA

MAX

(Note 8) UNITS

145 °C
110 °C

3

FN9220.3

March 11, 2008

ISL9012

www.BDTIC.com/Intersil

Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature

range of the device as follows:

= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;

T

A

= 0.01µF; C

C

BYP

PARAMETER SYMBOL TEST CONDITIONS

Output Noise Voltage IO = 100µA, VO = 1.5V, TA = +25°C, C

BW = 10Hz to 100kHz (Note 6)

DEVICE START-UP CHARACTERISTICS

Device Enable TIme t

LDO Soft-start Ramp Rate t

Time from assertion of the ENx pin to when the output voltage

EN

reaches 95% of the VO(nom)
Slope of linear portion of LDO output voltage ramp during start-

SSR

up

EN1, EN2 PIN CHARACTERISTICS

Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Pin Capacitance C

PIN CHARACTERISTICS

POR

POR

Thresholds V

Delay t

POR

Pin Output Low Voltage V

POR

Pin Internal Pull-Up

POR
Resistance

IL

POR+

V

POR­PLH

t

PHL

R

POR

IL
IH

, I

IH

Informative 5 pF

PIN

As a percentage of nominal output voltage 91 94 97 %

CPOR = 0.01µF 100 200 300 ms

@IOL = 1.0mA 0.2 V

OL

NOTES:

6. Limits established by characterization and are not production tested.

7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.

8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.

= 0.01µF (Continued)

POR

BYP

= 0.1µF

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

30 µVrms

250 500 µs

30 60 µs/V

-0.3 0.5 V

1.4 VIN+0.3 V

0.1 µA

87 90 93 %

25 µs

78 100 180 kΩ

EN2

t

EN

V

VO2

POR

POR+

t

PLH

V

POR-

V

POR+

<t

PHL

FIGURE 1. TIMING PARAMETER DEFINITION

4

t

PHL

V

POR-

FN9220.3

March 11, 2008

Typical Performance Curves

www.BDTIC.com/Intersil

0.8
VO = 3.3V

0.6

0.4

OUTPUT VOLTAGE, VO (%)

0.2

0.0

-0.2

-0.4

-0.6

-0.8

3.8 4.2 6.25.8
INPUT VOLTAGE (V)

-40°C

+25°C

+85°C

FIGURE 2. OUTPUT VOLTAGE vs INPUT VOL TAGE (3.3V

OUTPUT)

I

LOAD

= 0mA

ISL9012

6.63.4 4.6 5.0 5.4

0.10

+25°C

(mA)

O

VIN = 3.8V
VO = 3.3V

-40°C

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

0.08

0.06

0.04

0.02

0.00

+85°C

50 150 250 350

100 200 300 4000

LOAD CURRENT - I

FIGURE 3. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

OUTPUT VOLTAGE CHANGE (%)

-0.08

-0.10

VIN = 3.8V
VO = 3.3V
I

= 0mA

LOAD

-10 20 50 110-40

-25 5 35 8065 95 125
TEMPERATURE (°C)

3.4

IO = 0mA

3.3

3.2

3.1

3.0

OUTPUT VOLTAGE, VO (V)

2.9

2.8

3.1 3.6 4.1 4.6 5.1 6.15.6

IO = 150mA

INPUT VOLTAGE (V)

VO1 = 3.3V

FIGURE 4. OUTPUT VOLTAGE CHANGE vs TEMPERATURE FIGURE 5. OUTPUT VOLT AGE vs INPUT VOL TAGE

(VO1 = 3.3V)

2.9

IO = 0mA

2.8

2.7
IO = 150mA

2.6

IO = 300mA

2.5

OUTPUT VOLTAGE, VO (V)

2.4

VO2 = 2.8V

350

300

(mV)

250

DO

200

150

100

DROPOUT VOLTAGE, V

50

VO1 = 3.3V

VO2 = 2.8V

6.5

2.3

2.63.13.64.14.65.1 6.1
INPUT VOLTAGE (V)

5.6

FIGURE 6. OUTPUT VOLT AGE vs INPUT VOL T AGE

6.5

0

50 100 150 200 250 300 350 4000

FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT

(VO2 = 2.8V)

5

OUTPUT LOAD (mA)

FN9220.3

March 11, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL9012

175

150

(mV)

125

DO

100

75

50

DROPOUT VOLTAGE, V

25

0

VO1 = 3.3V

25 50 75 100 125 150 175 2000

+85°C

OUTPUT LOAD (mA)

+25°C

-40°C

55

50

+125°C

45

40

35

GROUND CURRENT (µA)

30

25

3.0 3.5 4.58 5.5 6.0

4.0 5.0 6.5
INPUT VOLTAGE (V)

VO1 = 3.3V
VO2 = 2.8V

IO (BOTH CHANNELS) = 0µA

+25°C

FIGURE 8. VO1 DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE

200
180
160
140
120
100

GROUND CURRENT (µA)

+85°C

80
60
40
20

0

50 100 150 200 250 4000

LOAD CURRENT (mA)

FIGURE 10. GROUND CURRENT vs LOAD

+25°C

-40°C

VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V

350300

55

50

45

40

35

GROUND CURRENT (µA)

30

25

-25 5 35 8065 95 125

-10 20 50 110-40
TEMPERATURE (°C)

VIN = 3.8V
VO = 3.3V
I

= 0µA

LOAD

BOTH OUTPUTS ON

FIGURE 11. GROUND CURRENT vs TEMPERATURE

-40°C

VO1 = 3.3V

5

4

3

2

VOLTAGE (V)

1

0

0

1234567 10

VIN

VO1

VO2

TIME (s)

VO2 = 2.8V
I

1 = 150mA

L

I

2 = 300mA

L

89

FIGURE 12. POWER-UP/POWER-DOWN

3.5

3.0

2.5

2.0

1.5

VOLTAGE (V)

1.0

0.5

VO-1

VO-2

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.00

FIGURE 13. POWER-UP/POWER-DOWN WITH POR SIGNALS

6

POR

TIME (s)

VO1 = 3.3V
VO2 = 2.8V
I

1 = 150mA

L

I

2 = 300mA

L

CPOR = 0.1µF

4.0 4.5

FN9220.3

March 11, 2008

Typical Performance Curves (Continued)

www.BDTIC.com/Intersil

ISL9012

VO2 (10mV/DIV)

3

2

1

VO1 (V)VEN (V)

0

5

0

VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 150mA
IL2 = 300mA

1, CL2 = 1µF

C

L

C

= 0.01µF

BYP

100 200 300 400 500 600 700 8000

TIME (µs)

900 1000

4.3V

3.6V

10mV/DIV

400µs/DIV

VO = 3.3V
I

LOAD

C

LOAD

C

BYP

FIGURE 14. TURN ON/TURN OFF RESPONSE FIGURE 15. LINE TRANSIENT RESPONSE, 3.3V OUTPUT

VO = 2.8V
I

= 300mA

LOAD

C

= 1µF

LOAD

C

4.2V

3.5V

BYP

= 0.01µF

VO (25mV/DIV)

= 150mA

= 1µF

= 0.01µF

VO = 1.8V

VIN = 2.8V

10mV/DIV

400µs/DIV

FIGURE 16. LINE TRANSIENT RESPONSE, 2.8V OUTPUT

100

90
80
70
60
50

PSRR (dB)

40
30
20
10

0

0.1k 1k 10k 100k 1M
FREQUENCY (Hz)

VIN = 3.6V
VO = 1.8V
I

= 10mA

O

= 0.01µF

C

BYP

C

= 1µF

LOAD

FIGURE 18. PSRR vs FREQUENCY

300mA

I

10µA

LOAD

100µs/DIV

FIGURE 17. LOAD TRANSIENT RESPONSE

1000

100

10

VIN = 3.6V
VO = 1.8V
I

= 10mA

LOAD

= 0.01µF

C

BYP

1

= 1µF

C

IN

C

= 1µF

SPECTRAL NOISE DENSITY (nV/√Hz)

LOAD

0.1
10 100 1k 10k 100k 1M

FREQUENCY (Hz)

FIGURE 19. SPECTRAL NOISE DENSITY vs FREQUENCY

7

FN9220.3

March 11, 2008

Pin Description

www.BDTIC.com/Intersil

ISL9012

PIN

NUMBER

PIN

NAME TYPE DESCRIPTION

1 VIN Analog I/O Supply Voltage/LDO Input:

Connect a 1µF capacitor to GND.

2 EN1 Low Voltage Compatible

LDO-1 Enable.

CMOS Input

3 EN2 Low Voltage Compatible

LDO-2 Enable.

CMOS Input

4 CBYP Analog I/O Reference Bypass Capacitor Pin:

Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.

5 CPOR Analog I/O POR Delay Setting Capacitor Pin:

Connect a capacitor between this pin and GND to delay the POR

output reaches 94% of its specified voltage level (200ms delay per 0.01µF).
6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane.
7 NC NC No Connection.
8POR
9VO2

Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low).
Analog I/O LDO-2 Output:

Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

10 VO1 Analog I/O LDO-1 Output:

Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

Typical Application

output release after LDO-2

VIN (2.3V TO 6.5V)

ENABLE 1

ENABLE 2

OFF

OFF

ON

ON

ISL9012

1

VIN

2

EN1

3

EN2

4

CBYP

5

CPOR

C1 C2 C3 C4 C5

C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X5R CERAMIC CAPACITOR
C3: 0.01µF X5R CERAMIC CAPACITOR
R1: 100kΩ RESISTOR, 5%

VO1
VO2

POR

NC

GND

10
9

8
7

6

R1

V

OUT

2 OK

V

OUT

2 TOO LOW

1

V

OUT

2

V

OUT

RESET
(200ms DELAY, C3 = 0.01µF)

8

FN9220.3

March 11, 2008

Block Diagram

www.BDTIC.com/Intersil

IS2

1V

QEN2

VREF

TRIM

ISL9012

VIN

LDO

ERROR

AMPLIFIER

VO2

VO1

COMPARATOR

LDO-2

LDO-1

IS1

IS2

QEN1

QEN2

EN1

EN2

UVLO

CONTROL

LOGIC

BANDGAP AND

TEMPERATURE

SENSOR

Functional Description

The ISL9012 contains all circuitry required to implement two
high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9012 adjusts its biasing to achieve the lowest standby
current consumption.

The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.

Power Control

The ISL9012 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown

POR

VOLTAGE
REFERENCE
GENERATOR

VOK2

1.00V

0.94V

0.90V

~1.0V

VOK2
POR

POR

DELAY

CPORCBYPGND

VO2

POR

mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.

If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9012 delays the VO2 turn-on until
the VO1 output reaches its target level.

If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and the ISL9012

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ISL9012

www.BDTIC.com/Intersil

delays the VO2 turn-on until the VO1 output reaches its
target level.

If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9012 immediately starts to ramp
up the VO1 output.

If both EN1 and EN2 are high, the VO1 output has priority,
and is always powered up first.

During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9012 immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.

Reference Generation

The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a

0.1µF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz to1kHz frequency
band, which is crucial in many noise-sensitive applications.

The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference, POR detection thresholds,
and other voltage references required for current generation
and over-temperature detection.

The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9012 provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.

Ω. The design is performance-optimized for a 1µF

one of the following output voltages: 1.5V, 1.8V, 1.85V, 2.5V,

2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, and 3.3V.

Power-On Reset Generation

LDO-2 has a Power-on Reset signal generation circuit which
outputs to the POR pin. The POR signal is generated as
follows:

A POR comparator continuously monitors the voltage of the
LDO-2 output. The LDO enters a power-good state when the
output voltage is above 94% of the expected output voltage
for a period exceeding the LDO PGOOD entry delay time. In
the power-good state, the open-drain POR output is in a
high-impedance state. An external resistor can be added
between the POR output and either LDO output or the input
voltage, VIN.

The power-good state is exited when the LDO-2 output falls
below 90% of the expected output voltage for a period longer
than the PGOOD exit delay time. While power-good is false,
the ISL9012 pulls the respective POR pin low.

The PGOOD entry and exit delays are determined by the
value of the external capacitor connected to the CPOR pin.
For a 0.01µF capacitor, the entry and exit delays are 200ms
and 25µs respectively. Larger or smaller capacitor values will
yield proportionately longer or shorter delay times. The POR
exit delay should never be allowed to be less than 10µs to
ensure sufficient immunity against transient induced false
POR triggering.

Overheat Detection

The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.

Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge. The
ISL9012 provides short-circuit protection by limiting the
output current to about 475mA.

Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory to

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Dual Flat No-Lead Plastic Package (DFN)

www.BDTIC.com/Intersil

ISL9012

(DAT UM B )

6

INDEX

AREA

(DATUM A)

NX (b)

5

SECTION "C-C"

6

INDEX
AREA

SEATING

PLANE

NX L

8

A

C

D

TOP

VIEW

SIDE VIEW

D2

D2/2

12

N

N-1

e
(Nd-1)Xe

REF .

BOTTOM VIEW

(A1)

2X

A3

E2/2

NX b

5

C

L

e

CC

FOR ODD TERMINAL/SIDE

87

0.10

ABC0.10

2X

0.10

E

//

A

NX k

E2

M

9

TERMINAL TIP

0.10

0.08

L

CB

BAC

L10.3x3C

10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

SYMBOL

A 0.85 0.90 0.95 ­A1 - - 0.05 ­A3 0.20 REF -

b 0.20 0.25 0.30 5, 8

D 3.00 BSC ­D2 2.33 2.38 2.43 7, 8

C

E 3.00 BSC ­E2 1.59 1.64 1.69 7, 8

C

e 0.50 BSC ­k0.20- - ­L 0.35 0.40 0.45 8

N102
Nd 5 3

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identi fier may be
either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.

NOTESMIN NOMINAL MAX

Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its sub s idiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

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