intersil ISL9012 DATA SHEET

®
www.BDTIC.com/Intersil
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Data Sheet March 11, 2008
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ISL9012
FN9220.3
Dual LDO with Low Noise, Low IQ, and High PSRR
The device integrates a Power-On-Reset (POR) function for the VO2 output. The POR delay for VO2 can be externally programmed by connecting a timing capacitor to the CPOR pin. A reference bypass pin is also provided for connecting a noise-filtering capacitor for low noise and high PSRR applications.
The quiescent current is typically only 45µA with both LDO’s enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard. Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options are available on request.
Pinout
ISL9012
(10 LD 3X3 DFN)
TOP VIEW
VIN EN1 EN2
CBYP
CPOR
1 2 3 4 5
VO1
10
VO2
9
POR
8
NC
7
GND
6
Features
• Integrates two high performance LDOs
- VO1 - 150mA output
- VO2 - 300mA output
• Excellent transient response to large current steps
• Excellent load regulation: 1% voltage change across full range of load current
• High PSRR: 70dB @ 1kHz
• Wide input voltage capability: 2.3V to 6.5V
• Extremely low quiescent current: 45µA (both LDOs on)
• Low dropout voltage: typically 120mV @ 150mA
• Low output noise: typically 30µV
• Stable with 1 to10µF ceramic capacitors
• Separate enable pins for each LDO
• POR output, with adjustable delay time indicates when the VO2 output is good
• Soft-start to limit input current surge during enable
• Current limit and overheat protection
• ±1.8% accuracy over all operating conditions
• Tiny 10 Ld 3x3mm DFN package
• -40°C to +85°C operating temperature range
• Pin compatible with Micrel MIC2212
• Pb-free (RoHS compliant)
@ 100µA (1.5V)
RMS
Applications
• PDAs, Cell Phones and Smart Phones
• Portable Instruments, MP3 Players
• Handheld Devices including Medical Handhelds
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006. 2008. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
www.BDTIC.com/Intersil
Ordering Information
ISL9012
PART NUMBER
(Notes 1, 2, 3) PART MARKING
ISL9012IRNNZ DCTA 3.3 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRNJZ DAPA 3.3 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRNFZ DARA 3.3 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRMNZ DCYA 3.0 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRMMZ DAAK 3.0 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRMGZ DCBC 3.0 2.7 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRLLZ DAAJ 2.9 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRKKZ DASA 2.85 2.85 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRKJZ DATA 2.85 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRKFZ DAVA 2.85 2.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRKCZ DAAB 2.85 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRJNZ DCBD 2.8 3.3 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRJMZ DAAH 2.8 3.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRJRZ DAAG 2.8 2.6 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRJCZ DAAF 2.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRJBZ DAWA 2.8 1.5 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRGCZ DAAE 2.7 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRFJZ DAYA 2.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRFDZ DCBK 2.5 2.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRFCZ DCBL 2.5 2.0 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRPLZ DAAD 1.85 2.9 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRCJZ DCBN 1.8 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRCCZ DCBP 1.8 1.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9012IRBJZ DAAC 1.5 2.8 -40 to +85 10 Ld 3x3 DFN L10.3x3C
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VO1 VOLTAGE
(V)
VO2 VOLTAGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-free) PKG. DWG. #
2
FN9220.3
March 11, 2008
ISL9012
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V
V
O1, VO2
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V
+ 0.3)V
IN
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . .2.3V to 6.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
4. θ
JA
Tech Brief TB379.
, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
5. θ
JC
Thermal Resistance (Notes 4, 5) θ
3x3 DFN Package . . . . . . . . . . . . . . . . 50 10
Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
T
A
= 0.01µF; C
C
BYP
PARAMETER SYMBOL TEST CONDITIONS
DC CHARACTERISTICS
Supply Voltage V Ground Current Quiescent condition: I
Shutdown Current I UVLO Threshold V
Regulation Voltage Accuracy Variation from nominal voltage output, V
Line Regulation V Load Regulation I
Maximum Output Current I
Internal Current Limit I Dropout Voltage (Note 7) V
Thermal Shutdown Temperature T
AC CHARACTERISTICS
Ripple Rejection I
IN
I
DD1
I
DD2
DDS
UV+
V
UV-
MAX
LIM
DO1IO
V
DO2IO
V
DO3IO
V
DO4IO SD+
T
SD-
One LDO active 25 40 µA Both LDO active 45 60 µA @+25°C 0.1 1.0 µA
T
J IN
OUT
I
OUT
VO1: Continuous 150 mA VO2: Continuous 300 mA
O
@ 1kHz 70 dB @ 10kHz 55 dB @ 100kHz 40 dB
= 0.01µF
POR
MIN
(Note 8) TYP
2.3 6.5 V
= 0µA; IO2 = 0µA
O1
1.9 2.1 2.3 V
1.6 1.8 2.0 V
= VO + 0.5 to 5.5V,
= -40°C to +125°C
= (V
= 150mA; VO > 2.1V (VO1) 125 200 mV = 300mA; VO < 2.5V (VO2) 300 500 mV = 300mA; 2.5V ≤ VO ≤ 2.8V (VO2) 250 400 mV = 300mA; VO > 2.8V (VO2) 200 325 mV
= 10mA, VIN = 2.8V(min), VO = 1.8V, C
+ 1.0V relative to highest output voltage) to 5.5V -0.2 0 0.2 %/V
OUT
= 100µA to 150mA (VO1 and VO2) 0.1 0.7 % = 100µA to 300mA (VO2) 1.0 %
IN
BYP
= 0.1µF
-1.8 +1.8 %
350 475 600 mA
(°C/W) θJC (°C/W)
JA
MAX
(Note 8) UNITS
145 °C 110 °C
3
FN9220.3
March 11, 2008
ISL9012
www.BDTIC.com/Intersil
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows:
= -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
T
A
= 0.01µF; C
C
BYP
PARAMETER SYMBOL TEST CONDITIONS
Output Noise Voltage IO = 100µA, VO = 1.5V, TA = +25°C, C
BW = 10Hz to 100kHz (Note 6)
DEVICE START-UP CHARACTERISTICS
Device Enable TIme t
LDO Soft-start Ramp Rate t
Time from assertion of the ENx pin to when the output voltage
EN
reaches 95% of the VO(nom) Slope of linear portion of LDO output voltage ramp during start-
SSR
up
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage V Input High Voltage V Input Leakage Current I Pin Capacitance C
PIN CHARACTERISTICS
POR
POR
Thresholds V
Delay t
POR
Pin Output Low Voltage V
POR
Pin Internal Pull-Up
POR Resistance
IL
POR+
V
POR­PLH
t
PHL
R
POR
IL IH
, I
IH
Informative 5 pF
PIN
As a percentage of nominal output voltage 91 94 97 %
CPOR = 0.01µF 100 200 300 ms
@IOL = 1.0mA 0.2 V
OL
NOTES:
6. Limits established by characterization and are not production tested.
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
= 0.01µF (Continued)
POR
BYP
= 0.1µF
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
30 µVrms
250 500 µs
30 60 µs/V
-0.3 0.5 V
1.4 VIN+0.3 V
0.1 µA
87 90 93 %
25 µs
78 100 180 kΩ
EN2
t
EN
V
VO2
POR
POR+
t
PLH
V
POR-
V
POR+
<t
PHL
FIGURE 1. TIMING PARAMETER DEFINITION
4
t
PHL
V
POR-
FN9220.3
March 11, 2008
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