intersil ISL8843 DATA SHEET

®

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ISL8843

Data Sheet January 3, 2006

Industry Standard Single-Ended Current
Mode PWM Controller

The ISL8843 is an industry standard drop-in replacement for
the popular 28C43 and 18C43 PWM controllers suitable for
a wide range of power conversion applications including
boost, flyback, and isolated output configurations. Its fast
signal propagation and output switching characteristics
make this an ideal product for existing and new designs.

Features include 30V operation, low operating current, 90µA
start-up current, adjustable operating frequency to 2MHz,
and high peak current drive capability with 20ns rise and fall
times.

PART NUMBER RISING UVLO MAX. DUTY CYCLE

ISL8843 8.4V 100%

Ordering Information

PART

NUMBER

ISL8843ABZ
(See Note)

ISL8843AUZ
(See Note)

ISL8843MBZ
(See Note)

ISL8843MUZ
(See Note)

Add -T to part number for Tape and Reel packaging.

PAR T

MARKING

8843 ABZ -40 to 105 8 Ld SOIC

8843Z -40 to 105 8 Ld MSOP

8843 MBZ -55 to 125 8 Ld SOIC

843MZ -55 to 125 8 Ld MSOP

TEMP.

RANGE (°C) PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

M8.15

M8.118

M8.15

M8.118

FN9238.1

Features

• 1A MOSFET gate driver

•90µA start-up current, 125µA maximum

• 35ns propagation delay current sense to output

• Fast transient response with peak current mode control

• 30V operation

• Adjustable switching frequency to 2MHz

• 20ns rise and fall times with 1nF output load

• Trimmed timing capacitor discharge current for accurate
deadtime/maximum duty cycle control

• 1.5MHz bandwidth error amplifier

• Tight tolerance voltage reference over line, load, and
temperature

• ±3% current limit threshold

• Pb-free plus anneal available and ELV, WEEE, RoHS

Compliant

Applications

• Telecom and datacom power

• Wireless base station power

• File server power

• Industrial power systems

• PC power supplies

• Isolated buck and flyback regulators

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

• Boost regulators

Pinout

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL8843

(8 LD SOIC, MSOP)

TOP VIEW

COMP

1

2

FB

3

CS

4

RTCT

Copyright © Intersil Americas Inc. 2005, 2006 All Rights Reserved.

8

7

5

6

VREF

VDD

OUT

GND

Functional Block Diagram

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ENABLE

V

REF

5.00 V

PWM

COMPARATOR

+

-

VREF FAULT

UV COMPARATOR

4.65V ↓ 4.80V ↑

VREF

-

+

-

+

V

DD

START/STOP

UV COMPARATOR

VDD OK

+

-

+

-

2

GND

CS

2.5V

A

A=0.5

+

-

100mV

5%

VREF

ISL8843

+

FB

AMPLIFIER

COMP

VREF

100K

150K

RTCT

January 3, 2006

FN9238.1

ERROR

2.9V

1.0V

8.4mA

ON

-

OSCILLATOR

COMPARATOR

< 10nS

-

+

VF Total = 1.15V

ON

CLOCK

2R

100 nS

FALLING EDGE

DELAY

1.1V 3%
CLAMP

R

OUT

SRQ

Q

RESET

DOMINANT

36K

Typical Application - 48V Input Dual Output Flyback

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VIN+

3

R1

36-75V

C1

C2

C3

R3

C4

CR6

Q1

C5

CR2

T1

C17

C6

R21

CR5

CR4

C19

+

R16

U2

C21

C15 C16

+

C22

+

C20

R17

R19

C14

+3.3V

+

+1.8V

RETURN

R18

R4

VIN-

R6

CR1

Q3

VR1

January 3, 2006

FN9238.1

C8

R26

R22

COMP
CS

FB
RTCT

R27

U4

ISL8843

R10

VREF

V

DD

OUT
GND

R13

U3

C13

C11

R15

R20

ISL8843

C12

ISL8843

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Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +30.0V

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A

ESD Classification

Human Body Model (Per JESD22-A114C.01) . . . . . . . . . . .2000V

Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .200V

Charged Device Model (Per JESD22-C191-A) . . . . . . . . . .1000V

DD

+ 0.3V

Thermal Resistance (Typical, Note 1) θ

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature . . . . . . . . . . . . . . . . -55°C to 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC, MSOP - Lead Tips Only)

Operating Conditions

Temperature Range

ISL8843AxZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 105°C

ISL8843MxZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C

Supply Voltage Range (Typical)

ISL8843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V - 30V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. All voltages are with respect to GND.

Electrical Specifications ISL8843A - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V
are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

UNDERVOLTAGE LOCKOUT

START Threshold 8.0 8.4 9.0 V

STOP Threshold 7.3 7.6 8.0 V

Hysteresis -0.8- V

Startup Current, I

Operating Current, I

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy Over line (V

Long Term Stability T

Current Limit, Sourcing -20 - - mA

Current Limit, Sinking 5--mA

CURRENT SENSE

Input Bias Current V

CS Offset Voltage V

COMP to PWM Comparator Offset Voltage V

Input Signal, Maximum 0.97 1.00 1.03 V

Gain, A

CS

CS to OUT Delay -3555ns

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 5) 60 90 - dB

Unity Gain Bandwidth (Note 5) 1.0 1.5 - MHz

Reference Voltage V

= ∆V

DD

DD

D

/∆VCS 0 < VCS < 910mV, VFB = 0V 2.5 3.0 3.5 V/V

COMP

= 25°C

A

VDD < START Threshold - 90 125 µA

(Note 4) - 2.9 4.0 mA

Includes 1nF GATE loading - 4.75 5.5 mA

temperature

= 125°C, 1000 hours (Note 5) - 5 - mV

A

= 1V -1.0 - 1.0 µA

CS

= 0V (Note 5) 95 100 105 mV

CS

= 0V (Note 5) 0.80 1.15 1.30 V

CS

= V

FB

= 15V, RT = 10kΩ, CT = 3.3nF, TA = -40 to 105°C (Note 3) Typical values

DD

= 12V to 18V), load,

DD

COMP

4.925 5.000 5.050 V

2.475 2.500 2.530 V

(°C/W)

JA

4

FN9238.1

January 3, 2006

ISL8843

www.BDTIC.com/Intersil

Electrical Specifications ISL8843A - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V
are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

FB Input Bias Current VFB = 0V -1.0 -0.2 1.0 µA

COMP Sink Current V

COMP Source Current V

COMP VOH V

COMP VOL V

PSRR Frequency = 120Hz, V

OSCILLATOR

Frequency Accuracy Initial, T

Frequency Variation with V

Temperature Stability (Note 5) - - 5 %

Amplitude, Peak to Peak Static Test - 1.75 - V

RTCT Discharge Voltage (Valley Voltage) Static Test - 1.0 - V

Discharge Current RTCT = 2.0V 6.5 7.8 8.5 mA

OUTPUT

Gate VOH V

Gate VOL OUT - GND, I

Peak Output Current C

Rise Time C

Fall Time C

GATE VOL UVLO Clamp Voltage VDD = 5V, I

PWM

Maximum Duty Cycle COMP = VREF 93.5 95 - %

Minimum Duty Cycle COMP = GND - - 0 %

NOTES:

3. Specifications at -40°C and 105°C are guaranteed by 25°C test with margin limits.

4. This is the V

5. Guaranteed by design, not 100% tested in production.

DD

DD

current consumed when the device is active but not switching. Does not include gate drive current.

= 25°C (Continued)

A

COMP

COMP

FB

FB

18V (Note 5)

TA= 25°C, (F

DD

OUT

OUT

OUT

= 2.3V 4.80 - VREF V

= 2.7V 0.4 - 1.0 V

- OUT, I

= 1nF (Note 5) - 1.0 - A

= 1nF (Note 5) - 20 40 ns

= 1nF (Note 5) - 20 40 ns

= 15V, RT = 10kΩ, CT = 3.3nF, TA = -40 to 105°C (Note 3) Typical values

DD

= 1.5V, VFB = 2.7V 1.0 - - mA

= 1.5V, VFB = 2.3V -0.4 - - mA

= 12V to

DD

= 25°C 485153kHz

A

- F9V)/F

30V

OUT

OUT

LOAD

30V

= -200mA - 1.0 2.0 V

= 200mA - 1.0 2.0 V

= 1mA - - 1.2 V

60 80 - dB

-0.21.0%

Electrical Specifications ISL8843M - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V
are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

UNDERVOLTAGE LOCKOUT

START Threshold 8.0 8.4 9.0 V

STOP Threshold 7.3 7.6 8.0 V

Hysteresis -0.8- V

Startup Current, I

Operating Current, I

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy Over line (V

DD

DD

D

= 25°C

A

VDD < START Threshold - 90 125 µA

(Note 7) - 2.9 4.0 mA

Includes 1nF GATE loading - 4.75 5.5 mA

temperature

5

= 15V, RT = 10kΩ, CT = 3.3nF, TA = -55 to 125°C (Note 6), Typical values

DD

= 12V to 18V), load,

DD

4.900 5.000 5.050 V

January 3, 2006

FN9238.1

ISL8843

www.BDTIC.com/Intersil

Electrical Specifications ISL8843M - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V
are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Long Term Stability TA = 125°C, 1000 hours (Note 8) - 5 - mV

Current Limit, Sourcing -20 - - mA

Current Limit, Sinking 5--mA

CURRENT SENSE

Input Bias Current V

CS Offset Voltage V

COMP to PWM Comparator Offset Voltage V

Input Signal, Maximum 0.97 1.00 1.03 V

CS

= ∆V

Gain, A

CS to OUT Delay -3560ns

ERROR AMPLIFIER

Open Loop Voltage Gain (Note 8) 60 90 - dB

Unity Gain Bandwidth (Note 8) 1.0 1.5 - MHz

Reference Voltage V

FB Input Bias Current V

COMP Sink Current V

COMP Source Current V

COMP VOH V

COMP VOL V

PSRR Frequency = 120Hz, V

OSCILLATOR

Frequency Accuracy Initial, T

Frequency Variation with V

Temperature Stability (Note 8) - - 5 %

Amplitude, Peak to Peak Static Test - 1.75 - V

RTCT Discharge Voltage (Valley Voltage) Static Test - 1.0 - V

Discharge Current RTCT = 2.0V 6.2 8.0 8.5 mA

OUTPUT

Gate VOH V

Gate VOL OUT - GND, I

Peak Output Current C

Rise Time C

Fall Time C

GATE VOL UVLO Clamp Voltage VDD = 5V, I

PWM

Maximum Duty Cycle COMP = VREF 93.5 95 - %

Minimum Duty Cycle COMP = GND - - 0 %

NOTES:

6. Specifications at -55°C and 125°C are guaranteed by 25°C test with margin limits.

7. This is the V

8. Guaranteed by design, not 100% tested in production.

/∆VCS 0 < VCS < 910mV, VFB = 0V 2.5 3.0 3.5 V/V

COMP

DD

current consumed when the device is active but not switching. Does not include gate drive current.

DD

= 25°C (Continued)

A

CS

CS

CS

FB

FB

COMP

COMP

FB

FB

18V (Note 8)

TA = 25°C, (F

DD

OUT

OUT

OUT

= 1V -1.0 - 1.0 µA

= 0V (Note 8) 95 100 105 mV

= 0V (Note 8) 0.80 1.15 1.30 V

= V

= 0V -1.0 -0.2 1.0 µA

= 2.3V 4.80 - VREF V

= 2.7V 0.4 - 1.0 V

- OUT, I

= 1nF (Note 8) - 1.0 - A

= 1nF (Note 8) - 20 40 ns

= 1nF (Note 8) - 20 40 ns

= 15V, RT = 10kΩ, CT = 3.3nF, TA = -55 to 125°C (Note 6), Typical values

DD

COMP

= 1.5V, VFB = 2.7V 1.0 - - mA

= 1.5V, VFB = 2.3V -0.4 - - mA

= 12V to

DD

= 25°C 485153kHz

A

- F9V)/F

30V

OUT

OUT

LOAD

30V

= -200mA - 1.0 2.0 V

= 200mA - 1.0 2.0 V

= 1mA - - 1.2 V

2.460 2.500 2.535 V

60 80 - dB

-0.21.0%

6

FN9238.1

January 3, 2006

Typical Performance Curves

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ISL8843

1.01

1

0.99

NORMALIZED FREQUENCY

0.98

-60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 1. FREQUENCY vs TEMPERATURE FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

1.001

1.000

0.998

0.997

NORMALIZED EA REFERENCE

0.996

-60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 3. EA REFERENCE vs TEMPERATURE FIGURE 4. RTCT vs FREQUENCY

1.001

1.000

0.999

0.998

0.997

NORMALIZED VREF

0.996

0.995

-60 -40 -20 0 20 40 60 80 100

TEMPERATURE (°C)

3

1•10

100

10

FREQUENCY (kHz)

1

1 10 100

RT (kΩ)

140120

CT =
100pF

220pF
330pF
470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

Pin Descriptions

RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a
timing capacitor, CT, from this pin to GND. The oscillator
produces a sawtooth waveform with a programmable
frequency range up to 2.0MHz. The charge time, T
discharge time, T

, the switching frequency, f, and the

D

maximum duty cycle, Dmax, can be approximated from the
following equations:

TC0.533 RT CT••≈

0.008 RT 3.83–•



T

RT– CT

D

f 1T

DT

CTD

C

+()⁄=

f•=

----------------------------------------------

ln••≈



0.008 RT 1.71–•

7

, the

C

(EQ. 1)

(EQ. 2)

(EQ. 3)

(EQ. 4)

The formulae have increased error at higher frequencies due
to propagation delays. Figure 4 may be used as a guideline
in selecting the capacitor and resistor values required for a
given frequency.

COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.

FB - The output voltage feedback is connected to the
inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a
reference voltage.

CS - This is the current sense input to the PWM comparator.
The range of the input signal is nominally 0 to 1.0V and has
an internal offset of 100mV.

GND - GND is the power and small signal reference ground
for all functions.

FN9238.1

January 3, 2006

ISL8843

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OUT - This is the drive output to the power switching device.
It is a high current output capable of driving the gate of a

power MOSFET with peak currents of 1.0A. This GATE

output is actively held low when V

is below the UVLO

DD

threshold.

V

- VDD is the power connection for the device. The total

DD

supply current will depend on the load applied to OUT. Total
I

current is the sum of the operating current and the

DD

average output current. Knowing the operating frequency, f,
and the MOSFET gate charge, Qg, the average output
current can be calculated from:

I

OUT

Qg f×=

To optimize noise immunity, bypass V
ceramic capacitor as close to the V

DD

to GND with a

DD

and GND pins as

(EQ. 5)

possible.

VREF - The 5.00V reference voltage output. +1.0/-1.5%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1µF to 3.3µF capacitor to filter this output as
needed.

Functional Description

Features

The ISL8843 current mode PWM makes an ideal choice for
low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts,
it is the obvious choice for new designs or existing designs
which require updating.

Oscillator

The ISL8843 has a sawtooth oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor from VREF and a capacitor to GND on the RTCT

pin. (Please refer to Figure 4 for the resistor and capacitance

required for a given frequency.)

Soft-Start Operation

Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.

The COMP pin is clamped to the voltage on capacitor C1
plus a base-emitter junction by transistor Q1. C1 is charged
from VREF through resistor R1 and the base current of Q1.
At power-up C1 is fully discharged, COMP is at ~0.7V, and
the duty cycle is zero. As C1 charges, the voltage on COMP
increases, and the duty cycle increases in proportion to the
voltage on C1. When COMP reaches the steady state
operating point, the control loop takes over and soft start is
complete. C1 continues to charge up to VREF and no longer
affects COMP. During power down, diode D1 quickly
discharges C1 so that the soft start circuit is properly
initialized prior to the next power on sequence.

Gate Drive

The ISL8843 is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole
output of the IC (OUT pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.

Slope Compensation

For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale
current feedback signal. For applications where the duty
cycle is greater than 50%, slope compensation is required to
prevent instability.

Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by
subtracting the external ramp from the voltage feedback
error signal. Adding the external ramp to the current
feedback signal is the more popular method.

From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is

Fm

1

------------------- -=

SnTsw

(EQ. 6)

where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes

Fm

1

---------------------------------------

Sn Se+()Tsw

where Se is slope of the external ramp and

m

c

Se

1

-------+=

Sn

D1 R1

C1

VREF

ISL8843

COMP

Q1

GND

The criteria for determining the correct amount of external

FIGURE 5. SOFT-START

ramp can be determined by appropriately setting the
damping factor of the double-pole located at the switching

8

1

----------------------------==

m

SnTsw

c

(EQ. 7)

(EQ. 8)

FN9238.1

January 3, 2006

ISL8843

www.BDTIC.com/Intersil

frequency. The double-pole will be critically damped if the
Q-factor is set to 1, over-damped for Q < 1, and under­damped for Q > 1. An under-damped condition may result in
current loop instability.

Q

-------------------------------------------------=

π m

1

1D–()0.5–()

c

(EQ. 9)

where D is the percent of on time during a switching cycle.
Setting Q = 1 and solving for Se yields

S

eSn

1





-- - 0.5+

=





π

1

-------------

1D–

1–

(EQ. 10)

Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by Ton to obtain the voltage change that occurs during Ton.

V

eVn

1





=

-- -





π

1

-------------

0.5+
1D–

1–

(EQ. 11)

where Vn is the change in the current feedback signal (∆I)
during the on time and Ve is the voltage that must be added
by the external ramp.

For a flyback converter, Vn can be solved for in terms of
input voltage, current transducer components, and primary
inductance, yielding

Substituting Equations 12 and 13 into Equation 14 and
solving for R

-------------------------------------------------------------- ----------------------------------------------------------------- ------------------------- -=

R

CS

DT

---------------------------------

yields

CS

⋅⋅

swVIN

L

p

1

1

-- - 0.5+



π



----------------- -

⋅



1D–



N

s

-------

1–

N

p

1D–()V



+

⋅+

I



O



⋅⋅

2L

OTsw

s

(EQ. 15)

----------------------------------------------

Adding slope compensation is accomplished in the ISL8843
using an external buffer transistor and the RTCT signal. A
typical application sums the buffered RTCT signal with the
current sense feedback and applies the result to the CS pin
as shown in Figure 6.

VREF

R9

R6

C4

ISL8843

CS

RTCT

DT⋅

----------------------------------------------------

V

= V

e

where R
switching frequency, L

⋅⋅

SWVINRCS

L

p

is the current sense resistor, T

CS

1





-- - 0.5+





π

is the primary inductance, VIN is the

p

1

-------------

1D–

1–

(EQ. 12)

is the

SW

minimum input voltage, and D is the maximum duty cycle.

The current sense signal at the end of the ON time for CCM
operation is:

NSRCS⋅

------------------------

= V (EQ. 13)

V

CS

where V
L

is the secondary winding inductance, and IO is the output

s

N

P

is the voltage across the current sense resistor,

CS

1D–()VOT⋅⋅



+

I

----------------------------------------------



O



2L

sw

s

current at current limit. Equation 13 assumes the voltage
drop across the output rectifier is negligible.

Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value when the output load is at the current limit
threshold.

V

+ 1=

eVCS

(EQ. 14)

FIGURE 6. SLOPE COMPENSATION

Assuming the designer has selected values for the RC filter
(R6 and C4) placed on the CS pin, the value of R9 required
to add the appropriate external ramp can be found by
superposition.

2.05D R6⋅

= V

V

---------------------------- -

e

R6 R9+

(EQ. 16)

The factor of 2.05 in Equation 16 arises from the peak
amplitude of the sawtooth waveform on RTCT minus a base­emitter junction drop. That voltage multiplied by the
maximum duty cycle is the voltage source for the slope
compensation. Rearranging to solve for R9 yields:

2.05D V

–()R6⋅

R9

-----------------------------------------------= Ω

V

e

The value of R

e

determined in Equation 15 must be

CS

(EQ. 17)

rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 13. The divider created
by R6 and R9 makes this necessary.

R6 R9+

CS

----------------------

R9

⋅=

R

CS

(EQ. 18)

R′

9

FN9238.1

January 3, 2006

Example:

www.BDTIC.com/Intersil

VIN = 12V

VO = 48V

Ls = 800µH

Ns/Np = 10

Lp = 8.0µH

IO = 200mA

Switching Frequency, Fsw = 200kHz
Duty Cycle, D = 28.6%
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 15.
RCS = 295mΩ

Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 12.

Ve = 92.4mV

ISL8843

Using Equation 17, solve for the summing resistor, R9, from
CT to CS.

R9 = 2.67kΩ

Determine the new value of R

R’CS = 350mΩ

Additional slope compensation may be considered for
design margin. The above discussion determines the
minimum external ramp that is required. The buffer transistor
used to create the external ramp from RTCT should have a
sufficiently high gain (>200) so as to minimize the required
base current. Whatever base current is required reduces the
charging current into RTCT and will reduce the oscillator
frequency.

, R’CS, using Equation 18.

CS

Fault Conditions

A Fault condition occurs if VREF falls below 4.65V. When a
Fault is detected OUT is disabled. When VREF exceeds

4.80V, the Fault condition clears, and OUT is enabled.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. V
bypassed directly to GND with good high frequency
capacitors.

should be

DD

References

[1] Ridley, R., “A New Continuous-Time Model for Current

Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.

10

FN9238.1

January 3, 2006

Small Outline Plastic Packages (SOIC)

www.BDTIC.com/Intersil

ISL8843

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45°

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

M

A1

C

0.10(0.004)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/05

11

FN9238.1

January 3, 2006

ISL8843

www.BDTIC.com/Intersil

Mini Small Outline Plastic Packages (MSOP)

N

EE1

INDEX

AREA

AA1A2

-H-

SIDE VIEW

12

TOP VIEW

b

e

D

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- H -

-A -

.

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen­sions are for reference only.

-B-

0.20 (0.008) A

GAUGE
PLANE

SEATING

PLANE

0.10 (0.004) C

-A-

0.20 (0.008) C

- B -

0.25

(0.010)

-C-

SEATING
PLANE

a

0.20 (0.008) C

- H -

B

4X θ

C

D

4X θ

L1

C

C

L

E

1

END VIEW

R1

R

L

-B-

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.037 0.043 0.94 1.10 ­A1 0.002 0.006 0.05 0.15 ­A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

0 5

α

o

o

0

15

o

o

6

o

5

o

0

15

o

o

6

Rev. 2 01/03

NOTESMIN MAX MIN MAX

-

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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12

FN9238.1

January 3, 2006