®
ISL6269A
Data Sheet May 30, 2007
High-Performance Notebook PWM
Controller
The ISL6269A IC is a Single-Phase Synchronous-Buck
PWM controller featuring Intersil's Robust Ripple Regulator
3
(R
) technology that delivers truly superior dynamic
response to input voltage and output load transients.
Integrated MOSFET drivers and bootstrap diode result in
fewer components and smaller implementation area.
Intersil’s R
3
technology combines the best features of fixedfrequency PWM and hysteretic PWM while eliminating many
of their shortcomings. R
modulator that synthesizes an AC ripple voltage signal V
3
technology employs an innovative
,
R
analogous to the output inductor ripple current. The AC
signal V
threshold is the error amplifier output V
threshold is a programmable voltage reference V
in generation of the PWM signal. The voltage reference V
enters a window comparator where the lower
R
, and the upper
COMP
resulting
W,
W
sets the steady-state PWM frequency. Both edges of the
PWM can be modulated in response to input voltage
transients and output load transients, much faster than
conventional fixed-frequency PWM controllers. Unlike a
conventional hysteretic converter, the ISL6269A has an error
amplifier that provides ±1% voltage regulation at the FB pin.
The ISL6269A has a 1.5ms digital soft-start and can be
started into a pre-biased output voltage. A resistor divider is
used to program the output voltage setpoint. The ISL6269A
can be configured to operate in continuous-conductionmode (CCM) or diode-emulation-mode (DEM), which
improves light-load efficiency. In CCM the controller always
operates as a synchronous rectifier however, when DEM is
enabled the low-side MOSFET is permitted to stay off,
blocking negative current flow into the low-side MOSFET
from the output inductor.
Pinout
ISL6269A
(16 LD 4x4 QFN)
TOP VIEW
PGOODUGPHASE
1516 14 13
BOOT
FN9253.2
Features
• High performance R3 technology
• Fast transient response
• ±1% regulation accuracy: -10°C to +100°C and
-40°C to +100°C
• Wide input voltage range: +5.0V to +25.0V
• Output voltage range: +0.6V to +3.3V
• Wide output load range: 0A to 25A
• Selectable diode emulation mode for increased light load
efficiency
• Programmable PWM frequency: 200kHz to 600kHz
• Pre-biased output start-up capability
• Integrated MOSFET drivers and bootstrap diode
• Internal digital soft-start
• Power good monitor
• Fault protection
- Undervoltage protection
- Soft crowbar overvoltage protection
- Low-side MOSFET r
overcurrent protection
DS(ON)
- Over-temperature protection
- Fault identification by PGOOD pull down resi stance
• Pb-free plus anneal available (RoHS compliant)
Applications
• PCI express graphical processing unit
• Auxiliary power rail
•VRM
• Network adapter
Ordering Information
TEMP
PART NUMBER
(Note)
ISL6269ACRZ* 62 69ACRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
PART
MARKING
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
VIN
VCC
FCCM
EN
VO
PVCC
12
LG
11
10
PGND
9
ISEN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
1
2
3
4
GND
6578
FB
COMP
FSET
1
ISL6269AIRZ* 62 69AIRZ -40 to +100 16 Ld 4x4 QFN L16.4x4
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Block Diagram
VIN
GND
VCC
2
EN
PACKAGE BOTTOM
V
REF
−
OVP
+
−
UVP
+
+
+
gmV
−
gmV
−
PWM FREQUENCY
CONTROL
−
+
IN
V
W
−
+
R
PWM
V
R
O
+
C
R
V
COMP
−
+
Q
S
−
VO
FSET
ISL6269A
BOOT
+
EA
FB
−
EA
POR
DRIVER
DIGITAL SOFT-START
UG
COMP
ISEN
PGOOD
May 30, 2007
FN9253.2
−
I
OC
OCP
+
30Ω
90Ω
FIGURE 1. SCHEMATIC BLOCK DIAGRAM
60Ω
150°OT
PWM CONTROL
SHOOT THROUGH
PROTECTION
DRIVER
PHASE
PVCC
LG
PGND
FCCM
Typical Application
5V
R
VCC
R
PGOOD
PGOOD
PVCC
ISL6269A
ISL6269A
VIN
UG
V
IN
5V TO 25V
C
IN
Q
HIGH_SIDE
C
PVCC
R
COMP
C
VCC
C
COMP1
VCC
GND
FCCM
EN
COMP
BOOT
PHASE
ISEN
LG
PGND
C
BOOT
R
SEN
L
OUT
Q
LOW_SIDE
V
OUT
0.6V TO 3.3V
C
OUT
C
COMP2
R
BOTTOM
R
FB
VO
TOP
FSET
FIGURE 2. ISL6269A TYPICAL APPLICATION SCHEMATIC
3
R
FSET
C
FSET
FN9253.2
May 30, 2007
ISL6269A
Absolute Voltage Ratings
ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V
VCC, PGOOD to GND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V
VO, FB, COMP, FSET . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V
PHASE to GND (DC). . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +28V
(<100ns Pulse Width, 10μJ). . . . . . . . . . . . . . . . . . . . . . . . . -5.0V
BOOT to GND, or PGND. . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7V
UG (DC). . . . . . . . . . . . . . . . . . . . . . .-0.3V to PHASE, BOOT +0.3V
(<200ns Pulse Width, 20μJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PGND, PVCC +0.3V
(<100ns Pulse Width, 4μJ). . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . . 48 11.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6269AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6269AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 5V to 25V
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTES:
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
1. θ
JA
Tech Brief TB379.
2. For θ
Electrical Specifications These specifications apply for V
, the “case temp” location is the center of the exposed metal pad on the package underside.
JC
= 15V, TA = -40°C to +100°C, unless otherwise stated.
All typical specifications T
IN
= +25°C, VCC = 5V, PVCC = 5V, VIN = 15V
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VIN
VIN Input Bias Current I
VIN
EN = 5V, VIN = 5V - 6.5 10 μA
EN = 5V, VIN = 25V - 26 35 μA
VIN Shutdown Current I
VIN_SHDN
EN = GND, VIN = 25V - 0.1 1.0 μA
VCC and PVCC
VCC Input Bias Current I
VCC Shutdown Current I
PVCC Shutdown Current I
VCC_SHDN
PVCC_SHDN
VCC
EN = 5V, FCCM = GND, FB = 0.65V - 1.7 2.5 mA
EN = GND, VCC = 5V - 0.1 1.0 μA
EN = GND, PVCC = 5V - 0.1 1.0 μA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage V
VCC_THRTA
= -10°C to +100°C 4.35 4.45 4.55 V
4.33 4.45 4.55 V
Falling VCC POR Threshold Voltage
V
VCC_THFTA
= -10°C to +100°C 4.10 4.20 4.30 V
4.08 4.20 4.30 V
REGULATION
Reference Voltage V
REF
- 0.6 - V
Regulation Accuracy FB connected to COMP -1 - +1 %
PWM
Frequency Range f
SW
Frequency-Set Accuracy f
VO Range V
VO Input Leakage
VO
I
VO
FCCM = 5V 200 - 600 kHz
= 300kHz -12 - +12 %
SW
0.60 - 3.30 V
VO = 0.60V - 1.3 - μA
VO = 3.30V - 7.0 - μA
ERROR AMPLIFIER
FB Input Bias Current I
FB
FB = 0.60V -0.5 - +0.5 μA
4
FN9253.2
May 30, 2007
ISL6269A
Electrical Specifications These specifications apply for V
All typical specifications T
= 15V, TA = -40°C to +100°C, unless otherwise stated.
IN
= +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
A
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
COMP Source Current I
COMP Sink Current I
COMP High Clamp Voltage V
COMP Low Clamp Voltage V
COMP_SRC
COMP_SNK
COMP_HC
COMP_LC
FB = 0.40V, COMP = 3.20V - 2.5 - mA
FB = 0.80V, COMP = 0.30V - 0.3 - mA
FB = 0.40V, Sink 50μA 3.10 3.40 3.65 V
FB = 0.80V, Source 50μA 0.09 0.15 0.21 V
POWER GOOD
PGOOD Pull-down Impedance R
PG_SS
PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 Ω
PGOOD = 5mA Sink 67 95 125 Ω
R
PG_UV
PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 Ω
PGOOD = 5mA Sink 67 95 125 Ω
R
PG_OV
PGOOD = 5mA Sink, TA = -10°C to +100°C 50 63 85 Ω
PGOOD = 5mA Sink 45 63 85 Ω
R
PG_OC
PGOOD = 5mA Sink, TA = -10°C to +100°C 25 32 45 Ω
PGOOD = 5mA Sink 22 32 45 Ω
PGOOD Leakage Current I
PGOOD
PGOOD = 5V - 0.1 1.0 μA
PGOOD Maximum Sink Current (Note 3) - 5.0 - mA
PGOOD Soft-Start Delay t
SS
EN High to PGOOD High, TA = -10°C to +100°C 2.20 2.75 3.30 ms
EN High to PGOOD High 2.20 2.75 3.50 ms
GATE DRIVER
UG Pull-Up Resistance R
UG Source Current (Note 3) I
UG Sink Resistance R
UG Sink Current (Note 3) I
LG Pull-Up Resistance R
LG Source Current (Note 3) I
LG Sink Resistance R
LG Sink Current (Note 3) I
UG to LG Deadtime t
LG to UG Deadtime t
UGPU
UGSRC
UGPD
UGSNK
LGPU
LGSRC
LGPD
LGSNK
UGFLGR
LGFUGR
200mA Source Current - 1.0 1.5 Ω
UG - PHASE = 2.5V - 2.0 - A
250mA Sink Current - 1.0 1.5 Ω
UG - PHASE = 2.5V - 2.0 - A
250mA Source Current - 1.0 1.5 Ω
LG - PGND = 2.5V - 2.0 - A
250mA Sink Current - 0.5 0.9 Ω
LG - PGND = 2.5V - 4.0 - A
UG falling to LG rising, no load - 21 - ns
LG falling to UG rising, no load - 14 - ns
BOOTSTRAP DIODE
Forward Voltage V
Reverse Leakage I
R
PVCC = 5V, IF = 2mA - 0.58 - V
F
VR = 25V - 0.2 - μA
CONTROL INPUTS
EN High Threshold V
EN Low Threshold V
FCCM High Threshold V
FCCM Low Threshold V
FCCMTHR
FCCMTHF
EN Leakage I
FCCM Leakage I
I
ENTHR
ENTHF
ENL
I
ENH
FCCML
FCCMH
EN = 0V - 0.1 1.0 μA
EN = 5.0V - 0.1 1.0 μA
FCCM = 0V - 0.1 1.0 μA
FCCM = 5.0V - 2.0 - μA
2.0 --V
--1.0 V
2.0 --V
--1.0 V
5
FN9253.2
May 30, 2007
ISL6269A
Electrical Specifications These specifications apply for V
All typical specifications T
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
PROTECTION
ISEN OCP Threshold I
ISEN Short-Circuit Threshold I
UVP Threshold V
OVP Rising Threshold V
OVP Falling Threshold V
OTP Rising Threshold (Note 3) T
OTP Hysteresis (Note 3) T
NOTE:
3. Guaranteed by characterization.
OC
SC
UV
OVR
OVF
OTR
OTHYS
= +25°C, VCC = 5V, PVCC = 5V, VIN = 15V (Continued)
A
ISEN sourcing, TA = -10°C to +100°C 19 26 33 μA
ISEN sourcing 17 26 33 μA
ISEN sourcing - 50 - μA
Functional Pin Descriptions
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
VIN (Pin 1)
The VIN pin measures the converter input voltage which is a
required input to the R3 PWM modulator. Connect across
the drain of the high-side MOSFET to the GND pin.
VCC (Pin 2)
The VCC pin is the input bias voltage for the IC. Connect
+5V from the VCC pin to the GND pin. Decouple with at least
1µF of a MLCC capacitor from the VCC pin to the GND pin.
FCCM (Pin 3)
The FCCM pin configures the controller to operate in forcedcontinuous-conduction-mode (FCCM) or diode-emulationmode (DEM.) DEM is disabled when the FCCM pin is pulled
above the rising threshold voltage V
FCCMTHR
DEM is enabled when the FCCM pin is pulled below the
falling threshold voltage V
FCCMTHF.
EN (Pin 4)
The EN pin is the on/off switch of the IC. The soft-start
sequence begins when the EN pin is pulled above the rising
threshold voltage V
reset (POR) rising threshold voltage
and VCC is above the power-on
ENTHR
V
VCC_THR
EN pin is pulled below the falling threshold voltage V
PWM immediately stops.
COMP (Pin 5)
The COMP pin is the output of the control-loop error
amplifier. Compensation components for the control-loop
connect across the COMP and FB pins.
FB (Pin 6)
The FB pin is the inverting input of the control-loop error
amplifier. The converter output voltage regulates to 600mV
, conversely
. When the
ENTHF
= 15V, TA = -40°C to +100°C, unless otherwise stated.
IN
81 84 87 %
113 116 119 %
100 103 106 %
- 150 - °C
- 25 - °C
from the FB pin to the GND pin. Program the desired output
voltage with a resistor network connected across the VO,
FB, and GND pins. Select the resistor values such that FB to
GND is 600mV when the converter output voltage is at the
programmed regulation value.
FSET (Pin 7)
The FSET pin programs the PWM switching frequency.
Program the desired PWM frequency with a resistor and a
capacitor connected across the FSET and GND pins.
VO (Pin 8)
The VO pin measures the converter output voltage and is
used exclusively as an input to the R
Connect at the physical location where the best output
voltage regulation is desired.
ISEN (Pin 9)
The ISEN pin programs the threshold of the OCP
overcurrent fault protection. Program the desired OCP
threshold with a resistor connected across the ISEN and
PHASE pins. The OCP threshold is programmed to detect
the peak current of the output inductor. The peak current is
the sum of the DC and AC components of the inductor
current.
PGND (Pin 10)
The PGND pin conducts the turn-off transient current
through the LG gate driver. The PGND pin must be
connected to complete the pulldown circuit of the LG gate
driver. The PGND pin should be connected to the source of
the low-side MOSFET through a low impedance path,
preferably in parallel with the trace connecting the LG pin to
the gate of the low-side MOSFET. The adaptive shootthrough protection circuit, measures the low-side MOSFET
gate-source voltage from the LG pin to the PGND pin.
3
PWM modulator.
6
FN9253.2
May 30, 2007
ISL6269A
LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
PGND pin. Decouple with at least 1µF of an MLCC capacitor
across the PVCC and PGND pins.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
diode.
UG (Pin 14)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
The negative slope of V
V
RNEGgmVOUT
Where g
⋅=
is the gain of the transconductance amplifier.
m
can be written as:
R
(EQ. 2)
A window voltage VW is referenced with respect to the error
amplifier output voltage V
which the ripple voltage V
V
is set by a resistor connected across the FSET and GND
W
pins. The V
R, VCOMP,
comparator in which V
and V
is the higher threshold voltage. Figure 3 shows
W
and VW signals feed into a window
COMP
PWM pulses being generated as V
V
thresholds . The PWM switching frequency is
COMP
, creating an envelope into
COMP
is compared. The amplitude of
R
is the lower threshold voltage
traverses the VW and
R
proportional to the slew rates of the positive and negative
slopes of V
proportional to the voltage between V
Ripple Capacitor Voltage C
the PWM switching frequency is inversely
R;
R
Error Amplifier Voltage V
and V
W
Window Voltage V
COMP.
W
COMP
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
Theory of Operation
Modulator
The ISL6269A is a hybrid of fixed frequency PWM control,
and variable frequency hysteretic control. Intersil’s R
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The term “Ripple” in the name
“Robust-Ripple-Regulator” refers to the converter output
inductor ripple current, not the converte r ou tp u t rip p l e
voltage. The R
3
modulator synthesizes an AC signal VR,
which is an ideal representation of the output inductor ripple
current. The duty-cycle of V
is the result of charge and
R
discharge current through a ripple capacitor C
through C
is provided by a transconductance amplifier gm
R
that measures the VIN and VO pin voltages. The positive
slope of V
V
RPOSgm
can be written as:
R
()VINV
–()•=
OUT
3
. The current
R
(EQ. 1)
PWM
FIGURE 3. MODULA TOR W A VEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6269A is disabled until the voltage V
increased above the rising power-on reset (POR)
threshold voltage. The controller will become once again
disabled when the voltage
POR
V
VCC_THF
threshold voltage.
V
decreases below the falling
VCC
VCC
has
V
VCC_THR
EN, Soft-Start, and PGOOD
The ISL6269A uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage V
Soft-Start Delay t
starts and the output voltage begins to
SS
rise. The output voltage enters regulation in approximately
1.5ms and the PGOOD pin goes to high impedance once t
has elapsed.
ENTHR
the PGOOD
SS
7
FN9253.2
May 30, 2007
1.5ms
VOUT
VCC and PVCC
ISL6269A
connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a “boot
diode” each time the low-side MOSFET turns on, pulling the
PHASE pin low. The ISL6269A has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
EN
PGOOD
2.75ms
FIGURE 4. SOFT-START SEQUENCE
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if
POR threshold
threshold
V
VCC_THF
V
V
has not reached the rising
VCC
VCC_THR
, or if V
is below the falling POR
VCC
. The ISL6269A features a unique faultidentification capability that can drastically reduce troubleshooting time and effort. The pull-down resistance of the
PGOOD pin corresponds to the fault status of the controller.
During soft-start or if an undervoltage fault occurs, the
PGOOD pulldown resistance is 95Ω, or 30Ω for an
overcurrent fault, or 60Ω for an overvoltage fault.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION PGOOD RESISTANCE
VCC Below POR Undefined
Soft Start or Undervoltage 95Ω
Overvoltage 60Ω
Overcurrent 30Ω
MOSFET Gate-Drive Outputs LG and UG
The ISL6269A has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The LG gate-driver is
optimized for low duty-cycle applications where the low-side
MOSFET conduction losses are dominant, requiring a low
r
order to clamp the gate of the MOSFET below the V
turnoff. The current transient through the gate at turnoff can
be considerable because the switching charge of a low
r
protection prevents a gate-driver output from turning on until
the opposite gate-driver output has fallen below
approximately 1V. The dead-time shown in Figure 5. is
extended by the additional period that the falling gate voltage
stays above the 1V threshold. The high-side gate-driver
output voltage is measured across the UG and PHASE pins
while the low-side gate-driver output voltage is measured
across the LG and PGND pins. The power for the LG
gate-driver is sourced directly from the PVCC pin. The power
for the UG gate-driver is sourced from a “boot” capacitor
MOSFET. The LG pulldown resistance is small in
DS(ON)
MOSFET can be large. Adaptive shoot-through
DS(ON)
GS(th)
at
UG
LG
t
LGFUGR
50%
50%
FIGURE 5. LG AND UG DEAD-TIME
t
UGFLGR
Diode Emulation
The ISL6269A normally operates in continuous-conductionmode (CCM), minimizing conduction losses by forcing the
low-side MOSFET to operate as a synchronous rectifier. An
improvement in light-load efficiency is achieved by allowing
the converter to operate in diode-emulation-mode (DEM),
where the low-side MOSFET behaves as a smart-diode,
forcing the device to block negative inductor current flow.
The ISL6269A can be configured to operate in DEM by
setting the FCCM pin low. Setting the FCCM pin high will
disable DEM.
Positive-going inductor current flows from either the source
of the high-side MOSFET, or the drain of the low-side
MOSFET. Negative-going inductor current usually flows into
the drain of the low-side MOSFET. When the low-side
MOSFET conducts positive inductor current, the phase
voltage will be negative with respect to the GND and PGND
pins. Conversely, when the low-side MOSFET conducts
negative inductor current, the phase voltage will be positive
with respect to the GND and PGND pins. Negative inductor
current occurs when the output load current is less than ½
the inductor ripple current. Sinking negative inductor current
through the low-side MOSFET lowers efficiency through
unnecessary conduction losses. Efficiency can be further
improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. Upon entering
DEM, the PWM frequency makes an initial step-reduction
because of a 33% step-increase of the window voltage V
With FCCM pulled low, the converter will automatically enter
DEM after the PHASE pin has detected positive voltage,
W
3
.
8
FN9253.2
May 30, 2007
ISL6269A
while the LG gate-driver pin is high, for eight consecutive
PWM pulses. The converter will return to CCM on the
following cycle after the PHASE pin detects negative
voltage, indicating that the body diode of the low-side
MOSFET is conducting positive inductor current.
Overcurrent and Short-Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor R
connected across the ISEN and PHASE pins. The PHASE
pin is connected to the drain terminal of the low-side
MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to 30Ω
and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V
below the falling POR threshold voltage
ENTHF
or if V
V
VCC_THF
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current I
is assumed to be equal to the
D
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the r
of the low-side MOSFET that is
DS(ON)
measured shortly after the LG gate-driver output goes high.
The ISEN pin sources the OCP sense current I
the OCP programming resistor R
forcing the ISEN pin to
SEN,
zero volts with respect to the GND pin. The negative voltage
across the PHASE and GND pins is nulled by the voltage
dropped across R
fault occurs if I
I
while attempting to null the negative voltage across the
OC
PHASE and GND pins. I
PWM pulses that occur within 20µs. If I
as I
SEN
rises above the OCP threshold current
SEN
conducts through it. An OCP
SEN
must exceed IOC on all the
SEN
SEN
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when I
exceeds twice I
The relationship between ID and I
OC.
written as:
I
• I
SENRSEN
The value of R
⎛⎞
I
⎝⎠
R
----------------------------------------------------------------------------
=
SEN
FL
+
SEN
I
PP
-------- -
•=
DrDS ON()
is then written as:
• r
•
OC
SP
2
I
DS ON()
OC
that is
SEN
has decayed
VCC
.
through
SEN,
falls below IOC
SEN
SEN
(EQ. 3)
(EQ. 4)
is
Where:
-R
(Ω) is the resistor used to program the
SEN
overcurrent setpoint
is the current sense current that is sourced from
-I
SEN
the ISEN pin
-I
OC
is the I
threshold current sourced from the ISEN
SEN
pin that will activate the OCP circuit
is the maximum continuous DC load current
-I
FL
is the inductor peak-to-peak ripple current
-I
PP
-OC
is the desired overcurrent setpoint expressed as
SP
a multiplier relative to I
FL
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will pull
down to 60Ω
remain latched until V
POR threshold voltage
and latch-off the converter. The OVP fault will
has decayed below the falling
VCC
V
VCC_THF
.
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold V
Although the converter has
OVR.
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off, in response to the output voltage transversing the
V
OVR
and V
thresholds.
OVF
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95Ω
and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V
falling POR threshold voltage
ENTHF
or if V
V
has decayed below the
VCC
VCC_THF.
The UVP fault
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold V
UV
Over-Temperature
When the temperature of the ISL6269A increases above the
rising threshold temperature T
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T
OTHYS
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V
V
decays below the falling POR threshold voltage
VCC
V
VCC_THF
. All other protection circuits function normally
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold V
the PGOOD pin will pulldown to 95Ω and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V
threshold voltage
ENTHF
or if V
has decayed below the falling POR
VCC
V
VCC_THF
, the IC will enter an OTP
OTR
at which time normal PWM
ENTHF
.
or if
UV
.
;
9
FN9253.2
May 30, 2007
ISL6269A
Programming the Output Voltage
When the converter is in regulation there will be 600mV from
the FB pin to the GND pin. Connect a two-resistor voltage
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the
GND pin when the converter is regul a ti ng at the desired
output voltage. The output voltage can be programmed from
600mV to 3.3V.
Programming the output voltage is written as:
R
V
REFVOUT
BOTTOM
•=
---------------------------------------------------
R
+
TOPRBOTTOM
Where:
-V
-V
is the desired output voltage of the converter
OUT
is the voltage that the converter regulates to
REF
between the FB pin and the GND pin
-R
is the voltage-programming resistor that connects
TOP
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
compensation network
-R
BOTTOM
is the voltage-programming resistor that
connects from the FB pin to the GND pin
Beginning with R
R
BOTTOM
R
BOTTOM
is written as:
V
-------------------------------------
=
V
between 1kΩ to 5kΩ, calculating
TOP
R•
REF
TOP
–
OUTVREF
Programming the PWM Switching Frequency
The ISL6269A does not use a clock signal to produce PWM.
The PWM switching frequency f
resistor R
that is connected from the FSET pin to the
FSET
is programmed by the
SW
GND pin. The approximate PWM switching frequency is
written as:
SW
Estimating the value of R
R
FSET
⋅
KR
------------------
=
Kf
FSET
1
•
SW
is written as:
FSET
1
---------------------------
f
=
Where:
is the PWM switching frequency
-f
SW
-R
- K = 75 x 10
is the fSW programming resistor
FSET
-12
It is recommended that whenever the control loop
compensation network is modified, f
should be checked
SW
for the correct frequency and if necessary, adjust R
Compensation Design
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R
modulator used in the ISL6269A makes the LC output filter
resemble a first order system in which the closed loop stability
can be achieved with a Type II compensation network.
(EQ. 5)
(EQ. 6)
(EQ. 7)
(EQ. 8)
FSET
3
.
R2
COMP
-
EA
C2
C1
R1
FB
+
REF
FSET
R
FSET
R3 MODULATOR
VO
VOUT
VIN
Q
UG
PHASE
GATE DRIVERS
Q
LG
GND
ISL6269A
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
VIN
HIGH_SIDE
L
OUT
LOW_SIDE
DCR
C
OUT
C
ESR
C
FSET
Your local Intersil representative ca n pro v i d e a PC -b ase d
tool that can be used to calculate compensation network
component values and help simulate the loop frequency
response. The compensation network consists of the internal
error amplifier of the ISL6269A and the external components
R1, R2, C1, and C2 as well as the frequency setting
components R
FSET
, and C
are identified in the
FSET,
schematic Figure 6.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a single-phase
power converter. It is assumed that the reader is famil iar with
many of the basic skills and techniques referenced below. In
10
FN9253.2
May 30, 2007
Δ
ISL6269A
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as:
V
OUT
--------------- -
D
=
V
IN
The output inductor peak-to-peak ripple current is written as:
V
1D–()•
OUT
--------------------------------------
=
I
PP
fSWL
•
OUT
A typical step-down DC/DC converter will have an I
20% to 40% of the maximum DC output load current. The
value of I
is selected based upon several criteria such as
PP
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by:
P
COPPERILOAD
Where I
LOAD
2
DCR•=
is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance
C
into which ripple current IPP can flow. Current IPP
OUT
develops a corresponding ripple voltage V
across C
PP
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from charge
moved in and out of the capacitor. These two voltages are
written as:
ΔV
ESRIPP
E• SR=
and
I
PP
-------------------------------------
V
=
C
8C
f•
•
OUT
SW
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be parallel ed
to reduce the total ESR until the required V
is achieved.
PP
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors constructed with reverse package
geometry are available. A capacitor dissipates heat as a
function of RMS current and frequency . Be sure tha t I
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at f
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
(EQ. 9)
(EQ. 10)
of
PP
(EQ. 11)
OUT,
(EQ. 12)
(EQ. 13)
is
PP
SW
.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 7 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
I
IN_RMS
2
I
-----------------------------------------------------------------------------------------------------
=
MAX
DD2–()⋅()xI
⎛⎞
+
⎝⎠
I
MAX
2
D
MAX
------
12
⋅⋅
(EQ. 14)
Where:
-I
is the maximum continuous I
MAX
of the converter
LOAD
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of I
(0% to 100%)
MAX
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter which is written as:
V
OUT
--------------------------
D
=
VINEFF⋅
(EQ. 15)
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
NORMALIZED INPUT RMS RIPPLE CURRENT
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
DUTY CYCLE
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
rating that exceeds the sum of the
DS
There are several power MOSFET s readily available that are
optimized for DC/DC converter applications. The preferred
11
FN9253.2
May 30, 2007
ISL6269A
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
V
IN-VOUT-VL
emphasizes low r
across it. The preferred low-side MOSFET
when fully saturated to minimize
DS(ON)
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
P
CON_LSILOAD
r⋅
DS ON()_LS
1D–()•≈
(EQ. 16)
2
For the high-side MOSFET, (HS), its conduction loss is
written as:
P
CON_HSILOAD
2
r•
DS ON()_HS
D•=
(EQ. 17)
For the high-side MOSFET, its switching loss is written as:
P
SW_HS
VINI
VALLEYtON
---------------------------------------------------------------- -
2
f•
••
V
INIPEAKtOFF
SW
-------------------------------------------------------------
+=
f•
••
2
SW
(EQ. 18)
Where:
-I
is the difference of the DC component of the
VALLEY
inductor current minus 1/2 of the inductor ripple current
-I
is the sum of the DC component of the inductor
PEAK
current plus 1/2 of the inductor ripple current
is the time required to drive the device into
-t
ON
saturation
is the time required to drive the device into cut-off
-t
OFF
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
C
BOOT
------------------------
=
ΔV
g
BOOT
(EQ. 19)
Q
Where:
is the total gate charge required to turn on the
-Q
g
high-side MOSFET
- ΔV
, is the maximum allowed voltage decay across
BOOT
the boot capacitor each time the high-side MOSFET is
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q
, of 25nC at VGS= 5V, and a ΔV
g
BOOT
of
200mV . The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the compensation
components, and the FSET components. The island should be
connected to the rest of the ground plane layer at one point.
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
GND
VOUT
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R
and capacitor C
should be placed directly adjacent to
FSET
FSET
this pin. Keep fast moving nodes away from this pin.
12
FN9253.2
May 30, 2007
ISL6269A
ISEN (Pin 9)
Route the connection to the ISEN pin away from the traces
and components connected to the FB pin, COMP pin, and
FSET pin.
LG (Pin 11)
The signal going through this trace is both high dv/dt and
high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
These two traces should be short, wide, and away from
other traces. There should be no other weak signal traces in
proximity with these traces on any layer.
BOOT (Pin 13), UG (Pin 14), and PHASE (Pin 15)
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UG and PHASE pins in parallel with short
and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
13
FN9253.2
May 30, 2007
ISL6269A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)
MILLIMETERS
SYMBOL
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.23 0.28 0.35 5, 8
D 4.00 BSC -
D1 3.75 BSC 9
D2 1.95 2.10 2.25 7, 8
E 4.00 BSC -
E1 3.75 BSC 9
E2 1.95 2.10 2.25 7, 8
e 0.65 BSC -
k0.25 - - -
L 0.50 0.60 0.75 8
L1 - - 0.15 10
N162
Nd 4 3
Ne 4 3
P- -0.609
θ --129
NOTES:
1. Dimensioning and tolerances conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist w ith PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
NOTESMIN NOMINAL MAX
Rev. 5 5/04
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN9253.2
May 30, 2007
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