Intersil ISL6266AIRZ, ISL6266HRZ Schematics

ISL6266, ISL6266A

Data Sheet August 25, 2015

Two-phase Core Controllers (Montevina, IMVP-6+)

The ISL6266 and ISL6266A are two-phase buck converter regulators implementing Intel® IMVP-6 protocol with embedded gate drivers. Both converters use interleaved channels to double the output voltage ripple frequency and thereby reduce output voltage ripple amplitude with fewer components, lower component cost, reduced power dissipation, and smaller real estate area.

The ISL6266A utilizes the patented R Intersil’s Robust Ripple Regulator modulator. Compared with traditional multiphase buck regulators, the R has the fastest transient response. This is due to the R modulator commanding variable switching frequency during load transient events.

Intel Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology, which effectively reduces power dissipation in Intel Pentium processors. To boost battery life, the ISL6266A supports DPRSLRVR (deeper sleep), DPRSTP# and PSI# functions, which maximizes efficiency by enabling different modes of operation. In active mode (heavy load), the regulator commands the two phase continuous conduction mode (CCM) operation. When PSI# is asserted in active mode (medium load), the ISL6266A operates in one-phase CCM. When the CPU enters deeper sleep mode, the ISL6266A enables diode emulation to maximize efficiency.

Technology™,

Technology™

FN6398.4

Features

• Precision Two/One-phase CORE Voltage Regulator

- 0.5% System Accuracy Over-Temperature

- Enhanced Load Line Accuracy

• Internal Gate Driver with 2A Driving Capability

• Dynamic Phase Adding/Dropping

• Microprocessor Voltage Identification Input

- 7-Bit VID Input

- 0.300V to 1.500V in 12.5mV Steps

- Support VID Change On-the-Fly

• Multiple Current Sensing Schemes Supported

- Lossless Inductor DCR Current Sensing

- Precision Resistive Current Sensing

• CPU Power Monitor

• Thermal Monitor

• User Programmable Switching Frequency

• Differential Remote CPU Die Voltage Sensing

• Static and Dynamic Current Sharing

• Support All Ceramic Output with Coupled Inductor (ISL6266)

• Overvoltage, Undervoltage and Overcurrent Protection

• Pb-Free (RoHS Compliant)

For better system power management, the ISL6266A provides a CPU power monitor output. The analog output at the power monitor pin can be fed into an A/D converter to report instantaneous or average CPU power.

A 7-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V. Over-temperature, the ISL6266A achieves a 0.5% system accuracy of core output voltage.

A unity-gain differential amplifier is provided for remote CPU die sensing. This allows the voltage on the CPU die to be accurately measured and regulated per Intel IMVP-6+ specifications. Current sensing can be realized using either lossless inductor DCR sensing or discrete resistor sensing. A single NTC thermistor network thermally compensates the gain and the time constant of the DCR variations.

The ISL6266 also includes all the functions for IMVP-6+

core power delivery. In addition, it has been optimized for use with coupled-inductor solutions. More information on the differences between ISL6266 and ISL6266A can be found in the “Electrical Specifications” on page 3 and the “ISL6266 Features” on page 21.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Ordering Information

TEMP.

PART NUMBER

(Note)

ISL6266HRZ

(No longer available or supported)

ISL6266HRZ-T*

(No longer available or supported)

ISL6266AIRZ ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7

ISL6266AIRZ-T* ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

| Intersil (and design) is a registered trademark of Intersil Americas LLC.

All other trademarks mentioned are the property of their respective owners.

PAR T

MARKING

ISL6266 HRZ -10 to +100 48 Ld 7x7 QFN L48.7x7

Technology™ is a trademark of Intersil Americas LLC.

RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

Pinout

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VDIFF

VSEN

RTN

DROOP

DFB

VSUM

VIN

GND

VDD

ISEN2

ISEN1

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

PGOOD

PSI#

PMON

RBIAS

VR_TT#

NTC

SOFT

OCSET

COMP

FB2

GND PAD

(BOTTOM)

ISL6266, ISL6266A

(48 LD 7x7 QFN)

TOP VIEW

FN6398.4

August 25, 2015

ISL6266, ISL6266A

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Battery Voltage (V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot to Phase Voltage (BOOT to PHASE). . . . . . -0.3V to +7V (DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns)

Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . PHASE -0.3V (DC) to BOOT

. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage (LGATE) . . . . . . . . . . . -0.3V (DC) to (VDD + 0.3V)

. . . . . . . . . . . . . .-2.5V (<20ns Pulse Width, 5µJ) to (VDD + 0.3V)

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)

Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . -0.3V to+7V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. 

Tech Brief TB379.

2. For 

, the “case temp” location is the center of the exposed metal pad on the package underside.

Thermal Resistance (Typical)

JA

°C/W JC°C/W

QFN Package (Notes 1, 2). . . . . . . . . . 29 4.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Battery Voltage, V

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 25V

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS

= 5V, TA = -40°C to +100°C, unless otherwise specified.

MIN

(Note 4) TYP

MAX

(Note 4) UNITS

INPUT POWER SUPPLY

+5V Supply Current I

VDD

VR_ON = 3.3V 5.1 5.7 mA

VR_ON = 0V 1 µA

+3.3V Supply Current I

Battery Supply Current at VIN pin I

3V3

VIN

POR (Power-On Reset) Threshold POR

POR

No load on CLK_EN# 1 µA

VR_ON = 0V, VIN = 25V 1 µA

VDD Rising 4.35 4.5 V

VDD Falling 4.0 4.15 V

SYSTEM AND REFERENCES

System Accuracy ( ISL6266AHRZ) %Error

CC_CORE

No load, closed loop, active mode,

)

TA = 0°C to +100°C, VID = 0.75V to 1.5V -0.5 0.5 %

VID = 0.5V to 0.7375V -8 8 mV

VID = 0.3V to 0.4875V -15 15 mV

System Accuracy (ISL6266AIRZ) %Error

cc_core

No load, closed loop, active mode,

)

VID = 0.75V to 1.5V -0.8 0.8 %

VID = 0.5V to 0.7375V -10 10 mV

VID = 0.3V to 0.4875V -18 18 mV

RBIAS Voltage R

Boot Voltage V

Output Voltage Range V

RBIAS

BOOT

CC_CORE

(max)

CC_CORE

(min)

= 147k 1.45 1.47 1.49 V

RBIAS

1.188 1.2 1.212 V

VID = [0000000] 1.5 V

VID = [1100000] 0.3 V

VID Off State VID = [1111111] 0 V

FN6398.4

August 25, 2015

ISL6266, ISL6266A

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS

= 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued)

MIN

(Note 4) TYP

MAX

(Note 4) UNITS

CHANNEL FREQUENCY

Nominal Channel Frequency f

ISL6266, 2 channel operation 410 440 470 kHz

ISL6266A, 2 channel operation 280 300 320 kHz

Adjustment Range 100 600 kHz

AMPLIFIERS

Droop Amplifier Offset -0.25 0.25 mV

Error Amp DC Gain A

Error Amp Gain-Bandwidth Product GBW C

Error Amp Slew Rate SR C

FB Input Current I

IN(FB)

(Note 3) 90 dB

= 20pF (Note 3) 18 MHz

= 20pF (Note 3) 5 V/µs

10 150 nA

ISEN

Imbalance Voltage 2mV

Input Bias Current 20 nA

SOFT-START CURRENT

Soft-Start Current I

Soft Geyserville Current I

Soft Deeper Sleep Entry Current I

Soft Deeper Sleep Exit Current I

C4EA

C4EB

|SOFT - REF| > 100mV ±180 ±205 ±230 µA

DPRSLPVR = 3.3V -47 -42 -37 µA

DPRSLPVR = 3.3V 37 42 47 µA

DPRSLPVR = 0V 180 205 230 µA

-47 -42 -37 µA

GATE DRIVER DRIVING CAPABILITY

UGATE Source Resistance R

UGATE Source Current I

UGATE Sink Resistance R

UGATE Sink Current I

LGATE Source Resistance R

LGATE Source Current I

LGATE Sink Resistance R

LGATE Sink Current I

UGATE to PHASE Resistance R

SRC(UGATE)

SRC(UGATE)VUGATE_PHASE

SNK(UGATE)

SNK(UGATE)VUGATE_PHASE

SRC(LGATE)

SNK(LGATE)

p(UGATE)

500mA Source Current (Note 3) 1 1.5 

= 2.5V (Note 3) 2 A

500mA Sink Current (Note 3) 1 1.5 

= 2.5V (Note 3) 2 A

500mA Source Current (Note 3) 1 1.5 

= 2.5V (Note 3) 2 A

LGATE

500mA Sink Current (Note 3) 0.5 0.9 

= 2.5V (Note 3) 4 A

LGATE

1k

GATE DRIVER SWITCHING TIMING (refer to “ISL6266, ISL6266A Gate Driver Timing Diagram” on page 6)

UGATE Rise Time t

LGATE Rise Time t

UGATE Fall Time t

LGATE Fall Time t

UGATE Turn-on Propagation Delay t

ISL6266AHRZ

PDHU

PVCC= 5V, 3nF Load (Note 3) 8.0 ns

PVCC= 5V, 3nF Load 4.0 ns

= -10°C to +100°C

= 5V, Outputs Unloaded

= 5V, Outputs Unloaded 18 30 44 ns

20 30 44 ns

ISL6266AIRZ

FN6398.4

August 25, 2015

ISL6266, ISL6266A

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS

LGATE Turn-on Propagation Delay t

= 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued)

= -10°C to +100°C

PDHL

ISL6266AHRZ

PDHL

= 5V, Outputs Unloaded

= 5V, Outputs Unloaded 5 15 30 ns

MIN

(Note 4) TYP

MAX

(Note 4) UNITS

71530ns

ISL6266AIRZ

BOOTSTRAP DIODE

Forward Voltage V

Leakage V

= 5V, Forward Bias Current = 2mA 0.43 0.58 0.72 V

DDP

= 16V 1 µA

POWER GOOD and PROTECTION MONITOR

PGOOD Low Voltage V

PGOOD Leakage Current I

PGOOD Delay t

Overvoltage Threshold O

Severe Overvoltage Threshold O

pgd

VHS

OCSET Reference Current I(R

= 4mA 0.26 0.4 V

PGOOD

= 3.3V -1 1 µA

GOOD

CLK_EN# Low to PGOOD High 6.3 7.6 8.9 ms

VO rising above setpoint >1ms 155 195 235 mV

VO rising above setpoint >0.5µs 1.675 1.7 1.725 V

) = 10µA 9.8 10 10.2 µA

BIAS

OC Threshold Offset DROOP rising above OCSET >120µs -3.5 3.5 mV

Current Imbalance Threshold Difference between ISEN1 and ISEN2 >1ms 9 mV

Undervoltage Threshold

VO falling below setpoint for >1ms -360 -300 -240 mV

(VDIFF-SOFT)

LOGIC INPUTS

VR_ON, DPRSLPVR Input Low V

VR_ON, DPRSLPVR Input High V

Leakage Current of VR_ON I

Leakage Current of DPRSLPVR I

IL_DPRSLP(3.3V)

IH_DPRSLP(3.3V)

DAC(VID0-VID6), PSI# and

IL(3.3V)

IH(3.3V)

IL(3.3V)

IH(3.3V)

IL(1V)

2.3 V

Logic input is low -1 0 µA

Logic input is high at 3.3V 0 1 µA

DPRSLPVR input is low -1 0 µA

DPRSLPVR input is high at 3.3V 0.45 1 µA

0.3 V

DPRSTP# Input Low

DAC(VID0-VID6), PSI# and DPRSTP# Input High

Leakage Current of DAC (VID0-VID6), PSI# and DPRSTP#

IH(1V)

IL(1V)

IH(1V)

Logic input is low -1 0 µA

Logic input is high at 1V 0.45 1 µA

0.7 V

THERMAL MONITOR

NTC Source Current NTC = 1.3V 53 60 67 µA

Over-Temperature Threshold V(NTC) falling 1.18 1.2 1.22 V

VR_TT# Low Output Resistance R

I = 20mA 6.5 9 

POWER MONITOR

PMON Output Voltage Range V

PMON Maximum Voltage V

pmon

pmonmax

VSEN = 1.2V, Droop - VO= 80mV 1.638 1.680 1.722 V

VSEN = 1V, Droop - V

= 20mV 0.308 0.350 0.392 V

2.8 3.0 V

FN6398.4

August 25, 2015

PWM

UGATE

LGATE

PDHL

PDHU

ISL6266, ISL6266A

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS

PMON Sourcing Current I

PMON Sinking Current I

Maximum Current Sinking Capability Refer to Figure 29 PMON/

PMON Impedance When PMON is within its sourcing/sinking

= 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued)

sc_pmon

sk_pmon

VSEN = 1V, Droop - VO= 50mV 2 mA

MIN

(Note 4) TYP

PMON/

250

180

7 

MAX

(Note 4) UNITS

PMON/

100

current range (Note 3)

CLK_EN# OUTPUT LEVELS

CLK_EN# High Output Voltage V

CLK_EN# Low Output Voltage V

3V3 = 3.3V, I = -4mA 2.9 3.1 V

EN# = 4mA 0.26 0.4 V

CLK_

NOTES:

3. Limits established by characterization and are not production tested.

4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.

ISL6266, ISL6266A Gate Driver Timing Diagram

FN6398.4

August 25, 2015

Functional Pin Description

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0

VDIFF

VSEN

RTN

DROOP

DFB

VSUM

VIN

GND

VDD

ISEN2

ISEN1

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

PGOOD

PSI#

PMON

RBIAS

VR_TT#

NTC

SOFT

OCSET

COMP

FB2

GND PAD

(BOTTOM)

ISL6266, ISL6266A

FN6398.4

August 25, 2015

ISL6266, ISL6266A

PGOOD - Power good open-drain output. Connect externally with 680 to VCCP or 1.9k to 3.3V.

PSI# - Current indicator input. When asserted low, indicates a reduced load-current condition and initiates single-phase operation.

PMON - Analog output. PMON is proportional to the product of Vsen and droop voltage.

RBIAS - 147k resistor to VSS sets internal current reference.

VR_TT# - Thermal overload output indicator with open-drain output. Over-temperature pull-down resistance is 10.

NTC - Thermistor input to VRTT# circuit and a 60µA current source is connected internally to this pin.

SOFT - A capacitor from this pin to GND sets the maximum slew rate of the output voltage. SOFT is the non-inverting input of the error amplifier.

OCSET - Overcurrent set input. A resistor from this pin to VO sets DROOP voltage limit for OC trip. A 10µA current source is connected internally to this pin.

VW - A resistor from this pin to COMP programs the switching frequency (for example, 6.45k 400kHz).

COMP - This pin is the output of the error amplifier.

N/C - Not connected. Grounding this pin to signal ground in

the practical layout.

BOOT2 - This pin is the upper gate driver supply voltage for Phase 2. An internal boot strap diode is connected to the PVCC pin.

UGATE2 - Upper MOSFET gate signal for Phase 2.

PHASE2 - The phase node of Phase 2. Connect this pin to

the source of the Channel 2 upper MOSFET.

PGND2 - The return path of the lower gate driver for Phase 2.

LGATE2 - Lower-side MOSFET gate signal for Phase 2.

PVCC - 5V power supply for gate drivers.

LGATE1 - Lower-side MOSFET gate signal for Phase 1.

PGND1 - The return path of the lower gate driver for

Phase 1.

PHASE1 - The phase node of phase 1. Connect this pin to the source of the Channel 1 upper MOSFET.

UGATE1 - Upper MOSFET gate signal for Phase 1.

BOOT1 - This pin is the upper-gate-driver supply voltage for

Phase 1. An internal boot strap diode is connected to the PVCC pin.

FB - This pin is the inverting input of error amplifier.

FB2 - There is a switch between FB2 pin and the FB pin.

The switch is closed in single-phase operation and is opened in two phase operation. The components connecting to FB2 are to adjust the compensation in single phase operation to achieve optimum performance.

VDIFF - This pin is the output of the differential amplifier.

VSEN - Remote core voltage sense input.

RTN - Remote core voltage sense return.

DROOP - Output of the droop amplifier. The voltage level on

this pin is the sum of V

and the droop voltage.

DFB - Inverting input to droop amplifier.

VO - An input to the IC that reports the local output voltage.

VSUM - This pin is connected to the summation junction of

channel current sensing.

VIN - Battery supply voltage. It is used for input voltage feed forward to improve input line transient performance.

VSS - Signal ground. Connect to local controller ground.

VDD - 5V control power supply.

VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with

VID0 is the least significant bit (LSB) and VID6 is the most significant bit (MSB).

VR_ON - Digital enable input. A logic high signal on this pin enables the regulator.

DPRSLPVR - Deeper sleep enable signal. A logic high signal on this pin indicates the micro-processor is in deeper-sleep mode and also indicates a slow C4 entry or exit rate with 41µA discharging or charging the SOFT capacitor.

DPRSTP# - Deeper sleep slow wake up signal. A logic low signal on this pin indicates the micro-processor is in deeper-sleep mode.

CLK_EN# - Digital output for system clock. Goes active 10µs after V

is within 10% of Boot voltage.

CORE

3V3 - 3.3V supply voltage for CLK_EN#.

ISEN2 - Individual current sharing sensing for Channel 2.

ISEN1 - Individual current sharing sensing for Channel 1.

FN6398.4

August 25, 2015

Functional Block Diagram

1 +

DAC

GND

COMP

VID0

VID1

VID2

VID3

VID4

SOFT

MODE

CONTROL

SOFT

VR_ON

VIN

VID5

E/A

PGOOD

MONITOR

AND LOGIC

RTN

MODULATOR

VIN

VSOFT

VIN

PHASE

CONTROL

LOGIC

PSI#

DPRSLPVR

CURRENT BALANCE

PHASE

SEQUENCER

ISEN1

VIN

FLT

RBIAS

VDD

ISEN2

VSUM

DFB

DROOP

VDIFF

VSEN

I_BALF

DACOUT

CLK_EN#

OCSET

NTC

VR_TT#

54µA

1 +

VIN

VSOFT

1.24V

DROOP

VID6

10µA

PHASE1

DRIVER

LOGIC

PVCC

LGATE1

UGATE1

BOOT1

PGND1

PHASE2

DRIVER

LOGIC

PVCC

LGATE2

UGATE2

BOOT2

PGND2

FLT

PVCC

VSOFT

DPRSTP#

SINGLE

PHASE

FB2

3V3

PVCC

ULTRASONIC

TIMER

MODE CHANGE

REQUEST

0.5

SINGLE PHASE

CH1 CH2

CH1

CH2

GOOD

FLT

FAULT AND

PGOOD

LOGIC

6µA

1.2V

FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6266, ISL6266A

SINGLE PHASE

PMON

MULTIPLIER

ISL6266, ISL6266A

FN6398.4

August 25, 2015

Typical Performance Curves

100

0 5 10 15 20 25 30 35 40 45 50

OUT

(A)

EFFICIENCY (%)

VIN = 12.6V

VIN = 19.0V

VIN = 8.0V

1.04

1.06

1.08

1.10

1.12

1.14

1.16

0 1020304050

OUT

(A)

OUT

(V)

VIN = 19.0V

VIN = 8.0V

VIN = 12.6V

100

0 5 10 15 20 25

OUT

(A)

EFFICIENCY (%)

VIN = 8.0V

VIN = 12.6V

VIN = 19.0V

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

0 5 10 15 20 25

OUT

(A)

OUT

(V)

VIN = 12.6V

VIN = 19.0V

VIN = 8.0V

100

0.1 1.0 10.0 I

OUT

(A)

EFFICIENCY (%)

VIN = 12.6V

VIN = 19.0V

VIN = 8.0V

0.757

0.758

0.759

0.760

0.761

0.762

0.763

0.764

0.765

0123

OUT

(A)

OUT

(V)

VIN = 19.0V

VIN = 12.6V

VIN = 8.0V

ISL6266, ISL6266A

FIGURE 2. ACTIVE MODE EFFICIENCY, 2-PHASE, CCM,

PSI# = HIGH, VID = 1.15V

FIGURE 4. ACTIVE MODE EFFICIENCY, 1-PHASE, CCM,

PSI# = LOW, VID = 1.00V (ISL6266 ONLY)

FIGURE 3. ACTIVE MODE LOAD LINE, 2-PHASE, CCM,

PSI# = HIGH, VID = 1.15V

FIGURE 5. ACTIVE MODE LOAD LINE, 1-PHASE, CCM,

PSI# = LOW, VID = 1.00V (ISL6266 ONLY)

FIGURE 6. DEEPER SLEEP MODE EFFICIENCY FIGURE 7. DEEPER SLEEP MODE LOAD LINE

FN6398.4

August 25, 2015

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