intersil ISL6265 DATA SHEET

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Data Sheet May 13, 2009

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ISL6265

FN6599.1

Multi-Output Controller with Integrated
MOSFET Drivers for AMD SVI Capable
Mobile CPUs

The ISL6265 is a multi-output controller with embedded gate
drivers. A single-phase controller powers the Northbridge
(VDDNB) portion of the CPU. The two remaining controller
channels can be configured for two-phase or individual
single-phase outputs. For uniplane CPU applications, the
ISL6265 is configured as a two-phase buck converter. This
allows the controller to interleave channels to effectively
double the output voltage ripple frequency and thereby
reduce output voltage ripple amplitude with fewer
components, lower component cost, reduced power
dissipation, and smaller area. For dual-plane processors, the
ISL6265 can be configured as independent single-phase
controllers powering VDD0 and VDD1.

The heart of the ISL6265 is the patented R
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional buck regulator, the R

3

faster transient response. This is due to the R
commanding variable switching frequency during a load
transient.

The Serial VID Interface (SVI) allows dynamic adjustment of
the Core and Northbridge output voltages independently and
in combination from 0.500V to 1.55V. Core and Northbridge
output voltages achieve a 0.5% system accuracy
over-temperature.

3

Technology™,

Technology™ has a

3

modulator

Features

• Core Configuration Flexibility

- Dual Plane, Single-Phase Controllers

- Uniplane, Two-Phase Controller

• Precision Voltage Regulators

- 0.5% System Accuracy Over-temperature

• Voltage Positioning with Adjustable Load Line and Offset

• Internal Gate Drivers with 2A Driving Capability

• Differential Remote CPU Die Voltage Sensing

• Core Differential Current Sensing: DCR or Resistor

• Northbridge Lossless r

• Serial VID Interface

- Two Wire Clock and Data Bus

- Supports High-Speed I

- 0.500V to 1.55V in 12.5mV Steps

- Supports PSI_L Power-Saving Mode

• Core Outputs Feature Phase Shedding with PSI_L

• Adjustable Output-Voltage Offset

• Digital Soft-Start of all Outputs

• User Programmable Switching Frequency

• Static and Dynamic Current Sharing (Uniplane Core)

• Overvoltage, Undervoltage, and Overcurrent Protection

• Pb-Free (RoHS Compliant)

Current Sensing

DS(ON)

2

C

A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately regulated per AMD mobile CPU specifications.
Core output current sensing is realized using lossless
inductor DCR sensing. All outputs feature overcurrent,
overvoltage and undervoltage protection.

Ordering Information

PART NUMBER

(Note)

ISL6265HRTZ ISL6265 HRTZ -10 to +100 48 Ld 6x6 TQFN L48 .6x6
ISL6265HRTZ-T* ISL6265 HRTZ -10 to +100 48 Ld 6x6 TQFN

* Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special

Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PART

MARKING TEMP (°C)

1

PACKAGE

(Pb-Free)

Tape and Reel

PKG.

DWG. #

L48.6x6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Pinout

OFS/VFIXEN

PGOOD
PWROK

SVD
SVC

ENABLE

RBIAS

OCSET

VDIFF_0

FB_0

COMP_0

VW0

ISL6265 (48 LD 6X6 TQFN)

TOP VIEW

PHASE_NB

VCC

FB_NB

COMP_NB

VSEN_NB

VIN

48

47 46 45 44 43 42 41 40 39

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22

ISP0

ISN0

RTN0

VSEN0

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

RTN_NB

FSET_NB

RTN1

49

GND

VSEN1

VDIFF_1

OCSET_NB

FB_1

PGND_NB

COMP_1

LGATE_NB

VW1

38 37

23 24

ISP_1

UGATE_NB

BOOT_NB

36

BOOT_0

35

UGATE_0

34

PHASE_0

33

PGND_0

32

LGATE_0

31

PVCC

30

LGATE_1

29

PGND_1

28

PHASE_1

27

UGATE_1

26

BOOT_1

25

ISN_1

Function Block Diagram

ISL6265

SVC

SVD

PWROK

OFS/FIXEN

OCSET_NB

OCSET

RBIAS

VW0

COMP0

FB0

VDIFF0

VSEN0

RTN0

ISP0
ISN0

ISP1

ISN1

VSEN1

RTN1

VDIFF1

RTN_NB

SVI

INTERFACE

AND DAC

1

CURRENT

SENSE

CURRENT

SENSE

1

VSEN_NB

NO DROOP
PSI_L
I_OFS
VREF_NB

VREF0
VREF1

I_OFS

V0

NO

DROOP

MODE

V1

VNB

1

1.5kΩ

FAULT

PROTECTION

∑

ISEN0

ISEN1

NO
DROOP

∑

I_OFS

FB_NB

1.5kW

VREF_NB

VREF0

VREF1

3.0kΩ

E/A

FLT
VNB
V0
V1
ISEN0
ISEN1

E/A

VIN

MODE

CURRENT
BALANCE

MODE

E/A

COMP_NB

RTN1

FSET_NB

I

FSET_NB

MODULATOR

NB

VIN

POWER-ON
RESET AND

SOFT-START

LOGIC

MODE

I

VW0

MODULATOR

CORE

I

VW1

FLT

PROTECTION

PSI_L

FLT

PSI_L

FLT

PSI_L

PVCC

MOSFET
DRIVER

SHOOT-THRU

DE MODE

PVCC

MOSFET
DRIVER

SHOOT-THRU

PROTECTION

DE MODE

PVCC

MOSFET
DRIVER

SHOOT-THRU

PROTECTION

DE MODE

BOOT_NB

UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

PVCC

VCC

ENABLE

PGOOD

GND

VIN

BOOT0

UGATE0

PHASE0

LGATE0

PGND0

BOOT1

UGATE1

PHASE1

LGATE1

PGND1

FB1

COMP1

VW1

FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6265

2

FN6599.1

May 13, 2009

ISL6265

Simplified Application Circuit for Dual Plane and Northbridge Support

SVI DATA

SVI CLOCK

ENABLE

PWROK

VDDPWRGD

REMOTE

SENSE

REMOTE

SENSE

VDD_PLANE_STRAP

+5V

VCC

SVD
SVC
EN
PWROK
PGOOD

VSEN0
RTN0

VSEN1
RTN1

OFS/VFIXEN

PVCC

VIN

VIN

GND

UGATE0

BOOT0

PHASE0

LGATE0

PGND0

OCSET

ISP0

ISN0

RBIAS

+VIN

C

IN

L

OUT

VDD0

CORE
LOAD

VDIFF0

FB0

COMP0

VW0

VDIFF1

FB1

COMP1

VW1

FSET_NB

COMP_NB

FB_NB

ISL6265

UGATE1

BOOT1

PHASE1

LGATE1

PGND1

ISP1

ISN1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

OCSET_NB

VSEN_NB

RTN_NB

+VIN

+VIN

C

IN

L

OUT

C

IN

L

OUT

VDD1

VDDNB

NB

LOAD

CORE
LOAD

FIGURE 2. ISL6265 BASED DUAL-PLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING

3

May 13, 2009

FN6599.1

ISL6265

Simplified Application Circuit for Uniplane Core and Northbridge Support

+5V

SVI DATA

SVI CLOCK

ENABLE

PWROK

VDDPWRGD

REMOTE

SENSE

REMOTE

SENSE

VDD_PLANE_STRAP

VCC

SVD
SVC
EN
PWROK
PGOOD

VSEN0
RTN0

VSEN1
RTN1

OFS/VFIXEN

VDIFF0

FB0

COMP0

PVCC

ISL6265

VIN

GND

UGATE0

BOOT0

PHASE0

LGATE0

PGND0

RBIAS

OCSET

UGATE1

BOOT1

PHASE1

ISP0

ISN0

+VIN

+VIN

C

IN

L

OUT

CORE
LOAD

VDD0

C

IN

L

OUT

LGATE1

VDDNB

NB

LOAD

CORE
LOAD

OPEN

OPEN

OPEN

OPEN

VW0

VDIFF1

FB1

COMP1

VW1

FSET_NB

COMP_NB

FB_NB

PGND1

ISP1

ISN1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

OCSET_NB

VSEN_NB

RTN_NB

+VIN

C

IN

L

OUT

FIGURE 3. ISL6265 BASED UNIPLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING

4

FN6599.1

May 13, 2009

ISL6265

Simplified Application Circuit for Dual Layout

+5V

SVI DATA

SVI CLOCK

ENABLE

PWROK

VDDPWRGD

REMOTE

SENSE

VDD_PLANE_STRAP

REMOTE

SENSE

DNP DUAL PLANE

DNP UNIPLANE

VCC

SVD
SVC
EN
PWROK
PGOOD

VSEN0
RTN0

RTN1

VSEN1

OFS/VFIXEN

VDIFF0

FB0

COMP0

PVCC

ISL6265

VIN

GND

UGATE0

BOOT0

PHASE0

LGATE0

PGND0

RBIAS

OCSET

UGATE1

BOOT1

PHASE1

ISP0

ISN0

+VIN

+VIN

C

IN

L

OUT

VDD0

CORE
LOAD

UNIPLANE

VDD0

C

IN

L

OUT

DNP
DUAL
PLANE

LGATE1

VDDNB

NB

LOAD

CORE
LOAD

POPULATION OPTIONAL IN UNIPLANE

VW0

VDIFF1

FB1

COMP1

VW1

FSET_NB

COMP_NB

FB_NB

PGND1

ISP1

ISN1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

OCSET_NB

VSEN_NB

RTN_NB

+VIN

C

IN

L

OUT

FIGURE 4. ISL6265 BASED UNIPLANE OR DUAL PLANE CORE CONVERTER WITH IN DUCTOR DCR CURRENT SENSING

VDD1

5

FN6599.1

May 13, 2009

ISL6265

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . .-0.3 - +7V

Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE). . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (<10ns)

Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . PHASE -0.3V (DC) to BOOT

LGATE Voltage (LGATE) . . . . . . . . . . . . . -0.3V (DC) to VCC + 0.3V

ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)

Open Drain Outputs, PGOOD . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

1. θ

JA

Brief TB379.

2. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical, Notes 1, 2) θ

(°C/W) θJC (°C/W)

JA

TQFN Package . . . . . . . . . . . . . . . . . . 30 1.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Supply Voltage, VCC, PVCC. . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to 24V

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

Electrical Specifications VCC = PVCC = 5V , V

= 12V, TA = -10°C to +100°C; Parameters with MIN and/or MAX limits are 100% tested

IN

at +25°C, unless otherwise specified. T emperature limits est ablished by characterization and are not production
tested.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT POWER SUPPLY

+5V Supply Current I

VCC

EN = 3.3V - 7.8 10 mA
EN = 0V - - 1 µA

POR (Power-On Reset) Threshold VCC POR

VCC POR

Battery Supply Current (VIN) I

VIN

Rising - 4.35 4.5 V

rVCC

Falling 3.9 4.1 - V

fVCC

EN = 0V, VIN = 24V - - 1 µA

SYSTEM AND REFERENCES

System Accuracy
(V

core0, Vcore1, Vcore_NB

)

RBIAS Voltage R
Maximum Output Voltage (Note 3) V

Minimum Output Voltage (Note 3) V

%Error

(V

CORE

RBIAS

COREx

(max)

COREx

(min)

No load, closed loop, active mode VID = 0.75V to 1.55V -0.5 - 0.5 %

)

VID = 0.50V to 0.7375V -5 - +5 mV
R

= 117kΩ 1.15 1.17 1.19 V

RBIAS

SVID = [000_0000b] - 1.55 - V

SVID = [101_0100b] - 0.500 - V

CHANNEL FREQUENCY

Nominal CORE Switching Frequency f

Nominal NB Switching Frequency f

SW_core0

SW_core_NBRFSET_NB

VIN = 15.5V, V
force V

comp_0

= 22.1kΩ, C

V

= 0.51V

sen_nb

= 1.55V, V

DAC

=2V, R

= 1.60V,

FB0

= 6.81kΩ, 2-Phase Operation

VW

FSET_NB

= 1nF, V

DAC

= 0.5V,

285 300 315 kHz

285 300 315 kHz

Core Frequency Adjustment Range 200 - 500 kHz
NB Frequency Adjustment Range 200 - 500 kHz

AMPLIFIERS (Note 3)

Error Amp DC Gain A

V0

Error Amp Gain-Bandwidth Product GBW C
Error Amp Slew Rate SR C

= 20pF - 18 - MHz

L

= 20pF - 5.0 - V/µs

L

-90-dB

6

FN6599.1

May 13, 2009

ISL6265

Electrical Specifications VCC = PVCC = 5V , V

at +25°C, unless otherwise specified. T emperature limits est ablished by characterization and are not production

= 12V, TA = -10°C to +100°C; Parameters with MIN and/or MAX limits are 100% tested

IN

tested. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CORE CURRENT SENSE (Note 3)

Current Imbalance Threshold Di -4-mV
Input Bias Current -20-nA
RTN1 Threshold -0.8- V

SOFT START/VID-ON-THE-FLY

Soft-Start Voltage Transition V

SS

1.25 1.875 2.50 mV/µs

VID on the Fly Transition 5 7.5 10 mV/µs

GATE DRIVER DRIVING CAPABILITY [CORE AND NB]

UGATE Source Resistance (Note 4) R
UGATE Source Current (Note 4) I
UGATE Sink Resistance (Note 4) R
UGATE Sink Current (Note 4) I
LGATE Source Resistance (Note 4) R
LGATE Source Current (Note 4) I
LGATE Sink Resistance (Note 4) R
LGATE Sink Current (Note 4) I
UGATE to PHASE Resistance (Note 3) R

SRC(UGATE)

SRC(UGATE)VUGATE_PHASE

SNK(UGATE)

SNK(UGATE)VUGATE_PHASE

SRC(LGATE)

SRC(LGATE)VLGATE

SNK(LGATE)

SNK(LGATE)VLGATE

p(UGATE)

500mA Source Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Sink Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Source Current - 1 1.5 Ω

= 2.5V - 2 - A

500mA Sink Current - 0.5 0.9 Ω

= 2.5V - 4 - A

-1-kΩ

GATE DRIVER SWITCHING TIMING (Note 3) (Refer to “ISL6265 Gate Driver Timing Diagram” on page 8)

UGATE Rise Time t
LGATE Rise Time t
UGATE Fall Time t
LGATE Fall Time t
UGATE Turn-on Propagation Delay t
LGATE Turn-on Propagation Delay t

RU

RL

FU

FL

PDHU

PDHL

PVCC = 5V, 3nF Load - 8.0 - ns
PVCC = 5V, 3nF Load - 8.0 - ns
PVCC = 5V, 3nF Load - 8.0 - ns
PVCC = 5V, 3nF Load - 4.0 - ns
PVCC = 5V, Outputs Unloaded - 36 - ns
PVCC = 5V, Outputs Unloaded - 20 - ns

BOOTSTRAP DIODE

Forward Voltage V
Leakage V

= 5V, Forward Bias Current = 2mA 0.43 0.58 0.67 V

DDP

= 16V - - 1 µA

R

POWER GOOD AND PROTECTION MONITOR

PGOOD Low Voltage V
PGOOD Leakage Current I

OL

OH

PGOOD High After Soft-Start Enable to PGOOD High, V

I

= 4mA - 0.2 0.5 V

PGOOD

P

= 5V -1 - 1 µA

GOOD

= 1.1V 570 700 1010 µs

COREx

PGOOD Low After Fault Fault to PGOOD Low 160 208 250 µs
Undervoltage Threshold U
Overvoltage Threshold O

VH

VHS

V

falls below set-point for 208μs 240 295 350 mV

COREx

VO rising above threshold > 0.5µs 1.770 1.795 1.820 V

OVERCURRENT PROTECTION VDD0 AND VDD1

OCSET Reference Voltage
(V

- V

ISNx

)

ISPx

= 180mV; VIN = 15.5V 5 6.0 7 mV

V

OCSET

OVERCURRENT PROTECTION VDD_NB

OCSET_NB OCP Current RBIAS pin to GND = 117kΩ; Trips after 8 PWM cycles 9.2 10 10.8 µA

7

FN6599.1

May 13, 2009

ISL6265

Electrical Specifications VCC = PVCC = 5V , V

at +25°C, unless otherwise specified. T emperature limits est ablished by characterization and are not production

= 12V, TA = -10°C to +100°C; Parameters with MIN and/or MAX limits are 100% tested

IN

tested. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFFSET FUNCTION

OFS Pin Voltage For Droop Enabling V
FB Pin Source Current I
OFS Pin Voltage Threshold for VFIX

Mode and No Droop Operation (Note 3)
OFS Pin Voltage Threshold for SVI Mode

and No Droop Operation (Note 3)
OFS Bias (Note 3) I

V

V

OFS

FB

OFS

OFS

OFS

R

= 240kΩ (OFS pin to GND) 1.18 1.2 1.22 V

OFS

I

= 10µA 9.0 9.9 10.8 µA

OFS

-1.8- V

-4.0- V

1.8V < OFS < VCC - 4.0 - µA

LOGIC INPUTS

ENABLE Low Threshold V
ENABLE High Threshold V

IL(3.3V)

IH(3.3V)

- 1.35 0.9 V

2.0 1.6 - V

ENABLE Leakage Current Logic input is low -1 0 - µA

Logic input is high at 3.3V - 0 1 µA

SVI INTERFACE

PWROK Input Low Threshold - 0.65 0.8 V
PWROK Input High Threshold (Note 3) -0.9- V
SVC, SVD Input HIGH (VIH) 1.05 0.87 - V
SVC, SVD Input LOW (VIL) - 0.68 0.45 V
Schmitt Trigger Input Hysteresis (Note 3) -0.19- V
SVD Low Level Output Voltage 3mA Sink Current - 0.1 0.285 V
SVC, SVD Leakage (Note 3) EN = 0V, SVC, SVD = 0V - < -100 - nA

EN = 5V, SVC, SVD = 1.8V - < -100 - nA

DIFF AMP

Accuracy VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V -2 - 2 mV

NOTES:

3. Limits should be considered typical and are not production tested.

4. Limits established by characterization and are not production tested.

ISL6265 Gate Driver Timing Diagram

PWM

t

PDHU

t

RU

UGATE

LGATE

1V

t

FL

8

1V

t

PDHL

t

FU

t

RL

FN6599.1

May 13, 2009