Intersil ISL6255AHAZ, ISL6255AHRZ, ISL6255HAZ, ISL6255HRZ Schematics

®

ISL6255, ISL6255A

Data Sheet May 23, 2006

Highly Integrated Battery Charger with Automatic Power Source Selector for Notebook Computers

The ISL6255, ISL6255A is a highly integrated battery charger controller for Li-Ion/Li-Ion polymer batteries. High Effici ency is achieved by a synchronous buck topology and the use of a MOSFET, instead of a diode, for selecting power from the adapter or battery . The low side MOSFET emulates a diode at light loads to improve the light load efficiency and prevent system bus boosting.

The constant output voltage can be selected for 2, 3 and 4 series Li-Ion cells with 0.5% accuracy over temperature. It can also be programmed between 4.2V+5%/cell and 4.2V -5% /cell to optimize battery capacity. When supplying the load and battery charger simultaneously, the input current limit for the AC adapter is programmable to within 3% accuracy to avoid overloading the AC adapter, and to allow the system to ma ke efficient use of available adapter power for charging. It also has a wide range of programmable charging current. The ISL6255, ISL6255A provides outputs that are used to monitor the current drawn from the AC adapter , and monito r for th e presence of an AC adapter. The ISL6255, ISL6255A automatically transitions from regulating current mode to regulating voltage mode.

ISL6255, ISL6255A has a feature for automatic power source selection by switching to the battery when the AC adapter is removed or switching to the AC adapter when the AC adapter is available. It also provides a DC adapter monitor to support aircraft power applications with the option of no battery charging.

Ordering Information

PART

NUMBER

(Notes 1, 2)

ISL6255HRZ ISL6255HRZ -10 to 100 28 Ld 5x5 QFN L28.5×5 ISL6255HAZ ISL6255HAZ -10 to 100 28 Ld QSOP M28.15 ISL6255AHRZ ISL6255AHRZ -10 to 100 28 Ld 5x5 QFN L28.5×5 ISL6255AHAZ ISL6255AHAZ -10 to 100 28 Ld QSOP M28.15

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-0 20.

2. Add “-T” for Tape and Reel.

PART

MARKING

TEMP

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

FN9203.2

Features

• ±0.5% Charge Voltage Accuracy (-10°C to 100°C)

• ±3% Accurate Input Current Limit

• ±3% Accurate Battery Charge Current Limit

• ±25% Accurate Battery Trickle Charge Current Limit (ISL6255A)

• Programmable Charge Current Limit, Adapter Current Limit and Charge Voltage

• Fixed 300kHz PWM Synchronous Buck Controller with Diode Emulation at Light Load

• Output for Current Drawn from AC Adapter

• AC Adapter Present Indicator

• Fast Input Current Limit Response

• Input Voltage Range 7V to 25V

• Support 2, 3 and 4 Cells Battery Pack

• Up to 17.64V Battery-Voltage Set Point

• Control Adapter Power Source Select MOSFET

• Thermal Shutdown

• Aircraft Power Capable

• DC Adapter Present Indicator

• Battery Discharge MOSFET Control

• Less than 10µA Battery Leakage Current

• Support Pulse Charging

• Charge Any Battery Chemistry: Li-Ion, NiCd, NiMH, etc.

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Notebook, Desknote and Sub-notebook Computers

• Personal Digital Assistant

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

ISL6255, ISL6255A

(28 LD QFN)

TOP VIEW

ISL6255, ISL6255A

(28 LD QSOP)

TOP VIEW

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

DCSET

ACSET

VDD

DCIN

28 27 26 25 24 23 22

1

2

3

4

5

6

7

8 9 10 11 12 13 14

GND

ACLIM

VADJ

PGND

DCPRN

LGATE

ACPRN

VDDP

CSON

21

20

19

18

17

16

15

BOOT

CSOP

CSIN

CSIP

SGATE

BGATE

PHASE

UGATE

DCIN

VDD

ACSET

DCSET

EN

CELLS

ICOMP

VCOMP

ICM

VREF

CHLIM

ACLIM

VADJ

GND

1 28

2 27

3 26

4 25

5 24

6 23

7 22

8 21

9 20

10 19

11 18

12 17

13 16

14 15

DCPRN

ACPRN

CSON

CSOP

CSIN

CSIP

SGATE

BGATE

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

2

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Absolute Maximum Ratings Thermal Information

DCIN, CSIP, CSON to GND. . . . . . . . . . . . . . . . . . . . .-0.3V to +28V

CSIP-CSIN, CSOP-CSON. . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

CSIP-SGATE, CSIP-BGATE . . . . . . . . . . . . . . . . . . . . .-0.3V to 16V

PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7V to 30V

BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +35V

BOOT to VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 28V

ACLIM, ACPRN, CHLIM, DCPRN, VDD to GND. . . . . . .-0.3V to 7V

BOOT-PHASE, VDDP-PGND . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

ACSET and DCSET to GND (Note 3) . . . . . . . . -0.3V to VDD+0.3V

ICM, ICOMP, VCOMP to GND. . . . . . . . . . . . . . -0.3V to VDD+0.3V

VREF, CELLS to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V

EN, VADJ, PGND to GND . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V

UGATE. . . . . . . . . . . . . . . . . . . . . . . . . PHASE-0.3V to BOOT+0.3V

LGATE. . . . . . . . . . . . . . . . . . . . . . . . . . PGND-0.3V to VDDP+0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. When the voltage across ACSET and DCSET is below 0V, the current through ACSET and DCSET should be limited to less than 1mA.

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

4. θ

JA

Brief TB379.

5. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance θ

(°C/W) θJC (°C/W)

JA

QFN Package (Notes 4, 5). . . . . . . . . . 39 9.5

QSOP Package (Note 4) . . . . . . . . . . . 80 NA

Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +150°C

Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET= DCSET = 1.5V, ACLIM = VREF,

VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, C T

= -10°C to +100°C, T

A

≤ 125°C, unless otherwise noted.

J

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SUPPLY AND BIAS REGULATOR

DCIN Input Voltage Range 725V DCIN Quiescent Current EN = VDD or GND, 7V ≤ DCIN ≤ 25V 1.4 3 mA Battery Leakage Current (Note 6) DCIN = 0, no load 3 10 µA VDD Output Voltage/Regulation 7V ≤ DCIN ≤ 25V, 0 ≤ I

≤ 30mA 4.925 5.075 5.225 V

VDD

VDD Undervoltage Lockout Trip Point VDD Rising 4.0 4.4 4.6 V

Hysteresis 200 250 400 mV

Reference Output Voltage VREF 0 ≤ I

≤ 300µA 2.365 2.39 2.415 V

VREF

Battery Charge Voltage Accuracy CSON = 16.8V, CELLS = VDD, VADJ = Float -0.5 0.5 %

CSON = 12.6V, CELLS = GND, VADJ = Float -0.5 0.5 % CSON = 8.4V, CELLS = Float, VADJ = Float -0.5 0.5 % CSON = 17.64V, CELLS = VDD, VADJ = VREF -0.5 0.5 % CSON = 13.23V, CELLS = GND, VADJ = VREF -0.5 0.5 % CSON = 8.82V, CELLS = Float, VADJ = VREF -0.5 0.5 % CSON = 15.96V, CELLS = VDD, VADJ = GND -0.5 0.5 % CSON = 11.97V, CELLS = GND, VADJ = GND -0.5 0.5 % CSON = 7.98V, CELLS = Float, VADJ = GND -0.5 0.5 %

TRIP POINTS

ACSET Threshold 1.24 1.26 1.28 V ACSET Input Bias Current Hysteresis 2.2 3.4 4.4 µA ACSET Input Bias Current ACSET ≥ 1.26V 2.2 3.4 4.4 µA ACSET Input Bias Current ACSET < 1.26V -1 0 1 µA DCSET Threshold 1.24 1.26 1.28 V

VDD

=1µF, I

VDD

=0mA,

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FN9203.2

May 23, 2006

ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET= DCSET = 1.5V, ACLIM = VREF,

VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, C T

= -10°C to +100°C, T

A

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DCSET Input Bias Current Hysteresis 2.2 3.4 4.4 µA DCSET Input Bias Current DCSET ≥ 1.26V 2.2 3.4 4.4 µA DCSET Input Bias Current DCSET < 1.26V -1 0 1 µA

OSCILLATOR

Frequency 245 300 355 kHz PWM Ramp Voltage (peak-peak) CSIP = 18V 1.6 V

CSIP = 11V 1 V

SYNCHRONOUS BUCK REGULATOR

Maximum Duty Cycle 97 99 99.6 % UGATE Pull-Up Resistance BOOT-PHASE = 5V, 500mA source current 1.8 3.0 Ω UGATE Source Current BOOT-PHASE = 5V, BOOT-UGATE = 2.5V 1.0 A UGATE Pull-down Resistance BOOT-PHASE = 5V, 500mA sink current 1.0 1.8 Ω UGATE Sink Current BOOT-PHASE = 5V, UGATE-PHASE = 2.5V 1.8 A LGATE Pull-Up Resistance VDDP-PGND = 5V, 500mA source current 1.8 3.0 Ω LGATE Source Current VDDP-PGND = 5V, VDDP-LGATE = 2.5V 1.0 A LGATE Pull-Down Resistance VDDP-PGND = 5V, 500mA sink current 1.0 1.8 Ω LGATE Sink Current VDDP-PGND = 5V, LGATE = 2.5V 1.8 A

CHARGING CURRENT SENSING AMPLIFIER

Input Common-Mode Range 0 18 V Input Offset Voltage Guaranteed by design -2.5 0 2.5 mV Input Bias Current at CSOP 0 < CSOP < 18V 0.25 2 µA Input Bias Current at CSON 0 < CSON < 18V 75 100 µA CHLIM Input Voltage Range 0 3.6 V CSOP to CSON Full-Scale Current Sense

Voltage

CHLIM Input Bias Current CHLIM = GND or 3.3V, DCIN = 0V -1 1 µA CHLIM Power-Down Mode Threshold

Voltage CHLIM Power-Down Mode Hysteresis

Voltage

ADAPTER CURRENT SENSING AMPLIFIER

Input Common-Mode Range 7 25 V Input Offset Voltage Guaranteed by design -2 2 mV Input Bias Current at CSIP and CSIN

Combined Input Bias Current at CSIN 0 < CSIN < DCIN, Guaranteed by design 0.10 1 µA

ISL6255: CHLIM = 3.3V 157 165 173 mV ISL6255A: CHLIM = 3.3V 160 165 170 mV ISL6255: CHLIM = 2.0V 95 100 105 mV ISL6255A: CHLIM = 2.0V 97 100 103 mV ISL6255: CHLIM = 0.2V 5.0 10 15.0 mV ISL6255A: CHLIM = 0.2V 7.5 10 12.5 mV

CHLIM rising 80 88 95 mV

CSIP = CSIN = 25V 100 130 µA

≤ 125°C, unless otherwise noted. (Continued)

J

15 25 40 mV

VDD

=1µF, I

VDD

=0mA,

4

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET= DCSET = 1.5V, ACLIM = VREF,

VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, C T

= -10°C to +100°C, T

A

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ADAPTER CURRENT LIMIT THRESHOLD

CSIP to CSIN Full-Scale Current Sense Voltage

ACLIM Input Bias Current ACLIM = VREF 10 16 20 µA

VOLTAGE REGULATION ERROR AMPLIFIER

Error Amplifier Transconductance from CSON to VCOMP

CURRENT REGULATION ERROR AMPLIFIER

Charging Current Error Amplifier Transconductance

Adapter Current Error Amplifier Transconductance

BATTERY CELL SELECTOR

CELLS Input Voltage for 4 Cell Select 4.3 V CELLS Input Voltage for 3 Cell Select 2V CELLS Input Voltage for 2 Cell Select 2.1 4.2 V

MOSFET DRIVER

BGATE Pull-Up Current CSIP-BGATE= 3V 10 30 45 mA BGATE Pull-Down Current CSIP-BGATE = 5V 2.7 4.0 5.0 mA CSIP-BGATE Voltage High 89.611V CSIP-BGATE Voltage Low 50 0 50 mV DCIN-CSON Threshold for CSIP-BGATE

Going High DCIN-CSON Threshold Hysteresis 250 300 400 mV SGATE Pull-Up Current CSIP-SGATE= 3V 7 12 15 mA SGATE Pull-Down Current CSIP-SGATE = 5V 50 160 370 µA CSIP-SGATE Voltage High 8911V CSIP-SGATE Voltage Low -50 0 50 mV CSIP-CSIN Threshold for CSIP-SGATE

Going High CSIP-CSIN Threshold Hysteresis 1.3 5 8 mV

LOGIC INTERFACE

EN Input Voltage Range 0VDDV EN Threshold Voltage Rising 1.030 1.06 1.100 V

EN Input Bias Current EN = 2.5V 1.8 2.0 2.2 µA ACPRN Sink Current ACPRN = 0.4V 3 8 11 mA ACPRN Leakage Current ACPRN = 5V -0.5 0.5 µA DCPRN Sink Current DCPRN = 0.4V 3 8 11 mA

ACLIM = VREF 97 100 103 mV ACLIM = Float 72 75 78 mV ACLIM = GND 47 50 53 mV

ACLIM = GND -20 -16 -10 µA

CELLS = VDD 30 µA/V

DCIN = 12V, CSON Rising -100 0 100 mV

Falling 0.985 1.000 1.025 V Hysteresis 30 60 90 mV

≤ 125°C, unless otherwise noted. (Continued)

J

2.5 8 13 mV

=1µF, I

VDD

50 µA/V

VDD

=0mA,

5

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Electrical Specifications DCIN = CSIP = CSIN = 18V, CSOP = CSON = 12V, ACSET= DCSET = 1.5V, ACLIM = VREF,

VADJ=Floating, EN=VDD=5V, BOOT-PHASE=5.0V, GND=PGND=0V, C T

= -10°C to +100°C, T

A

≤ 125°C, unless otherwise noted. (Continued)

J

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DCPRN Leakage Current DCPRN = 5V -0.5 0.5 µA ICM Output Accuracy

(Vicm = 19.9 x (Vcsip-Vcsin))

CSIP-CSIN = 100mV -3 0 +3 % CSIP-CSIN = 75mV -4 0 +4 %

CSIP-CSIN = 50mV -5 0 +5 % Thermal Shutdown Temperature 150 °C Thermal Shutdown Temperature Hysteresis 25 °C

NOTE:

6. This is the sum of currents in these pins (CSIP, CSIN, BGATE, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V . No current in pins EN, ACSET, DCSET, VADJ, CELLS, ACLIM, CHLIM.

VDD

=1µF, I

VDD

=0mA,

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, T

0.6

VDD=5.075V

VDD=5.075V EN=0

0.3

0

-0.3

-0.6

VDD LOAD REGULATION A CCURACY (% )

0 8 16 24 32 40

LOAD CURRENT (mA)

FIGURE 1. VDD LOAD REGULATION

10

9

8

(%)

|

7

6

5

4

3

ICM ACCURACY

|

2

1

0

10 20 30 40 50 60 70 80 90

Test

CSIP-CSIN (mV)

EN=0

100

= 25°C, unless otherwise noted.

A

0.1

VREF=2.390V

0.08

0.06

0.04

0.02

0

VREF LOAD REGULATION A CCURACY (%)

0 100 200 300 400

LOAD CURRENT (µA)

VREF=2.390V

FIGURE 2. VREF LOAD REGULATION

1

0.96

VCSON=12.6V

0.92

0.88

0.84

EFFICIENCY (%)

0.8

0.76

00.511.522.533.54

VCSON=12.6V

(3 CELLS)

VCSON=16.8V

VCSON=16.8V 4 CELLS

4 CELLS

CHARGE CURRENT (A)

VCSON=8.4V

VCSON=8.4V 2 CELLS

2 CELLS

FIGURE 3. ICM ACCURACY vs AC ADAPTER CURRENT FIGURE 4. SYSTEM EFFICIENCY vs CHARGE CURRENT

6

FN9203.2

May 23, 2006

A

ISL6255, ISL6255A

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, T

DCIN

DCIN 10V/div

10V/div

ACSET

ACSET 1V/div

1V/div

DCSET

DCSET 1V/div

1V/div

DCPRN

DCPRN 5V/div

5V/div ACPRN

ACPRN 5V/div

5V/div

FIGURE 5. AC AND DC ADAPTER DETECTION

CSON

CSON 5V/div

5V/div

EN

EN 5V/div

5V/div

INDUCTOR

INDUCTOR CURRENT

CURRENT 2A/div

2A/div

CHARGE

CHARGE CURRENT

CURRENT 2A/div

2A/div

= 25°C, unless otherwise noted. (Continued)

A

LOAD STEP: 0-4A CHARGE CURRENT: 3A

C ADAPTER CURRENT LIMIT: 5.15A

FIGURE 6. LOAD TRANSIENT RESPONSE

BATTERY

BATTERY REMOVAL

REMOVAL

VCOMP

ICOMP

BATTERY

BATTERY INSERTION

INSERTION

LOAD CURRENT 5A/div

DAPTER CURRENT 5A/div

CHARGE CURRENT 2A/div

BATTERY VOLTAGE 2V/div

INDUCTOR

INDUCTOR CURRENT

CURRENT 2A/div

2A/div

CSON

CSON 10V/div

10V/div

VCOMP

VCOMP 2V/div

2V/div

ICOMP

ICOMP 2V/div

2V/div

FIGURE 7. CHARGE ENABLE AND SHUTDOWN FIGURE 8. BATTERY INSERTION AND REMOVAL

CHLIM=0.2V

CHLIM=0.2V CSON=8V

CSON=8V

PHASE

PHASE 10V/div

PHASE

PHASE 10V/div

10V/div

INDUCTOR

INDUCTOR CURRENT

CURRENT

CURRENT 1A/div

1A/div

UGATE

UGATE 5V/div

5V/div

10V/div

UGATE

UGATE 2V/div

2V/div

LGATE

LGATE 2V/div

2V/div

FIGURE 9. AC ADAPTER REMOVAL FIGURE 10. AC ADAPTER INSERTION

7

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Typical Operating Performance DCIN = 20V, 4S2P Li-Battery, T

SGATE-CSIP

SGATE-CSIP 2V/div

2V/div

ADAPTER REMOVAL

FIGURE 11. SWITCHING WA VEFORMS A T DIODE EMULA TION

2V/div

SYSTEM BUS

SYSTEM BUS VOLTAGE

VOLTAGE

VOLTAGE 10V/div

10V/div

BGATE-CSIP

BGATE-CSIP 2V/div

2V/div

INDUCTOR

INDUCTOR CURRENT

CURRENT

CURRENT 2A/div

2A/div

= 25°C, unless otherwise noted. (Continued)

A

BGATE-CSIP

BGATE-CSIP 2V/div

2V/div

SYSTEM BUS

SYSTEM BUS VOLTAGE

VOLTAGE

VOLTAGE 10V/div

10V/div

SGATE-CSIP

SGATE-CSIP 2V/div

2V/div

2V/div INDUCTOR

INDUCTOR

INDUCTOR CURRENT

CURRENT

ADAPTER INSERTION

CURRENT 2A/div

2A/div

FIGURE 12. SWITCHING WAVEFORMS IN CC MODE

CHARGE CURRENT 1A/div

FIGURE 13. TRICKLE TO FULL-SCALE CHARGING

Functional Pin Descriptions

BOOT

Connect BOOT to a 0.1µF ceramic capacitor to PHASE pin and connect to the cathode of the bootstrap schottky diode.

UGATE

UGATE is the high side MOSFET gate drive output.

SGATE

SGATE is the AC adapter power source select output. The SGATE pin drives an external P-MOSFET used to switch to AC adapter as the system power source.

BGATE

Battery power source select output. This pin drives an external P-channel MOSFET used to switch the battery as the system power source. When the voltage at CSON pin is higher than the AC adapter output voltage at DCIN, BGATE is driven to low and selects the battery as the power source.

LGATE

LGATE is the low side MOSFET gate drive output; swing between 0V and VDDP.

CHLIM 1V/div

PHASE

The Phase connection pin connects to the high side MOSFET source, output inductor, and low side MOSFET drain.

CSOP/CSON

CSOP/CSON is the battery charging current sensing positive/negative input. The differential volt age across CSOP and CSON is used to sense the battery charging current, and is compared with the charging current limit threshold to regulate the charging current. The CSON pin is also used as the battery feedback voltage to perform voltage regulation.

CSIP/CSIN

CSIP/CSIN is the AC adapter current sensing positive/negative input. The differential voltage across CSIP and CSIN is used to sense the AC adapter current, and is compared with the AC adapter current limit to regulate the AC adapter current.

GND

GND is an analog ground.

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FN9203.2

May 23, 2006

ISL6255, ISL6255A

DCIN

The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect a 0.1µF ceramic capacitor from DCIN to CSON.

ACSET

ACSET is an AC adapter detection input. Connect to a resistor divider from the AC adapter output.

ACPRN

Open-drain output signals AC adapter is present. ACPRN pulls low when ACSET is higher than 1.26V; and pulled high when ACSET is lower than 1.26V.

DCSET

DCSET is a lower voltage adapter detection input (like aircraft power 15V).Allows the adapter to power the system where battery charging has been disabled.

DCPRN

Open-drain output signals DC adapter is present. DCPRN pulls low when DCSET is higher than 1.26V; and pulled high when DCSET is lower than 1.26V.

EN

EN is the Charge Enable input. Connecting EN to high enables the charge control function, connecting EN to low disables charging functions. Use with a thermistor to detect a hot battery and suspend charging.

ICM

ICM is the adapter current output. The output of this pin produces a voltage proportional to the adapter current.

VDDP

VDDP is the supply voltage for the low-side MOSFET gate driver. Connect a 4.7Ω resistor to VDD and a 1μF ceramic capacitor to power ground.

ICOMP

ICOMP is a current loop error amplifier output.

VCOMP

VCOMP is a voltage loop amplifier output.

CELLS

This pin is used to select the battery voltage. CELLS = VDD for a 4S battery pack, CELLS = GND for a 3S battery pack, CELLS = Float for a 2S battery pack.

VADJ

VADJ adjusts battery regulation voltage. VADJ = VREF for

4.2V+5%/cell; VADJ = Floating for 4.2V/cell; VADJ = GND for 4.2V-5%/cell. Connect to a resistor divider to program the desired battery cell voltage between 4.2V-5% and 4.2V+5%.

CHLIM

CHLIM is the battery charge current limit set pin.CHLIM input voltage range is 0.1V to 3.6V. When CHLIM = 3.3V, the set point for CSOP-CSON is 165mV. The charger shuts down if CHLIM is forced below 88mV.

ACLIM

ACLIM is the adapter current limit set pin. ACLIM = VREF for 100mV, ACLIM = Floating for 75mV, and ACLIM = GND for 50mV. Connect a resistor divider to program the adapter current limit threshold between 50mV and 100mV.

PGND

PGND is the power ground. Connect PGND to the source of the low side MOSFET.

VDD

VDD is an internal LDO output to supply IC analog circuit. Connect a 1μF ceramic capacitor to ground.

VREF

VREF is a 2.39V reference output pin. It is internally compensated. Do not connect a decoupling capacitor.

9

FN9203.2

May 23, 2006

V

ACSET

V

ACSET

ACPRN

ACLIM

ICOMP

COMP

VADJ

CELLS

VREF

EN

PGND

LGATE

152K

VDDP

152K

PHASE

UGATE

BOOT

VDD

514K

DCIN

514K

BGATE

+

-

1.065V

1.06V

+

-

1.26V

VREF

Current Limit Set

2.1V

VREF

Reference

+

+-+

-

VDDP

Adapter

+

gm1

-

Voltage

Voltage Selector

Selector

VDD

1.26V

Adapter

1.27V

1.27V Current

Current

Limit Set

LDO

LDO LDO

LDO

+

-

- +-+

+-+-+

ISL6255, ISL6255A

ICM

SGATE

+

-

gm3

+

-

+

gm3

+

PWM

Regulator

gm1

Regulator

Regulator +

+

2.1V

Voltage

Selector

PWM

-

Min

Voltage

Buffer

-

CSON

1.26V

-

0.25V

0.25 V

V

CA2

´

20

X

CA2

-

- CA2

CA2

-

Min

Current

Buffer

+

++

CA2

CA2 CA2

CA2

V

CA2

+

19.9

+

CA1

+

-

+

-

+

-

+

-

+

´

CHLIM

CSIP

CA1

gm2

-

+

CSOP

CSIN

+

CA1

+

´

X

19.9

+

CA2

V

-

CA2

CA2 CA2

CA2

-

+

-

+

++

++ +

-

+

-

Buffer

Current

Min

+

CA1

-

gm3

gm3 gm3

gm3

-

20

CA2

+

+ +

+

-

+

-

CA2

-

CA2

´

V

0.25 V

0.25V

Buffer

Voltage

Min

-

PWM

+

CSON

DCSET

1.26V

CSON

-

+-+

+-+-+

-

Selector

Voltage

2.1V

+

LDO

LDO LDO

LDO

Regulator

gm1

Regulator

Current

1.27V

Adapter

1.26V

GND

DCPRN

Reference

VDD

+

514K

Selector

Selector Voltage

Voltage

514K

VREF

-

gm1

+

2.1V

Current Limit Set

152K

VREF

1.06V

1.065V

152K

Adapter

Limit Set

VDDP

-

- +

+-+

-

- +

+

-

+

BGATE

DCIN

VDD

BOOT

UGATE

PHASE

VDDP

LGATE

PGND

EN

VREF

CELLS

VADJ

COMP

ICOMP

ACLIM

ACPRN

ACSET

DCSET

DCPRN

GND

DCSET

CSON

CSIN

CSOP

CSIP

CHLIM

SGATE

ICM

FIGURE 14. FUNCTIONAL BLOCK DIAGRAM

10

FN9203.2

May 23, 2006

AC ADAPTER

ISL6255, ISL6255A

Q3

VREF

To Host

To Host Controller

Controller

R12

R12 20k 1%

20k 1%

TRICKLE

CHARGE

C7

1µF

1

R5

100k

C5:10nF

R11

130k

1%

Q6

VDD

R8

130k

1%

R9

10.2k

10.2k 1%

1%

3.3V

C6:6.8nF

R6: 10k

FLOATING

4.2V/CELL

CHARGE

ENABLE

2.6A CHARGE LIMIT

2.6A CHARGE LIMIT 253mA Trickle Charge

253mA Trickle Charge

R13

1.87k

1.87k 1%

1%

R10

4.7

4.7Ω

C9

1

µF

Q5

DCIN

ACSET

VDDP

VDD

ACPRN

VCOMP

VADJ

EN

ACLIM

VREF

CHLIM

C8

0.1

DCIN

ACSET

VDDP

VDD

ACPRN

ICOMP

VCOMP

VADJ

EN

ACLIM

VREF

CHLIM

µF

CSON

ISL6255

ISL6255 ISL6255A

ISL6255A

SGATE

CSIP

CSIN

BGATE

BOOT

UGATE

PHASE

LGATE

PGND

CSOP

CSON

CELLS

ICM

GND

R7: 100Ω

C2

µF

0.1

R3

R3 18

18

18Ω

VDDP

D2

C4

0.1

µF

0.1

Q2

C3

C3 1

1

µF

VDD

VDD 4 CELLS

4 CELLS

Q1

R4

2.2

2.2Ω

C11

C11 3300pF

3300pF

R2

R2 20m

20m

20mΩ

C1:10

D1

Optional

SYSTEM LOAD

Q4

F

µ

F

L

10

µH

R1

40m

40mΩ

BAT+

Battery

C10

C10 10

10

µF

Battery

Pack

BAT-

FIGURE 15. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS

11

FN9203.2

May 23, 2006

VCC

DIGITAL

INPUT

DIGITAL

INPUT

D/A OUTPUT

OUTPUT

A/D INPUT

HOST

AVDD/VREF

SCL

SCL SDL

SDL

A/D INPUT

GND

ADAPTER

R14

100k

1%

R15

11.5k

11.5k 1%

1%

R16 100k

100k

C11

C11 3300pF

3300pF

R11,R12

R11,R12 R13: 10K

R13: 10K

VDD

R8

130k

1%

R9

10.2k

10.2k 1%

1%

C7

µF

1

C9

µF

1

R5

R5 100k

100k

R7: 100Ω

R7:

5.15A INPUT

CURRENT LIMIT

C6

6.8nF

R6

R6 10k

10k

ISL6255, ISL6255A

C8

µ

0.1

0.1 CSON

CSON

ACSET

ISL6255

ISL6255A

CSON

UGATE

SGATE

CSIP

CSIN

BGATE

BOOT

UGATE

PHASE

LGATE

PGND

CSOP

CSON

CELLS

VADJ

R10

4.7

4.7Ω

VREF

C5

C5 10nF

10nF

Q5

DCIN

ACSET

DCSET

VDDP

VDD

ACPRN

DCPRN

CHLIM

EN

ICM

ACLIM

VREF

ICOMP

VCOMP

CSIP

CSIN

VADJ

GND

Q3

Q2

C2

0.1

R3: 18Ω

D2

C4

0.1

µF

VDDP

µF

C3

µF

1

GND

GND 3 CELLS

3 CELLS

FLOATING

4.2V/CELL

R2

R2 20m

20m

20mΩ

C1:10µF

C1:10

Q1

D1

Optional

R4

2.2

2.2Ω

L

µH

10

R1

R1 40m

40m

40mΩ

C10

C10 10

10

µF

SYSTEM LOAD

Q4

BAT+

BATTERY

Pack

SCL

SCL SDL

SDL

SDL TEMP

TEMP

TEMP BAT-

BAT-

FIGURE 16. ISL6255, ISL6255A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL AND AIRCRAFT POWER SUPPORT

12

May 23, 2006

FN9203.2

ISL6255, ISL6255A

Theory of Operation

Introduction

The ISL6255, ISL6255A includes all of the functions necessary to charge 2 to 4 cell Li-Ion and Li-polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A. The ISL6255, ISL6255A has input current limiting and analog inputs for setting the charge current and charge voltage; CHLIM inputs are used to control charge current and VADJ inputs are used to control charge voltage.

The ISL6255, ISL6255A charges the battery with constant charge current, set by CHLIM input, until the battery voltage rises up to a programmed charge voltage set by VADJ input; then the charger begins to operate at a constant voltage charge mode. The charger also drives an adapter isolation Pchannel MOSFET to efficiently switch in the adapter supply.

ISL6255, ISL6255A is a complete power source selection controller for single battery systems and also aircraft power applications. It drives a battery selector P-channel MOSFET to efficiently select between a single battery and the adapter. It controls the battery discharging MOSFET and switches to the battery when the AC adapter is removed, or, switches to the AC adapter when the AC adapter is inserted for single battery system.

The EN input allows shutdown of the charger through a command from a micro-controller. It also uses EN to safely shutdown the charger when the battery is in extremely hot conditions. The amount of adapter current is reported on the ICM output. Figure 14 shows the IC functional block diagram.

The synchronous buck converter uses external N-channel MOSFETs to convert the input voltage to the required charging current and charging voltage. Figure 15 shows the ISL6255, ISL6255A typical application circuit with charging current and charging voltage fixed at specific values. The typical application circuit shown in Figure 16 shows the ISL6255, ISL6255A typical application circuit which uses a micro-controller to adjust the charging current set by CHLIM input for aircraft power applications. The voltage at CHLIM and the value of R1 sets the charging current. The DC/DC converter generates the control signals to drive two external N-channel MOSFETs to regulate the voltage and current set by the ACLIM, CHLIM, VADJ and CELLS inputs.

The ISL6255, ISL6255A features a voltage regulation loop (VCOMP) and two current regulation loops (ICOMP). The VCOMP voltage regulation loop monitors CSON to ensure that its voltage never exceeds the voltage and regulates the battery charge voltage set by VADJ. The ICOMP current regulation loops regulate the battery charging current delivered to the battery to ensure that it never exceeds the charging current limit set by CHLIM; and the ICOMP current regulation loops also regulate the input current drawn from the AC adapter to ensure that it never exceeds the input

current limit set by ACLIM, and to prevent a system crash and AC adapter overload.

PWM Control

The ISL6255, ISL6255A employs a fixed frequency PWM current mode control architecture with a feed-forward function. The feed-forward function maintains a constant modulator gain of 11 to achieve fast line regulation as the buck input voltage changes. When the battery charge voltage approaches the input voltage, the DC/DC converter operates in dropout mode, where there is a timer to prevent the frequency from dropping into the audible frequency range. It can achieve duty cycle of up to 99.6%.

To prevent boosting of the system bus voltage, the battery charger operates in standard-buck mode when CSOPCSON drops below 4.25mV. Once in standard-buck mode, hysteresis does not allow synchronous operation of the DC/DC converter until CSOP-CSON rises above 12.5mV.

An adaptive gate drive scheme is used to control the dead time between two switches. The dead time control circuit monitors the LGATE output and prevents the upper side MOSFET from turning on until LGATE is fully off, preventing cross-conduction and shoot-through. In order for the dead time circuit to work properly, there must be a low resistance, low inductance path from the LGATE driver to MOSFET gate, and from the source of MOSFET to PGND. The external Schottky diode is between the VDDP pin and BOOT pin to keep the bootstrap capacitor charged.

Setting the Battery Regulation Voltage

The ISL6255, ISL6255A uses a high-accuracy trimmed band-gap voltage reference to regulate the battery charging voltage. The VADJ input adjusts the charger output voltage, and the VADJ control voltage can vary from 0 to VREF, providing a 10% adjustment range (from 4.2V-5% to

4.2V+5%) on CSON regulation voltage. An overall voltage accuracy of better than 0.5% is achieved.

The per-cell battery termination voltage is a function of the battery chemistry. Consult the battery manufacturers to determine this voltage.

• Float VADJ to set the battery voltage V number of the cells,

• Connect VADJ to VREF to set 4.41V × number of cells,

• Connect VADJ to ground to set 3.99V × number of the cells.

So, the maximum battery voltage of 17.6V can be achieved. Note that other battery charge voltages can be set by connecting a resistor divider from VREF to ground. The resistor divider should be sized to draw no more than 100µA from VREF; or connect a low impedance voltage source like the D/A converter in the micro-controller. The programmed battery voltage per cell can be determined by the following equation:

V 3.99V 175.0V

+=

VADJCELL

CSON

=4.2V ×

13

FN9203.2

May 23, 2006

ISL6255, ISL6255A

An external resistor divider from VREF sets the voltage at VADJ according to:

||

V

VADJ

where R

VREF

=

bot_VADJ

R

------------------------------------------------------------------------------------------------ -

×

R

top_VADJ 514k R

and R

bot_VADJ

||

top_VADJ

514k

||

+

bot_VADJ

514k

are external resistors at

VADJ. To minimize accuracy loss due to interaction with VADJ's

internal resistor divider, ensure the AC resistance looking back into the resistor divider is less than 25k.

Connect CELLS as shown in Table 1 to charge 2, 3 or 4 Li+ cells. When charging other cell chemistries, use CELLS to select an output voltage range for the charger. The internal error amplifier gm1 maintains voltage regulation. The voltage error amplifier is compensated at VCOMP. The component values shown in Figure 16 provide suitable performance for most applications. Individual compensation of the voltage regulation and current-regulation loops allows for optimal compensation.

TABLE 1. CELL NUMBER PROGRAMMING

CELLS CELL NUMBER

VDD 4 GND 3 Float 2

Setting the Battery Charge Current Limit

The CHLIM input sets the maximum charging current. The current set by the current sense-resistor connects between CSOP and CSON. The full-scale differential voltage between CSOP and CSON is 165mV for CHLIM = 3.3V, so the maximum charging current is 4.125A for a 40mΩ sensing resistor. Other battery charge current-sense threshold values can be set by connecting a resistor divider from VREF or 3.3V to ground, or by connecting a low impedance voltage source like a D/A converter in the micro-controller. Unlike VADJ and ACLIM, CHLIM does not have an internal resistor divider network. The charge current limit threshold is given by:

V

165mV

CHG

=

-------------------

I

To set the trickle charge current for the dumb charger, a resistor in series with a switch Q6 (Figure 15) controlled by the micro-controller is connected from CHLIM pin to ground. The trickle charge current is determined by:

165mV

CHG

=

-------------------

I

When the CHLIM voltage is below 88mV (typical), it will disable the battery charge. When choosing the current sensing resistor, note that the voltage drop across the sensing resistor causes further power dissipation, reducing

CHLIM

--------------------- -

R

1

V

CHLIM trickle,

--------------------------------------- -

R

1

3.3V

efficiency. However, adjusting CHLIM voltage to reduce the voltage across the current sense resistor R1 will degrade accuracy due to the smaller signal to the input of the current sense amplifier. There is a trade-off between accuracy and power dissipation. A low pass filter is recommended to eliminate switching noise. Connect the resistor to the CSOP pin instead of the CSON pin, as the CSOP pin has lower bias current and less influence on current-sense accuracy and voltage regulation accuracy.

Setting the Input Current Limit

The total input current from an AC adapter, or other DC source, is a function of the system supply current and the battery-charging current. The input current regulator limits the input current by reducing the charging current, when the input current exceeds the input current limit set point. System current normally fluctuates as portions of the system are powered up or down. Without input current regulation, the source must be able to supply the maximum system current and the maximum charger input current simultaneously . By using the input current limiter , the current capability of the AC adapter can be lowered, reducing system cost.

The ISL6255, ISL6255A limits the battery charge current when the input current-limit threshold is exceeded, ensuring the battery charger does not load down the AC adapter voltage. This constant input current regulation allows the adapter to fully power the system and prevent the AC adapter from overloading and crashing the system bus.

An internal amplifier gm3 compares the voltage between CSIP and CSIN to the input current limit threshold voltage set by ACLIM. Connect ACLIM to REF, Float and GND for the full-scale input current limit threshold voltage of 100mV, 75mV and 50mV, respectively, or use a resistor divider from VREF to ground to set the input current limit as the following equation

05.0

I

INPUT

⎛ ⎜

VREF

R

⎝

2

ACLIM

+= 050.0V

1

An external resistor divider from VREF sets the voltage at ACLIM according to:

V

ACLIM

where R

VREF

=

bot_ACLIM

------------------------------------------------------------------------------------------------------

×

R

and R

R

top_ACLIM 152k R

top_ACLIM

ACLIM. To minimize accuracy loss due to interaction with ACLIM's

internal resistor divider, ensure the AC resistance looking back into the resistor divider is less than 25k.

When choosing the current sense resistor, note that the voltage drop across this resistor causes further power dissipation, reducing efficiency. The AC adapter current sense accuracy is very important. Use a 1% tolerance

⎞ ⎟

⎠

||

+

bot_ACLIM

152k

bot_ACLIM

||

are external resistors at

||

152k

14

FN9203.2

May 23, 2006

ISL6255, ISL6255A

current-sense resistor. The highest accuracy of ±3% is achieved with 100mV current-sense threshold voltage for ACLIM = VREF , but it has the highest power dissipation. For example, it has 400mW power dissipation for rated 4A AC adapter and 1W sensing resistor may have to be used. ±4% and ±6% accuracy can be achieved with 75mV and 50mV current-sense threshold voltage for ACLIM = Floating and ACLIM = GND, respectively.

A low pass filter is suggested to eliminate the switching noise. Connect the resistor to CSIN pin instead of CSIP pin because CSIN pin has lower bias current and less influence on the current-sense accuracy.

AC Adapter Detection

Connect the AC adapter voltage through a resistor divider to ACSET to detect when AC power is available, as shown in Figure 15. ACPRN is an open-drain output and is high when ACSET is less than V above V

V •

rise,th

V −•

fall,th

Where I V

ACSET

hysteresis is I

. V

th,fall

⎛ ⎜ ⎜ ⎝

hys

th,rise

⎞

⎛

R

8

⎟

⎜ ⎜

R

⎝

R R

V1

+=

ACSET

⎟

9

⎠

⎞

8

⎟

+=

⎟

9

⎠

is the ACSET input bias current hysteresis and

= 1.24V (min), 1.26V (typ) and 1.28V (max). The

, where I

hysR8

, and active low when ACSET is

th,rise

and V

are given by:

th,fall

RIV1

8hysACSET

= 2.2µA (min), 3.4µA (typ)

hys

and 4.4µA (max).

DC Adapter Detection

Connect the DC adapter voltage like aircraft power through a resistor divider to DCSET to detect when DC power is available, as shown in Figure 16. DCPRN is an open-drain output and is high when DCSET is less than V active low when DCSET is above V

th,fall

. V

th,rise

and V

, and

th,fall

are given by:

V

th rise

V

th fall

Where I V

DCSET

⎜⎟

,

⎝⎠

R

⎛⎞

--------- - 1+

⎜⎟

,

R

⎝⎠

is the DCSET input bias current hysteresis and

hys

= 1.24V (min), 1.26V (typ) and 1.28V (max). The

hysteresis is I

---------- 1+

R

14 15

•=

15

R14, where I

hys

V

DCSET

V

–•=

DCSETIhysR14

hys

= 2.2µA (min), 3.4µA (typ)

R

⎛⎞

14

and 4.4µA (max).

Current Measurement

Use ICM to monitor the input current being sensed across CSIP and CSIN. The output voltage range is 0 to 2.5V. The

voltage of ICM is proportional to the voltage drop across CSIP and CSIN, and is given by the following equation:

ICM 19.9 I

where I

INPUT

••=

INPUTR2

is the DC current drawn from the AC adapter. ICM has ±3% accuracy. It is recommended to have an RC filter at the ICM output for minimizing the switching noise.

LDO Regulator

VDD provides a 5.0V supply voltage from the internal LDO regulator from DCIN and can deliver up to 30mA of current. The MOSFET drivers are powered by VDDP, which must be connected to VDDP as shown in Figure 15. VDDP connects to VDD through an external low pass filter. Bypass VDDP and VDD with a 1µF capacitor.

Shutdown

The ISL6255, ISL6255A features a low-power shutdown mode. Driving EN low shuts down the ISL6255, ISL6255A. In shutdown, the DC/DC converter is disabled, and VCOMP and ICOMP are pulled to ground. The ICM, ACPRN and DCPRN outputs continue to function.

EN can be driven by a thermistor to allow automatic shutdown of the ISL6255, ISL6255A when the battery pack is hot. Often a NTC thermistor is included inside the battery pack to measure its temperature. When connected to the charger, the thermistor forms a voltage divider with a resistive pull-up to the VREF. The threshold voltage of EN is

1.0V with 60mV hysteresis. The thermistor can be selected to have a resistance vs temperature characteristic that abruptly decreases above a critical temperature. This arrangement automatically shuts down the ISL6255, ISL6255A when the battery pack is above a critical temperature.

Another method for inhibiting charging is to force CHLIM below 85mV (typ).

Supply Isolation

If the voltage across the adapter sense resistor R2 is typically greater than 8mV, the P-channel MOSFET controlled by SGATE is turned on reducing the power dissipation. If the voltage across the adapter sense resistor R2 is less than 3mV, SGATE turns off the P-channel MOSFET isolating the adapter from the system bus.

Battery Power Source Selection and Aircraft Power Application

The battery voltage is monitored by CSON. If the battery voltage measured on CSON is less than the adapter voltage measured on DCIN, then the P-channel MOSFET controlled by BGATE turns off and the P-channel MOSFET controlled by SGATE is allowed to turn on when the adapter current is high enough. If it is greater, then the P-channel MOSFET controlled by SGATE turns of f and BGATE turns on the battery discharge P-channel MOSFET to minimize the power loss. Also, the

15

FN9203.2

May 23, 2006

ISL6255, ISL6255A

charging function is disabled. If designing for airplane power, DCSET is tied to a resistor divider sensing the adapter voltage. When a user is plugged into the 15V airplane supply and the battery voltage is lower than 15V, the MOSFET driven by BGATE (See Figure 16) is turned off which keeps the battery from supplying the system bus. The comparator looking at CSON and DCIN has 300mV of hysteresis to avoid chattering. Only 2S and 3S are supported for DC aircraft power applications. For 4S battery packs, set DCSET = 0.

Short Circuit Protection and 0V Battery Charging

Since the battery charger will regulate the charge current to the limit set by CHLIM, it automatically has short circuit protection and is able to provide the charge current to wake up an extremely discharged battery.

Over Temperature Protection

If the die temp exceeds 150°C, it stops charging. Once the die temp drops below 125°C, charging will start up again.

Application Information

The following battery charger design refers to the typical application circuit in Figure 15, where typical battery configuration of 4S2P is used. This section describes how to select the external components including the inductor, input and output capacitors, switching MOSFETs, and current sensing resistors.

Inductor Selection

The inductor selection has trade-offs between cost, size and efficiency. For example, the lower the inductance, the smaller the size, but ripple current is higher. This also results in higher AC losses in the magnetic core and the windings, which decrease the system efficiency. On the other hand, the higher inductance results in lower ripple current and smaller output filter capacitors, but it has higher DCR (DC resistance of the inductor) loss, and has slower transient response. So, the practical inductor design is based on the inductor ripple current being ±(15-20)% of the maximum operating DC current at maximum input voltage. The required inductance can be calculated from:

−

=

L

Where V

I

Δ

L

IN,MAX

VV

voltage, battery voltage and switching frequency, respectively. The inductor ripple current

Δ

I30%I ⋅=

where the maximum peak-to-peak ripple current is 30% of the maximum charge current is used.

For V

IN,MAX

f

= 300kHz, th e calculated inductance is 8.3µH. Choosing

s

=19V, V

the closest standard value gives L = 10µH. Ferrite cores are often the best choice since they are optimized at 300kHz to

V

BATMAX,IN

, V

BAT

f V

sMAX,IN

, and fs are the maximum input

BAT

MAXBAT,L

= 16.8V, I

BAT

BAT,MAX

ΔI is found from:

= 2.6A, and

600kHz operation with low core loss. The core must be large enough not to saturate at the peak inductor current I

II

1

I

Δ

+=

LMAX,BATPeak

2

Peak

:

Output Capacitor Selection

The output capacitor in parallel with the battery is used to absorb the high frequency switching ripple current and smooth the output voltage. The RMS value of the output ripple current I

I

V

RMS

rms

MAX,IN

f L 12

s

is given by:

()

D1 D

−=

where the duty cycle D is the ratio of the output voltage (battery voltage) over the input voltage for continuous conduction mode which is typical operation for the battery charger. During the battery charge period, the output voltage varies from its initial battery voltage to the rated battery voltage. So, the duty cycle change can be in the range of between 0.5 and 0.88 for the minimum battery voltage of 10V (2.5V/Cell) and the maximum battery voltage of 16.8V. The maximum RMS value of the output ripple current occurs at the duty cycle of 0.5 and is expressed as:

V

IN,MAX

MAX,IN

f L 124

s

= 19V, L = 10H, and fs= 300kHz, the maximum

I =

RMS

For V RMS current is 0.46A. A typical 10µF ceramic capacitor is a good choice to absorb this current and also has very small size. The tantalum capacitor has a known failure mechan ism when subjected to high surge current.

EMI considerations usually make it desirable to minimize ripple current in the battery leads. Beads may be added in series with the battery pack to increase the battery impedance at 300kHz switching frequency. Switching ripple current splits between the battery and the output capacitor depending on the ESR of the output capacitor and battery impedance. If the ESR of the output capacitor is 10m battery impedance is raised to 2

Ω with a bead, then only

Ω and

0.5% of the ripple current will flow in the battery.

MOSFET Selection

The Notebook battery charger synchronous buck converter has the input voltage from the AC adapter output. The maximum AC adapter output voltage does not exceed 25V. Therefore, 30V logic MOSFET should be used.

The high side MOSFET must be able to dissipate the conduction losses plus the switching losses. For the battery charger application, the input voltage of the synchronous buck converter is equal to the AC adapter output voltage, which is relatively constant. The maximum efficiency is achieved by selecting a high side MOSFET that has the conduction losses equal to the switching losses. Ensure that ISL6255, ISL6255A LGATE gate driver can supply sufficient

16

FN9203.2

May 23, 2006

ISL6255, ISL6255A

gate current to prevent it from conduction, which is due to the injected current into the drain-to -so u r ce parasitic capacitor (Miller capacitor C

), and caused by the voltage

gd

rising rate at phase node at the time instant of the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Reasonably slowing turn-on speed of the highside MOSFET by connecting a resistor between the BOOT pin and gate drive supply source, and the high sink current capability of the low-side MOSFET gate driver help reduce the possibility of cross-conduction.

For the high-side MOSFET, the worst-case conduction losses occur at the minimum input voltage:

P =

Conduction,1Q

V

OUT

V

2

RI

DSON

BAT

IN

The optimum efficiency occurs when the switching losses equal the conduction losses. However, it is difficult to calculate the switching losses in the high-side MOSFET since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the MOSFET internal gate resistance, gate charge, threshold voltage, stray inductance, pull-up and pull-down resistance of the gate driver. The following switching loss calculation provides a rough estimate.

P ++=

Where Q

: drain-to-gate charge, Qrr: total reverse recovery

gd

1 2

Q

f IV

sLVINSwitching,1Q

I

source,g

1

gd

2

charge of the body-diode in low side MOSFET, I valley current, I

Inductor peak current, I

LP:

g,sink

Q

f IV

sLPIN

I

: inductor

LV

and Ig,

gd

ksin,g

source

are the peak gate-drive source/sink current of Q1, respectively. To achieve low switching losses, it requires low drain-to-gate

charge Q

. Generally, the lower the drain-to-gate charge,

gd

the higher the on-resistance. Therefore, there is a trade-off between the on-resistance and drain-to-gate charge. Good MOSFET selection is based on the Figure of Merit (FOM), which is a product of the total gate charge and on-resistance. Usually, the smaller the value of FOM, the higher the efficiency for the same application.

For the low-side MOSFET, the worst-case power dissipation occurs at minimum battery voltage and maximum input voltage:

V

OUT

V

⎞

2

⎟

RI

DSON

BAT

⎟

IN

⎠

⎛ ⎜

1P

−=

2Q

⎜ ⎝

Choose a low-side MOSFET that has the lowest possible on-resistance with a moderate-sized package like the SO-8 and is reasonably priced. The switching losses are not an issue for the low side MOSFET because it operates at zero-voltage-switching.

Choose a Schottky diode in parallel with low-side MOSFET Q2 with a forward voltage drop low enough to prevent the low-side MOSFET Q2 body-diode from turning on during the

dead time. This also reduces the power loss in the high-side MOSFET associated with the reverse recovery of the low-side MOSFET Q2 body diode.

As a general rule, select a diode with DC current rating equal to one-third of the load current. One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs should be less than 24mA. So, the total gate charge for the high-side and low-side MOSFETs is limited by the following equation:

I

Q ≤

GATE

Where I less than 24mA. Substituting I

GATE

f

s

is the total gate drive current and should be

GATE

= 24mA and fs= 300kHz

GATE

into the previous equation yields that the total gate charge should be less than 80nC. Therefore, the ISL6255, ISL6255A easily drives the battery charge current up to 8A.

Input Capacitor Selection

The input capacitor absorbs the ripple current from the synchronous buck converter, which is given by:

fVQ

s INrr

()

VVV

II−=

BATrms

This RMS ripple current must be smaller than the rated RMS current in the capacitor datasheet. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents when the AC adapter is plugged into the battery charger. For Notebook battery charger applications, it is recommend that ceramic capacitors or polymer capacitors from Sanyo be used due to their small size and reasonable cost.

Table 2 shows the component lists for the typical application circuit in Figure 15.

TABLE 2. COMPONENT LIST

PARTS PART NUMBERS AND MANUFACTURER

C1, C10 10μF/25V ceramic capacitor, Taiyo Yuden

TMK325 MJ106MY X5R (3.2x2.5x1.9mm) C2, C4, C8 0.1 C3, C7, C9 1

C5 10nF ceramic capacitor C6 6.8nF ceramic capacitor

C11 3300pF ceramic capacitor

D1 30V/3A Schottky diode, EC31QS03L (optional) D2 100mA/30V Schottky Diode, Central Semiconductor

μF/50V ceramic capacitor

μF/10V ceramic capacitor, Taiyo Yuden

LMK212BJ105MG

OUTINOUT

V

IN

17

FN9203.2

May 23, 2006

ISL6255, ISL6255A

TABLE 2. COMPONENT LIST (Continued)

PARTS PART NUMBERS AND MANUFACTURER

L10μH/3.8A/26mΩ, Sumida, CDRH104R-100 Q1, Q2 30V/35m Q3, Q4 -30V/30m

Q5 Signal P-channel MOSFET, NDS352AP Q6 Signal N-channel MOSFET, 2N7002

R1 40m R2 20m R3 18 R4 2.2Ω, ±5%, (0805) R5 100k R6 10k, R7 100Ω, ±5%, (0805)

R8, R11 130k,

R9 10.2k R10 4.7Ω, ±5%, (0805) R12 20k R13 1.87k

Ω, FDS6912A, Fairchild

Ω, SI4835BDY, Siliconix

Ω, ±1%, LRC-LR2512-01-R040-F, IRC Ω, ±1%, LRC-LR2010-01-R020-F, IRC

Ω, ±5%, (0805)

Ω, ±5%, (0805) ±5%, (0805)

±1%, (0805)

Ω, ±1%, (0805)

Loop Compensation Design

ISL6255, ISL6255A uses a constant frequency current mode control architecture to achieve fast loop transient response. An accurate current sensing resistor in series with the output inductor is used to regulate the charge current, and the sensed current signal is injected into the voltage loop to achieve current mode control to simplify the loop compensation design. The inductor is not considered as a state variable for current mode control and the system becomes a single order system. It is much easier to design a compensator to stabilize the voltage loop than voltage mode control. Figure 17 shows the small signal model of the synchronous buck regulator.

PWM Comparator Gain Fm:

The PWM comparator gain Fm for peak current mode control is given by:

11

---------

M

.=

V

IN

Power Stage Transfer Functions

Transfer function F1(S) from control to output voltage is:

S

1

ˆ

v

o

()

SF

1

Where ,

V

==

ˆ

d

=

ω

esr

+

ω

in

ω

esr

2

SS

1

2

o

1

,

CR

oc

++

ω

Q

po

C

ω

o

RQ

≈

op

L

1

=

o

LC

o

Transfer function F

ˆ

i

()

2

==

SF

ˆ

d

(S) from control to inductor current is:

2

V

inL

RR

+

Lo

ω

S

1

+

ω

z

2 2

ω

o

, where .

SS

1

++

Q

po

1

ω

≈

z

CR

oo

Current loop gain Ti(S) is expressed as the following equation:

TiS() 0.25 RTF2S()M=

where R

is the trans-resistance in current loop. RT is

T

usually equal to the product of the charging current sensing resistance and the gain of the current sense amplifier, CA2. For ISL6255, ISL6255A, R

= 20R1.

T

The voltage gain with open current loop is:

TvS() KM F1S()AVS()=

V

FB

Where , V error amplifier. The Voltage loop gain with current loop

K =

V

o

is the feedback voltage of the voltage

FB

closed is given by:

v

(S)>>1, then it can be simplified as follows:

If T

i

L

S()

V

+

V

4

FB

-------------- -

V

O

()

ST1

i

ROR

----------------------------- -

R

+()

L

T

S

1

------------+

ω

esr

------------------------

S

1

-------+

ω

AVS()

P

1

-----------------

ω

≈

,=

P

R

OCO

()

ST

v

)S(L

=

From the above equation, it is shown that the system is a single order system, which has a single pole located at

ω

before the half switching frequency. Therefore, simple type II compensator can be easily used to stabilize the system.

ˆ

i

in

1:D

dˆI

dˆILdˆI

ˆ

v

in

+

0.25V

FIGURE 17. SMALL SIGNAL MODEL OF SYNCHRONOUS

dˆILdˆI

L

ˆ

d

dˆd

11/Vin

+

CA2

-

BUCK REGULATOR

ˆ

L

i

L

+

dˆV

dˆVindˆV

in

Rc

-Av(S)

Rc

Co

R

T

V

CA2

T

(S)

i

ˆ

v

comp

Ro

Tv(S)

ˆ

v

p

o

K

18

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Vo

V

FB

-

g

V

REF

+

FIGURE 18. VOLTAGE LOOP COMPENSATOR

V

COMP

C1

R1

COMP

m

Figure 17 shows the voltage loop compensator, and its transfer function is expressed as follo ws:

S

+

1

ω

==

g

1

CR

11

cz

m

SC

1

()

SA

v

where

ω

ˆ

v

cz

comp

ˆ

FB

=

Compensator design goal:

• High DC gain

• Loop bandwidth fc:

⎛ ⎜

⎝

⎞

−

f

⎟

s

20

5

⎠

1

• Gain margin: >10dB

• Phase margin: 40° The compensator design procedure is as follows:

1. Put compensator zero at

cz

CR

oo

1

31−=

()

ω

2. Put one compensator pole at zero frequency to achie ve high DC gain, and put another compensator pole at either esr zero frequency or half switching frequency, whichever is lower.

The loop gain T gain. Therefore, the compensator resistance R

(S) at cross over frequency of fc has unity

v

is

1

determined by:

8

=

R

1

11

where g

π

RCVf 2

Tooc

Vg

FBm

is the trans-conductance of the voltage loop error

m

amplifier. Compensator capacitor C1 is then given by:

1

=

C

1

R

ω

cz 1

Example: V C

=10μF/10mΩ, L = 10μH, gm= 250μs, RT=0.8Ω,

o

V

=2.1V, fc= 20kHz, then compensator resistance

FB

R

= 10kΩ. Put the compensator zero at 1.5kHz. The

1

compensator capacitor is C voltage loop compensator: R

= 20V, Vo= 16.8V, Io=2.6A, fs= 300kHz,

in

= 6.5nF. Therefore, choose

1

=10k, C1= 6.5nF.

1

PCB Layout Considerations

Power and Signal Layers Placement on the PCB

As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board. As an example, layer arrangement on a 4-layer board is shown below:

1. Top Layer: signal lines, or half board for signal lines and the other half board for power lines

2. Signal Ground

3. Power Layers: Power Ground

4. Bottom Layer: Power MOSFET, Inductors and other Power traces

Separate the power voltage and current flowing path from the control and logic level signal path. The controller IC will stay on the signal layer, which is isolated by the signal ground to the power signal traces.

Component Placement

The power MOSFET should be close to the IC so that the gate drive signal, the LGATE, UGATE, PHASE, and BOOT, traces can be short.

Place the components in such a way that the area under the IC has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals.

Signal Ground and Power Ground Connection

At minimum, a reasonably large area of copper, which will shield other noise couplings through the IC, should be used as signal ground beneath the IC. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each side, where there is little noise; a noisy trace beneath the IC is not recommended.

GND and VDD Pin

At least one high quality ceramic decoupling cap should be used to cross these two pins. The decoupling cap can be put close to the IC.

LGATE Pin

This is the gate drive signal for the bottom MOSFET of the buck converter. The signal going through this trace has both high dv/dt and high di/dt, and the peak charging and discharging current is very high. These two traces should be short, wide, and away from other traces. There should be no other traces in parallel with these traces on any layer.

PGND Pin

PGND pin should be laid out to the negative side of the relevant output cap with separate traces.The negative side of the output capacitor must be close to the source node of the bottom MOSFET. This trace is the return path of LGATE.

19

FN9203.2

May 23, 2006

ISL6255, ISL6255A

PHASE Pin

This trace should be short, and positioned away from other weak signal traces. This node has a very high dv/dt with a voltage swing from the input voltage to ground. No trace should be in parallel with it. This trace is also the return path for UGATE. Connect this pin to the high-side MOSFET source.

UGATE Pin

This pin has a square shape waveform with high dv/dt. It provides the gate drive current to charge and discharge the top MOSFET with high di/dt. This trace should be wide, short, and away from other traces similar to the LGATE.

BOOT Pin

This pin’s di/dt is as high as the UGATE; therefore, this trace should be as short as possible.

CSOP, CSON Pins

The current sense resistor connects to the CSON and the CSOP pins through a low pass filter. The CSON pin is also used as the battery voltage feedback. The traces should be away from the high dv/dt and di/di pins like PHASE, BOOT pins. In general, the current sense resistor should be close to the IC. Other layout arrangements should be adjusted accordingly.

DCIN Pin

This pin connects to AC adapter output voltage, and should be less noise sensitive.

Copper Size for the Phase Node

The capacitance of PHASE should be kept very low to minimize ringing. It would be best to limit the size of the PHASE node copper in strict accordance with the current and thermal management of the application.

Identify the Power and Signal Ground

The input and output capacitors of the converters, the source terminal of the bottom switching MOSFET PGND should connect to the power ground. The other components should connect to signal ground. Signal and power ground are tied together at one point.

Clamping Capacitor for Switching MOSFET

It is recommended that ceramic caps be used closely connected to the drain of the high-side MOSFET, and the source of the low-side MOSFET. This capacitor reduces the noise and the power loss of the MOSFET.

EN Pin

This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground.

20

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)

2X

0.15

C

E1/2

E1

A2

A

A1

8

E2

9 CORNER OPTION 4X

A1

A

E/2

9

/ /

9

(Ne-1)Xe

REF.

7

8

C

L

E

B

0.10 C

0.08

e

0.152XB

C

L1

C

L

10

A

6

INDEX

AREA

2X

SEATING PLANE

(DATUM B)

(DATUM A)

INDEX

AREA

FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE

0.15

6

CC

C

4X

C

4X P

NX L

e

1 2 3

B

AC0.15

0

8

C

L

D

9

N

BOTTOM VIEW

D1

D1/2

N

TOP VIEW

SIDE VIEW

NX b

D2

2

e

(Nd-1)Xe

REF.

NX b

5

L1

TERMINAL TIP

D/2

5

SECTION "C-C"

0.10 BAMC

7

NX k

N

1

2 3

L

10

A3

E2/2

L28.5x5

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)

MILLIMETERS

SYMBOL

A 0.80 0.90 1.00 -

A1 - 0.02 0.05 -

A2 - 0.65 1.00 9

A3 0.20 REF 9

b 0.18 0.25 0.30 5,8

D 5.00 BSC -

D1 4.75 BSC 9

D2 2.95 3.10 3.25 7,8

E 5.00 BSC -

E1 4.75 BSC 9

E2 2.95 3.10 3.25 7,8

e 0.50 BSC -

k0.20 - - -

L 0.50 0.60 0.75 8

N282

Nd 7 3

Ne 7 3

P- -0.609

θ --129

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P &

θ are present when

Anvil singulation method is used and not present for saw singulation.

NOTESMIN NOMINAL MAX

Rev. 1 11/04

21

FN9203.2

May 23, 2006

ISL6255, ISL6255A

Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)

N

INDEX AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

GAUGE

PLANE

0.25

0.010 h x 45°

L

α

e

B

0.17(0.007) C AM BS

M

A1

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.

A2

C

-1982.

M28.15

28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY)

INCHES MILLIMETERS

SYMBOL

A 0.053 0.069 1.35 1.75 A1 0.004 0.010 0.10 0.25 A2 - 0.061 - 1.54 -

B 0.008 0.012 0.20 0.30 9

C 0.007 0.010 0.18 0.25 -

D 0.386 0.394 9.81 10.00 3

E 0.150 0.157 3.81 3.98 4

e 0.025 BSC 0.635 BSC -

H 0.228 0.244 5.80 6.19 -

h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6

N28 287

α

0° 8° 0° 8° -

NOTESMIN MAX MIN MAX

Rev. 1 6/04

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time with out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

22

FN9203.2

May 23, 2006

Intersil ISL6255AHAZ, ISL6255AHRZ, ISL6255HAZ, ISL6255HRZ Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual