intersil ISL6227 DATA SHEET

®

ISL6227

December 21, 2006Data Sheet FN9094.4

Dual Mobile-Friendly PWM Controller with
DDR Option

The ISL6227 dual PWM controller delivers high efficiency
precision voltage regulation from two synchronous buck DC/DC
converters. It was designed especially to provide power
regulation for DDR memory, chip sets, graphics and other
system electronics in Notebook PCs. The ISL6227’s wide
input voltage range capability allows for voltage conversion
directly from AC/DC adaptor or Li-Ion battery pack.

Automatic mode transition of constant-frequency synchronous
rectification at heavy load, and hysteretic (HYS) diode­emulation at light load, assure high efficiency over a wide range
of conditions. The HYS mode of operation can be disabled
separately on each PWM converter if constant-frequency
continuous-conduction operation is desired for all load levels.
Efficiency is further enhanced by using the lower MOSFET
r

Voltage-fe ed-forward ramp modulation, current mode control,
and internal feedback compensation provide fast response to
input voltage and load transients. Input current ripple is
minimized by channel-to-channel PWM phase shift of 0°, 90° or
180° (determined by input voltage and status of the DDR pin).

The ISL6227 can control two inde pendent ou tput volt ages
adjustable from 0.9V to 5.5V, or by activating the DDR pin,
transform into a complete DDR memory power supply solution.
In DDR mode, CH2 output voltage VTT tracks CH1 output
voltage VDDQ. CH2 output can bo th source and sink current, an
essential power supply feature for DDR memory. The reference
voltage VREF required by DDR memory is generated as well.

In dual power supply applications the ISL6227 monitors the
output voltage of both CH1 and CH2. An independent PGOOD
(power good) signal is asserted for each channel after the
soft-start sequence has completed, and the output voltage is
within PGOOD window. In DDR mode CH1 generates the only
PGOOD signal.

Built-in overvoltage protection prevents the output from going
above 115% of the set point by holding the lower MOSFET on
and the upper MOSFET off. When the output voltage re-enters
regulation, PGOOD will go HIGH and normal operation
automatically resumes. Once the soft-start sequence has
completed, undervoltage protection latches the offending
channel off if the output drops below 75% of its set point value.
Adjustable overcurrent protection (OCP) monitors the voltage
drop across the r
current-sensing is required, an external current sense resistor
may be used.

as the current sense element.

DS(ON)

DS(ON)

of the lower MOSFET. If more precise

Features

• Provides regulated output voltage in the range 0.9V–5.5V

• Operates from an input battery voltage range of 5V to 24V
or from 3.3V/5V system rail

• Complete DDR1 and DDR2 memory power solution with
VTT tracking VDDQ/2 and a VDDQ/2 buffered reference
output

• Flexible PWM or HYS plus PWM mode selection with HYS
diode emulation at light loads for higher system efficiency

•r

current sensing

DS(ON)

• Excellent dynamic response with voltage feed-forward and
current mode control accommodating wide range LC filter
selections

• Undervoltage lock-out on VCC pin

• Power-good, overcurrent, overvoltage, undervoltage
protection for both channels

• Synchronized 300kHz PWM operation in PWM mode

• Pb-free plus anneal available (RoHS compliant)

Applications

• Notebook PCs and Desknotes

• Tablet PCs/Slates

• Hand-held portable instruments

Ordering Information

PART

PART #

ISL6227CA ISL6227CA -10 to +100 28 Ld QSOP M28.15
ISL6227CAZ

(Note)
ISL6227IA ISL6227IA -40 to +100 28 Ld QSOP M28.15
ISL6227IAZ

(Note)
ISL6227HRZ

(Note)
ISL6227IRZ

(Note)
Add -T to part number for Tape and Reel

NOTE: Intersil Pb-free plus anneal product s empl oy special Pb -free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoH S compliant and comp atible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classifie d at Pb-fre e peak ref low te mperat ures tha t
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

MARKING

ISL6227CAZ -10 to +100 28 Ld QSOP

ISL6227IAZ -40 to +100 28 Ld QSOP

ISL6227HRZ -10 to +100 28 Ld QFN

ISL6227IRZ -40 to +100 28 Ld QFN

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

M28.15

M28.15

L28.5x5

L28.5x5

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2004-2006. All Rights Reserved

Pinouts

28LD SSOP

TOP VIEW

ISL6227

28 LD 5X5 QFN

TOP VIEW

1

GND

LGATE1

PHASE1
UGATE1

2
3

PGND1

4
5
6

BOOT1

7

ISEN1

8

EN1

9

VOUT1

10

VSEN1

11

SOFT1 SOFT2

12

DDR

13

VIN PG1

14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Generic Application Circuits

V

IN

+5V to +24V

+5V

VCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
ISEN2
EN2
VOUT2
VSEN2
OCSET2OCSET1

PG2/REF

OCSET1

OCSET2

EN1
EN2
VCC

DDR

PWM1

PWM2

Q1

Q2

PHASE1
UGATE1

BOOT1

ISEN1

EN1
VOUT1
VSEN1

PGN1

LGATE1

28 27 26 25 24 23 22
1
2
3
4
5
6
7

8 9 10 11 12 13 14

SOFT1

OCSET1

L1

+

C1

Q3

Q4

GND

GND

29

DDR

VCC

LGATE2

PGND2

PHASE2

21

UGATE2

20

BOOT2

19

ISEN2

18

EN2

17

VOUT2

16

VSEN2

15

OCSET2

VIN

PG1

SOFT2

PG2/REF

V

OUT1

+1.80V

L2

C2

V

OUT2

+1.20V

+

V

IN

+5V to 24V

VREF

+1.25V

ISL6227 APPLICATION CIRCUIT FOR TWO CHANNEL POWER SUPPLY

+5V

OCSET1

EN1

EN2
VCC
DDR

PG2/VREF

PWM1

PWM2

Q1

Q2

OCSET2

L1

C1

+

Q3

Q4

ISL6227 APPLICATION CIRCUIT FOR COMPLETE DDR MEMORY POWER SUPPLY

2

L2

C2

VDDQ

+2.50V

VTT

+1.25V

+

FN9094.4

December 21, 2006

ISL6227

Absolute Maximum Ratings

Bias Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.5V

Input Voltage, V

PHASE, UGATE . . . . . . . . . . . . . . . . . . . .GND-5V (Note 1) to 33.0V

BOOT, ISEN . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to +33.0V

BOOT with Respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . + 6.5V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +25.0V

IN

+ 0.3V

CC

Thermal Information

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

SSOP Package (Note 2)
QFN Package(Notes 3, 4)

Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C

. . . . . . . . . . . . . .

. . . . . . . . . . . .

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

80 N/A
36 6

Recommended Operating Conditions

Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V ± 5%

Input Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . .+5.0V to +24.0V

IN

Ambient Temperature Range . . . . . . . . . . . . . . . . . -10°C to +100°C

Junction Temperature Range. . . . . . . . . . . . . . . . . -10°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. 250ns transient. See Confining The Negative Phase Node Voltage Swing in Application Information Section
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See T ech

3. θ

JA

Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY

Bias Current I

Shut-down Current I

CC

CCSN

LGATEx, UGATEx Open, VSENx forced above
regulation point, V

IN

> 5V

VCC UVLO

Rising VCC Threshold V
Falling VCC Threshold V

V

IN

Input Voltage Pin Current (Sink) I
Shut-Down Current I

CCU
CCD

VIN

VINS

OSCILLATOR

PWM1 Oscillator Frequency F

Commercial, ISL6227C 255 300 345 kHz

c

Industrial, ISL6227I 240 300 345 kHz
Ramp Amplitude, pk-pk V
Ramp Amplitude, pk-pk V
Ramp Offset V
Ramp/V
Ramp/V

Gain G

IN

Gain G

IN

ROFF

RB1 VIN
RB2

VIN = 16V, by design - 2 - V

R1

VIN = 5V, by design - 0.625 - V

R2

By design - 1 - V

≥ 4.2V, by design - 125 - mV/V

VIN ≤ 4.1V by design - 250 - mV/V

REFERENCE AND SOFT-START

Internal Reference Voltage V

REF

Reference Voltage Accuracy -1.0 - +1.0 %
Soft-Start Current During Start-Up I
Soft-Start Comple te Threshold V

SOFT

ST

By design - 1.5 - V

-1.83.0mA

--1μA

4.3 4.45 4.5 V

44.144.34V

--35μA

--1μA

-0.9- V

--4.5- μA

3

FN9094.4

December 21, 2006

ISL6227

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

PWM CONVERTERS

Load Regulation 0.0mA < I
VSEN Pin Bias Current I
Minimum Duty Cycle D
Maximum Duty Cycle D
VOUT Pin Input Impedance I
Undervoltage Shut-Down Level V
Overvoltage Protection V

VSEN

max

VOUT

UVL

OVP1

By design - 80 - nA

min

VOUT = 5V - 134 - kΩ

Fraction of the set point; ~2μs noise filter 70 75 80 %

Fraction of the set point; ~2μs noise filter 110 115 - %

< 5.0A; 5.0V < V

VOUT1

GATE DRIVERS

Upper Drive Pull-Up Resistance R
Upper Drive Pull-Down Resistance R
Lower Drive Pull-Up Resistance R
Lower Drive Pull-Down Resistance R

2UGPUPVCC
2UGPDNVCC
2LGPUPVCC
2LGPDNVCC

= 5V - 4 8 Ω
= 5V - 2.3 4 Ω
= 5V - 4 8 Ω
= 5V - 1.1 3 Ω

POWER GOOD AND CONTROL FUNCTIONS

Power Good Lower Threshold V
Power Good Higher Threshold V
PGOODx Leakage Current I
PGOODx Voltage Low V

PG-

PG+

PGLKGVPULLUP

PGOODIPGOOD

Fraction of the set point; ~3μs noise filter 84 89 92 %

Fraction of the set point; ~3μs noise filter. 110 115 120 %

= 5.5V - - 1 μA

= -4mA - 0.5 1 V
ISEN Sourcing Current By design - - 260 μA
OCSET Sourcing Current Range 2-20μA
EN - Low (Off) --0.8V
EN - High (On) 2.0 - - V
Continuous-Conduction-Mode(CCM)

VOUTX pulled low - - 0.1 V

Enforced (HYS Operation Inhibited)
Automatic CCM/HYS Operation

VOUTX connected to the output 0.9 - - V

Enabled
DDR - Low (Off) --0.8V
DDR - High (On) 3--V
DDR REF Output Voltage V

DDR REF Output Current I

DDREF

DDREF

DDR = 1, I

DDR = 1. Guaranteed by design. - 10 12 mΑ

= 0...10mA 0.99*

REF

< 24.0V -2.0 - +2.0 %

BATT

-4-%

-87-%

V

OC2

V

OC2

1.01*

V

OC2

V

4

FN9094.4

December 21, 2006

Typical Operation Performance

ISL6227

100

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.01 0.1 1 10
LOAD CURRENT (A)

EFF@ 5V
EFF@ 12V
EFF@ 19.5V
EFF@ 5V, PWM
EFF@ 12V, PWM
EFF@ 19.5V, PWM

FIGURE 1. EFFICIENCY OF CHANNEL 1, 2.5V ,

HYS/PWM MODE

2.54

2.53

2.52

2.51

Vout @ 5V
Vout @ 12V
Vout @ 19.5V
Vout @ 5V, PWM
Vout @ 12V, PWM
Vout @ 19.5V, PWM

100

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.01 0.1 1 10
LOAD CURRENT (A)

EFF@ 5V
EFF@ 12V
EFF@ 19.5V
EFF@ 5V, PWM
EFF@ 12V, PWM
EFF@ 19.5V, PWM

FIGURE 2. EFFICIENCY OF CHANNEL 2, 1.8V,

HYS/PWM MODE

1.83

1.82

1.81

Vout @ 5V
Vout @ 12V
Vout @ 19.5V
Vout @ 5V, PWM
Vout @ 12V, PWM
Vout @ 19.5V, PWM

2.5

2.49

OUTPUT VOLTAGE (V)

2.48

2.47
012345

LOAD CURRENT (A)

1.8

OUTPUT VOLTAGE (V)

1.79

1.78
012345

LOAD CURRENT (A)

FIGURE 3. OUTPUT VOLTAGE OF CHANNEL 1 vs LOAD FIGURE 4. OUTPUT VOLTAGE OF CHANNEL 2 vs LOAD

308

306
304
302
300
298
296

FREQUENCY (KHz)

294
292
290
288
286

-20 0 20 40 60 80 100

75% Quantile
Frequency Mean
25% Quantile

TEMPERATURE (°C)

120

0.9025

0.902

0.9015

0.901

0.9005

0.9

VREF (V)

0.8995

0.899

0.8985

0.898

0.8975

-20 0 20 40 60 80 100 120

75% Quantile
Vref Mean
25% Quantile

TEMPERATURE (°C)

FIGURE 5. SWITCHING FREQUENCY OVER TEMPERATURE FIGURE 6. REFERENCE VOLTAGE ACCURACY OVER

TEMPERATURE

5

FN9094.4

December 21, 2006

Typical Operation Performance (Continued)

ISL6227

Vo1

Vphase1

Ilo1

Vo2

FIGURE 7. LOAD TRANSIENT (0 - 3A AT CHANNEL 1)

(DIODE EMULATION MODE)

Vo1

Vphase2

Vo1

Vphase1

Ilo1

Vo2

FIGURE 8. LOAD TRANSIENT (0 - 3A AT CHANNEL 1)

(FORCED PWM MODE)

Vo1

Vphase2

Ilo2

Vo2

FIGURE 9. LOAD TRANSIENT (0 - 2A AT CHANNEL 2)

(DIODE EMULATION MODE)

Vin1

Vo1

Vo2

Ilo2

Vo2

FIGURE 10. LOAD TRANSIENT (0 - 3A AT CHANNEL 2)

(FORCED PWM MODE)

Vin1

Vo1

Vo2

FIGURE 11. INPUT STEP-UP TRANSIENT AT PWM MODE FIGURE 12. INPUT STEP-UP TRANSIENT AT HYS MODE

6

FN9094.4

December 21, 2006

Typical Operation Performance (Continued)

ISL6227

Vin1

Vo1

Vo2

FIGURE 13. INPUT STEP-DOWN TRANSIENT AT PWM MODE FIGURE 14. INPUT STEP-DOWN TRANSIENT AT HYS MODE

EN1

PG1

Vin1

Vo1

Vo2

EN1

PG1

SOFT1

Vo1

FIGURE 15. SOFT-START INTERVAL AT ZERO INITIAL

VOLTAGE OF VO

Vo1

Vphase1

Ilo1

Vo2

SOFT1

Vo1

FIGURE 16. SOFT-ST ART INTERVAL WITH NON-ZERO INITIAL

VOLTAGE OF VO

Vo1

Vphase1

Ilo1

Vo2

FIGURE 17. OPERATION A T LIGHT LOAD OF 100mA,

CHANNEL 1

7

FIGURE 18. OPERATION AT HEAVY LOAD OF 4A,

CHANNEL 1

December 21, 2006

FN9094.4

Typical Operation Performance (Continued)

ISL6227

Vo1

PG1

Ilo1

Vo2

FIGURE 19. OVERCURRENT PROTECTION AT CHANNEL 1 FIGURE 20. SHORT-CIRCUIT PROTECTION AT CHANNEL 1

Vo1

Vphase1

Vo1

PG1

Ilo1

Vo2

Vo1

Vphase2

Ilo1

Vo2

FIGURE 21. MODE TRANSITION OF HYS

EN1

PG1

SOFT1

Vo1

→ _PWM

Ilo2

Vo2

FIGURE 22. MODE TRANSITION OF PWM

VTT

OCSET

VDDQ

VCC

→ HYS

FIGURE 23. SOFT SHUTDOWN INTERVAL

8

FIGURE 24. V

POWER-UP IN DDR MODE

CC

FN9094.4

December 21, 2006

Typical Operation Performance (Continued)

ISL6227

VDDQ

PGOOD1

VTT

IL1

FIGURE 25. VIN = 19V, VDDQ 3A STEP LOAD, VTT 0A LOAD FIGURE 26. VIN = 19V, VDDQ 3A STEP LOAD, VTT 3A LOAD

VDDQ

VTT

VDDQ

PGOOD1

VTT

IL1

VDDQ

VTT

OCSET2

IL2

FIGURE 27. VIN = 19V , LOAD STEP ON VTT,

VDDQ HYS MODE, 0.14A

VDDQ

Vin

VTT

OCSET2

OCSET2

IL2

FIGURE 28. VIN = 19V, LOAD STEP ON VTT,

VDDQ PWM MODE, 0.14A

VTT

EN1

VDDQ

IL1

FIGURE 29. INPUT LINE TRANSIENT IN DDR MODE FIGURE 30. VTT FOLLOWS VDDQ, ENABLE 2 IS HIGH

9

FN9094.4

December 21, 2006