intersil ISL6226 DATA SHEET

查询ISL6226EVAL1供应商

ISL6226

Data Sheet August 2002

Advanced PWM and Linear Power Controller for Portable Applications

The ISL6226 provides power control and protection for two user selected output voltages required in high-performance notebook PC applications. The IC integrates a fixed, selectable frequency pulse-width-modulation (PWM) controller and a 3A LDO linear regulator controller with monitoring and protection circuitry in a single 24 lead SSOP package.

The PWM controller regulates the battery input voltage to a user selected output voltage. Synchronous converter and hysteretic operation at light loads contribute to a high efficiency over a wide range of input voltage and load variation. Efficiency can be further enhanced by using the lower MOSFET’s r

DS(ON)

voltage feed-forward ramp modulation, current-mode control, and internal feed-back compensation provide fast and stable handling of input voltage load transients encountered in advanced portable computer chip sets.

as the current sense element. Input

FN9078.1

Features

• Provides Two Regulated Voltages

- Linear Regulator, User Selected, Current Limited

- High Efficiency PWM Over Wide Line and Load Range

- Synchronous Buck Converter on PWM Output

- Hysteretic Operation at Light Load

• Dual Mode Operation:

- Directly From Battery Input, V VCC of 5V

• PWM Output Adjustable From 0.9V to 0.93*V

• Low Drop-Out (LDO) Linear Regulator Operates from Vout+0.5V to 24V

• LDO Output Adjustable

- From 0.8V to 3.8V at 0A to 3A for NPN Transistor

- From 0.8V to 3.0V at 0A to 3A for N-MOSFET

• 300/600kHz Switching Frequency Selectable

, of 5.6V to 24V or from

The internal linear regulator controller provides a user selected high current output from an unregulated input with user selected current limit.

Ordering Information

PART

NUMBER

ISL6226CA -10 to 85 24 Ld SSOP M24.15

ISL6226EVAL1 Evaluation Board

TEMP. RANGE

(

C) PACKAGE PKG. NO.

Pinout

ISL6226 (SSOP)

TOP VIEW

VOUT

VSEN

FPWM

PGOODP

ISEN

BOOT

UGATE

PHASE

SSPWM

PVCC

LGATE

PGND

VIN

PGOODL

PWMEN

OCSET

LINEN

VCC

LINDR

LINCS1

LINCS2

SSLIN

LINVS

GND

12 13

• Forced PWM Mode Control Option

• No Current-Sense Resistor Required on PWM Output

- Uses MOSFET’s r

DS(ON)

- Optional Current-Sense Resistor for More Precision

• Separate Soft-Start For Both PWM and LDO

• Separate Enable Pins for both PWM and LDO for Advanced Configuration and Power Interface (ACPI) Compatibility

• Input Under voltage Lock-Out (UVLO) Protection

• Excellent Dynamic Response

- Input Voltage Feed-Forward and Current-Mode Control

• Monitors Output Voltages and Provides PGOOD Status

• Thermal Shut-Down Protection

Applications

•

Mobile PCs

• Hand-Held Portable Instruments

• Other Devices and Appliances With up to 24V Input

Related Literature

• AN1013

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

ISL6226

Absolute Maximum Ratings Thermal Information

Bias Voltage, Vcc. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 7V

Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30.0V

Phase and Isen Pins . . . . . . . . . . . . . . . . . . . . . GND-0.3V to +30.0V

Boot and Ugate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 35.0V

BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V

Imax for LINDR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70mA

All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 7V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Recommended Operating Conditions

Bias Voltage, Vcc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ %

Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +24.0V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -10

Junction Temperature Range. . . . . . . . . . . . . . . . . . -10

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ

JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5.0V 5±

C to 85oC

C to 125oC

Thermal Resistance (Typical, Note 1) θ

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature (Plastic Package) . . 150

Maximum Storage Temperature Range. . . . . . . . . . -65

(oC/W)

C to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SSOP - Lead Tips Only)

Electrical Specifications Operating Conditions: Vcc = 5V, T

= -10oC to 85oC, Unless Otherwise Noted.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY

Bias Current I

LGATE, UGATE Open, VSEN forced above regulation point (Fs = 300K Hz)

LGATE, UGATE Open, VSEN forced above

- 1100 - µA

regulation point (Fs = 600K Hz)

Shut-down Current I

CCSN

-525µA

VCC UVLO

Rising Vcc Threshold 4.30 - 4.65 V

Falling Vcc Threshold 4.1 - 4.45 V

Vcc Hysterises 30 500 mV

VIN

Input Voltage Pin Current (Sink) I

Input Voltage Pin Current (Source) I

Shut-down Current I

VIN

VIN pin connected to the input voltage

10 20 30 µA

source

VIN pin connected to ground -7 -12 -17 µA

--1µA

OSCILLATOR

PWM Oscillator Frequency F

Ramp Amplitude, pk-pk V

Ramp Offset V

ROFF

VIN=3.5V -- 24V 255 300 345 kHz

≤0.5V 510 600 690 kHz

VIN= 16V - 2 - V

≤5V - 1.25 - V

-0.5- V

PWM CONTROLLER

REFERENCE AND SOFT START

PWM Internal Reference Voltage V

PWM Soft-Start Threshold V

REF

SOFT

-0.9- V

-1.5- V

Reference Voltage Accuracy -2.0 - +2.0 %

ISL6226

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Soft-Start Current During Start-up I

SOFT

PWM CONVERTER

Load Regulation 0.0mA < I

VSEN pin bias current I

VOUT pin input impedance I

Under-Voltage Shut-Down Level V

VSEN

VOUT

UV1

Fraction of the set point; ~3µs noise filter 70 - 76 %

< 5.0A; 5.0V < VIN < 24.0V -2.0 - +2.0 %

VOUT1

Under Voltage Delay UV_DLY 3 - 5.5 uS

Over-Voltage Protection V

OVP1

Fraction of the set point; ~1µs noise filter 113.5 - 118 %

Over Voltage Delay OVP_DLY 0.5 - 2.7 uS

PWM CONTROLLER GATE DRIVER

Upper Drive Pull-Up Resistance R

Upper Drive Pull-Down Resistance R

Lower Drive Pull-Up Resistance R

Lower Drive Pull-Down Resistance R

2UGPUP

2UGPDN

2LGPUP

2LGPDN

POWER GOOD AND CONTROL FUNCTIONS

Power Good Lower Threshold V

Power Good Higher Threshold V

PGOOD Leakage Current I

PG-

PG+

PGLKG

PGOOD Voltage Low I

Fraction of the set point; ~3µs noise filter -13.5 - -7.5 % Fraction of the set point; ~3µs noise filter 7.4 - 13.5 %

PGOOD

= 5.5V - - 1 µA

PULLUP

= -4mA - - 0.5 V

EN- Low (Off) --0.8V

EN - High (On) 2.0 - - V

FCCM -Hysteretic Operation Enabled -Vcc/2- V

LOW DROP OUT CONTROLLER FUNTIONS

Linear Input Voltage Vin No External Passive Device - Vcc - V

Linear Input Voltage Vin With External Passive Device Device Rating

Linear Output Voltage LDOout No External Passive Device 0.8 - 4.5 V

Output Drive Current for NPN I(DRV) out 50 - - mA

OverCurrent Feedback Voltage V(CS) 100 mV

Under-Voltage Shut-Down Level V

Under-Voltage Delay UV

Fraction of the set point; ~3µs noise filter 71 74 77 %

DLY

REFERENCE AND SOFT START

LDO Internal Reference Voltage V

LDO Soft-Start Threshold V

REF

SOFT

Reference Voltage Accuracy -2.0 - +2.0 %

Soft-Start Current During Start-up I

SOFT

POWER GOOD AND CONTROL FUNTIONS

Power Good Lower Threshold V

Power Good Higher Threshold V

PG-

PG+

Vo<V

Vo>V

REF

PGOOD Leakage Current IPGLKG VPULLUP = 5.5V - - 1.0 uA

PGOOD Voltage Low VPGOOD IPGOOD = -4mA, VCC = 4.75V - - 0.5 V

LINEN-Low (OFF) --0.8V

-5- µA

-80- nA

135 150 198 kOhm

6.2 8.5 13.5 Ω

2.5 3.0 4.7 Ω

6.2 8.5 13.4 Ω

1.3 1.6 2.7 Ω

5.5 - 8 uS

-0.8- V

1.5 V

-5- µA

-15.5 -12 -9 %

10.5 13.5 16.5 %

ISL6226

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

LINEN-High (ON) 2.0 - - V

Input Bias Current LINCS1 and LINCS2 Ibias1 Vlincs = 0.8 V - -80 - nA

Input Bias Current LINVS Ibias2 Vlinvs = 0.8 V - -80 - nA

Functional Pin Descriptions

VIN (Pin 1)

Provides battery voltage to the oscillator for feed-forward rejection of the input voltage variation. Also, this pin programs frequency of the internal clock and gain of the ramp generator.

PGOODL (Pin 2)

PGOODL is an open drain output used to indicate the status of the LDO output voltages. This pin is pulled low when the output voltage is not within of its respective nominal voltage or over 120mV between pin 8 and 9.

PWMEN (Pin 3)

This pin provides enable/disable function the PWM output. The output is enabled when this pin is high. The PWM output is held off when this pin is pulled to ground. Intersil recommends to use hysteresis mode when input voltage higher than 18V and output voltage is 1.25V or less.

OCSET (Pin 4)

A resistor on this pin to ground sets the over current threshold for the PWM controller.

LINEN (Pin 5)

This pin provides enable/disable function and soft-start for the LDO. The output is enabled when this pin is high. The LDO is held off when this pin is pulled to ground.

VCC (Pin 6)

Input power for the controller and the upper MOSFET gate drive. The IC starts to operate when the voltage on this pin exceeds 4.3V and stops operating when the voltage on this pin drops below approximately 4.45V.

LINDR (Pin 7)

Current output to drive the NPN transistor.

LINCS1 (Pin 8)

High side of current sense resistor.

LINCS2 (Pin 9)

Low side of current sense resistor. Current limit for the linear regulator is initiated when the voltage difference between LINCS1 and LINCS2 is 120mV.

SSLIN (Pin 10)

This pin provides soft start of the LDO controller. When the EN pin is pulled high, the voltage on the capacitor connected to the soft start pin is rising linearly due to the 5 pull-up current. The output voltage follows the voltage on the

µA

capacitor till it reaches the value of 0.8V. At this moment the output voltage starts to regulate and soft start continues to rise to 1.5V. At this time, the soft start is complete and the PGOODL will be high to indicate the output voltage within its respective nominal voltage. The further rise of soft start capacitor does not affect the output voltage. The soft-start time can be obtained from the following equation.

Tsslin

1.5VxCss

----------------------------=

5µA

LINVS (Pin 11)

Voltage regulation point (0.8V) for the linear output.

GND (Pin 12)

Signal ground for the IC. All voltage levels are measured with respect to this pin.

PGND (Pin 13)

This is the lower MOSFET gate drive return connection for PWM converter. Tie the lower MOSFET source directly to this pin.

LGATE (Pin 14)

This pin provides the gate drive for the lower MOSFET. Connect the lower MOSFET gate to this pin.

PVCC (Pin 15)

This pin powers the lower MOSFET gate driver.

SSPWM (Pin 16)

This pin provides soft start of the PWM controller. This pin has the same function as SSLIN pin. When the EN pin is pulled high, the voltage on the capacitor connected to the soft start pin is rising linearly due to the 5 output voltage follows the voltage on the capacitor till it reaches the value of 0.9V. At this moment the output voltage starts to regulate and soft start continues to rise to 1.5V. At this time, the soft start is complete and the PGOODPWM will be high to indicate the output voltage within its respective nominal voltage. The further rise of soft start capacitor does not affect the output voltage. The soft-start time can be obtained from the following equitation.

Tsspwm

1.5VxCss

----------------------------=

5µA

pull-up current. The

µA

PHASE (Pin17)

The phase node is the junctions of the upper MOSFET source, output filter inductor, and lower MOSFET drain. Connect the PHASE pin directly to the PWM converter’s lower MOSFET drain.

ISL6226

UGATE (Pin18)

This pin provides the gate drive for the upper MOSFET. Connect UGATE pin to the PWM converter’s upper MOSFET gate.

BOOT (Pin 19)

Power is supplied to the upper MOSFET driver of the PWM converter via the BOOT pin. Connect this pin to the junction the bootstrap capacitor with the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to pin 6, VCC.

ISEN (Pin 20)

This pin is used to monitor the voltage drop across the lower MOSFET for current feedback control. For more precise current detection, this input can be connected to optional current sense resistors placed in series with the source of the lower MOSFET.

PGOODP (Pin 21)

PGOODP is an open drain output used to indicate the status of the PWM converter’s output voltages. This pin is pulled low when the output is not within of their respective nominal voltage.

FPWM (Pin 22)

This pin when pulled to VCC restrains hysterectic operation in light loads.

VSEN (Pin 23)

This pin is connected to the PWM voltage divider to provide the voltage feedback signal for the PWM controller. The PGOODP, overvoltage protection (OVP) and undervoltage shutdown circuits use this signal to determine output voltage status and/or to initiate undervoltage shut down.

VOUT (Pin 24)

The output voltage is sensed on this pin to provide feedback during the PWM to Hysteretic mode transition.

ISL6226

BOOT

FPWM

GND

UGATE

HGDR1

FPWM

PHASE

SHUTOFF

PVCC

GATE

CONTROL

GATE LOGIC

POR

DEADT

PWM/HYST

LGATE

LGDR

PWM ON

PGND

OVP

HYST ON

COMP

FFBK

CLAMP

ISEN

LGATE

R1=20K

LGATE1

VSEN

CLK1

HYST COMP1

OC COMP1

OC LOGIC1

VCC

PWM

LATCH 1

D Q

MODE CHANGE

REF

VOLTAGE

OCSET

VOUT

PWM/HYS

LOGIC

POWER-ON

RESET (POR)

VSEN

LINDR

POR

LINCS1

OUTPUT

MONITOR

RAMP

VCC

VIN

CLK

POR

FSET

PWMEN

SDWN

REFERENCE

LINEN

REF

AND

SOFT START

SSPWM

OVP UVO

SSLIN

VOLTAGE

PGOODP

PGOODL

SDWN

LINEAR

CONTROLLER

LINCS2

REF

LINVS

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

+ 11 hidden pages