intersil ISL6208A DATA SHEET

®

www.BDTIC.com/Intersil

ISL6208A

Data Sheet February 15, 2006 FN9272.0

High Voltage Synchronous Rectified Buck
MOSFET Driver

The ISL6208A is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is
especially suited for mobile computing applications that
require high efficiency and excellent thermal performance.
This driver, combined with an Intersil multiphase Buck PWM
controller, forms a complete single-stage core-voltage
regulator solution for advanced mobile microprocessors.

The ISL6208A features 4A typical sinking current for the
lower gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the Phase node.
This prevents shoot-through power loss caused by the high
dv/dt of phase voltages. The operating voltage matches the
30V breakdown voltage of the MOSFETs commonly used in
mobile computer power supplies.

The ISL6208A also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown.
This feature eliminates a protective Schottky diode usually
seen in a microprocessor power systems.

MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208A. Each driver is capable of driving a 3000pF
load with propagation delays of 15ns and transition times
under 10ns. Bootstrapping is implemented with an internal
Schottky diode. This reduces system cost and complexity,
while allowing the use of higher performance MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.

A diode emulation feature is integrated in the ISL6208A to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will
allow discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off
the low side MOSFET gate. Programmable dead-time
control with gate threshold monitoring is also integrated to
prevent both MOSFETs from conducting simultaneously.

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”

• Technical Brief TB447 “Guidelines for Preventing Boot-to­Phase Stress on Half-Bridge MOSFET Driver ICs”

Features

• Dual MOSFET Drives for Synchronous Rectified Bridge

• Adaptive Shoot-Through Protection

- Active Gate Threshold Monitoring

- Programmable Dead-Time

•0.5Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency up to 2MHz

- Fast Output Rise and Fall Time

- Low Propagation Delay

• Three-State PWM Input for Power Stage Shutdown

• Internal Bootstrap Schottky Diode

• Low Bias Supply Current (5V, 100µA)

• Diode Emulation for Efficiency and Pre-Biased Startup

• VCC POR (Power-On-Reset) Feature Integrated

• Pin-to-pin Compatible with ISL6207, ISL6208, ISL6209

• QFN Package:

- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Supplies for Intel® and AMD® Mobile Microprocessors

• High Frequency, Low Profile DC/DC Converters

• High Current Low Output Voltage DC/DC Converters

• High Input Voltage DC/DC Converters

Ordering Information

TEMP.

PART

PART NUMBER

ISL6208ACBZ
(Note)

ISL6208ACBZ-T
(Note)

ISL6208ACRZ
(Note)

ISL6208ACRZ-T
(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

ISL6208ACBZ -10 to 100 8 Ld SOIC

ISL6208ACBZ 8 Ld SOIC Tape and Reel

08AZ -10 to 100 8 Ld 3x3 QFN

08AZ 8 Ld 3x3 QFN Tape and Reel

RANGE

(°C) PACKAGE

(Pb-Free)

(Pb-Free)

(Pb-Free)

(Pb-Free)

PKG.

DWG.

#

M8.15

L8.3x3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2006. All Rights Reserved

Pinouts

www.BDTIC.com/Intersil

UGATE

BOOT

PWM

GND

Block Diagram

ISL6208ACB

(8 LD SOIC)

TOP VIEW

1

2

3

4

8

7

6

5

PHASE

FCCM

VCC

LGATE

ISL6208A

BOOT

PWM

ISL6208ACR

(8 LD 3x3 QFN)

TOP VIEW

UGATE

PHASE

7

8

1

2

43

GND

LGATE

6

6

5

FCCM

VCC

Timing Diagram

PWM

UGATE

t

PDHU

VCC

FCCM

PWM

t

RU

t

PDLU

10K

SHOOT-

THROUGH

CONTROL

LOGIC

PROTECTION

THERMAL PAD (FOR QFN PACKAGE ONLY)

FIGURE 1. BLOCK DIAGRAM

2.5V

t

FU

1V

t

PTS

VCC

t

RU

t

TSSHD

BOOT

UGATE

PHASE

LGATE

GND

t

FU

LGATE

1V

t

t

PDLL

t

FL

t

PDHL

RL

t

TSSHD

t

FL

2

t

PTS

February 15, 2006

FN9272.0

ISL6208A

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V
BOOT Voltage (V
BOOT To PHASE Voltage (V

PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V

UGATE Voltage . . . . . . . . . . . . . . . . V

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40°C to 125°C

, V

FCCM

BOOT-GND

V

PHASE

GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V

). . . . . . . . . . . . . -0.3V to VCC + 0.3V

PWM

). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V

BOOT-PHASE

GND -8V (<20ns Pulse Width, 10µJ)

- 5V (<20ns Pulse Width, 10µJ) to V

) . . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

- 0.3V (DC) to V

PHASE

BOOT
BOOT

Thermal Resistance (Typical Notes 2, 3, 4) θ

SOIC Package (Note 2) . . . . . . . . . . . . 110 n/a

QFN Package (Notes 3, 4). . . . . . . . . . 80 15

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10°C to 100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The Phase Voltage is capable of withstanding -7V DC when the BOOT pin is at GND.
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

3. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

(°C/W) θJC (°C/W)

JA

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Bias Supply Current I

POR Vcc Rising - 3.30 3.90 V

POR Hysteresis - 400 - mV

BOOTSTRAP DIODE

Forward Voltage V

PWM INPUT

Input Current I

PWM Three-State Rising Threshold V

PWM Three-State Falling Threshold V

Three-State Shutdown Holdoff Time t

UG/LG Three-state Propagation Delay t

FCCM INPUT

FCCM Threshold -2.5- V

FCCM Transient Delay R

SWITCHING TIME

UGATE Rise Time (Note 5) t

LGATE Rise Time (Note 5) t

UGATE Fall Time (Note 5) t

VCC

PWM

TSSHD

PTS

RU

RL

FU

PWM pin floating, V

Vcc Falling 2.40 2.90 - V

V

F

= 5V, forward bias current = 2mA 0.45 0.60 0.65 V

VCC

V

= 5V, V

PWM

V

PWM

VCC

VCC

V

VCC

= 0Ω -70-ns

SET

V

VCC

V

VCC

V

VCC

FCCM

= 0V, V

FCCM

= 5V 0.70 1.00 1.30 V

= 5V 3.5 3.8 4.1 V

= 5V, temperature = 25°C - 70 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V, 3nF Load - 8.0 - ns

= 5V - 100 - µA

FCCM

= 5V - 250 - µA

= 5V - -250 - µA

-20-ns

3

FN9272.0

February 15, 2006