Intersil ISL61851ACBZ, ISL61851AIBZ, ISL61851BCBZ, ISL61851BIBZ, ISL61851CCBZ Schematic [ru]

Dual USB Port Power Supply Controller

ISL6185

The ISL6185 USB power controller family provides fully
independent overcurrent (OC) fault protection for two or more
USB ports.

This product family consists of sixteen individual functional
product variants and three package options. It is operation
rated for a nominal +2.5V to +5V range and is specified over the
full commercial and industrial temperature ranges.

Each ISL6185 type incorporates in a single package two 71mΩ
P-channel MOSFET power switches for power control. Each
features internal current monitoring, accurate current limiting,
and current limited delay to turn-off, for system supply
protection along with control and communication I/O.

The ISL6185 family offers product variants with specified
continuous output current levels of 0.6A, 1.1A, 1.5A or 1.8A; enable
active high or low inputs; and latch off or automatic retry after
overcurrent turn-off, making these devices well suited for many
low-power applications.

This family of ICs is offered in an industry-standard SOIC pinout
and also in the 70% smaller 3x3 DFN packages providing similar
or enhanced performance in the smallest possible package.

Features

• 2.5V to 5V Operating Range

•71mΩ Integrated Power P-channel MOSFET Switches

• Continuous Current Options for 0.6A, 1.1A, 1.5A and 1.8A

• Thermally Insensitive 12ms of Current Limiting Prior to
Turn-O ff

• Output Discharges with Reverse Current Blocking When
Disabled

• Latch-off or Auto Restart Options

• 1µA Off-State Supply Current

• Enable Polarity Options

• Industry-standard Pin for Pin SOIC, and Smaller DFN Packages
Available

• UL Recognized, File Number: E333469

Applications

• USB 1, 2, 3 Port Power Management

• Low Power (18W) Electronic Circuit Limiting and Breaker

D+

D-

U
S
B

C
O
N

+5V
T
R
O
L
L
E
R

FIGURE 1. TYPICAL APPLICATION FIGURE 2. NORMALIZED r

ENABLE_1

FAULT_1

VIN

FAULT_2

ENABLE_2

USB PORT POWER

OUT_1

GND

ISL6185

OUT_2

D+
D-

USB

PORT 1

VBUS

VBUS

USB

PORT_2

1.3

1.2

1.1

DS(ON)

1.0

0.9

NORMALIZED r

0.8

0.7

-40 -25 0 25 45 75 85 115

CHARACTERISTIC CURVE

TEMPERATURE (°C)

TEMPERATURE

DS(ON)

March 8, 2012
FN6937.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

|Copyright Intersil Americas Inc. 2010, 2011, 2012. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Simplified Block Diagram

GND

ISL6185

CHANNEL 1 LIKE CHANNEL 2

-

-V

comp

+

FAULT_1

VIN

POR

EN_1

EN_2 FAULT_2

CURRENT AND TEMP.

MONITORING, GATE,

DELAY & OUTPUT CONTROL

LOGIC

OUT_1

OUT_2

Ordering Information

V

= 5V

IN

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

EN/EN

INPUT

ISL61851ACBZ 61851A CBZ EN 0.6 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851BCBZ 61851B CBZ EN 0.6 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851CCBZ 61851C CBZ EN 1.1 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851DCBZ 61851D CBZ EN 1.1 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851ECBZ 61851E CBZ EN

ISL61851FCBZ 61851F CBZ EN 0.6 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851GCBZ 61851G CBZ EN 1.1 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851HCBZ 61851H CBZ EN 1.1 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851ICBZ 61851I CBZ EN 1.5 LATCH 0 to +70 8 Lead SOIC M8.15

ISL61851JCBZ 61851J CBZ EN 1.5 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61851KCBZ 61851K CBZ EN

ISL61851LCBZ 61851L CBZ EN 1.5 RETRY 0 to +70 8 Lead SOIC M8.15

ISL61852ACRZ 52AC EN 0.6 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852BCRZ 52BC EN 0.6 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852CCRZ 52CC EN 1.1 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852DCRZ 52DC EN 1.1 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852ECRZ 52EC EN

MAXIMUM

CONTINUOUS IOUT

(A)

LATCH/AUTO

RETRY

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

0.6 LATCH 0 to +70 8 Lead SOIC M8.15

1.5 LATCH 0 to +70 8 Lead SOIC M8.15

0.6 LATCH 0 to +70 8 Lead DFN L8.3x3J

PKG.

DWG. #

2

FN6937.3

March 8, 2012

ISL6185

Ordering Information (Continued)

V

= 5V

IN

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

ISL61852FCRZ 52FC EN 0.6 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852GCRZ 52GC EN 1.1 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852HCRZ 52HC EN

ISL61852ICRZ 52IC EN 1.5 LATCH 0 to +70 8 Lead DFN L8.3x3J

ISL61852JCRZ 52JC EN 1.5 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61852KCRZ 52KC EN

ISL61852LCRZ 52LC EN 1.5 RETRY 0 to +70 8 Lead DFN L8.3x3J

ISL61853ACRZ 53AC EN 0.6 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853BCRZ 53BC EN 0.6 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853CCRZ 53CC EN 1.1 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853DCRZ 53DC EN 1.1 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853ECRZ 53EC EN

ISL61853FCRZ 53FC EN 0.6 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853GCRZ 53GC EN

ISL61853HCRZ 53HC EN 1.1 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853ICRZ 53IC EN 1.5 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853JCRZ 53JC EN 1.5 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853KCRZ 53KC EN

ISL61853LCRZ 53LC EN 1.5 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853MCRZ 53MC EN 1.8 LATCH 0 to +70 10 Lead DFN L10.3x3

ISL61853NCRZ 53NC EN 1.8 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61853OCRZ 53OC EN

ISL61853PCRZ 53PC EN 1.8 RETRY 0 to +70 10 Lead DFN L10.3x3

ISL61851AIBZ 61851A IBZ EN 0.6 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851BIBZ 61851B IBZ EN 0.6 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851CIBZ 61851C IBZ EN 1.1 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851DIBZ 61851D IBZ EN 1.1 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851EIBZ 61851E IBZ EN

ISL61851FIBZ 61851F IBZ EN

ISL61851GIBZ 61851G IBZ EN 1.1 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851HIBZ 61851H IBZ EN 1.1 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851IIBZ 61851I IBZ EN 1.5 LATCH -40 to +85 8 Lead SOIC M8.15

ISL61851JIBZ 61851J IBZ EN 1.5 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61851KIBZ 61851K IBZ EN

ISL61851LIBZ 61851L IBZ EN 1.5 RETRY -40 to +85 8 Lead SOIC M8.15

ISL61852AIRZ 52AI EN 0.6 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852BIRZ 52BI EN 0.6 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852CIRZ 52CI EN 1.1 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852DIRZ 52DI EN 1.1 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852EIRZ 52EI EN

EN/EN

INPUT

MAXIMUM

CONTINUOUS IOUT

(A)

1.1 RETRY 0 to +70 8 Lead DFN L8.3x3J

1.5 LATCH 0 to +70 8 Lead DFN L8.3x3J

0.6 LATCH 0 to +70 10 Lead DFN L10.3x3

1.1 LATCH 0 to +70 10 Lead DFN L10.3x3

1.5 LATCH 0 to +70 10 Lead DFN L10.3x3

1.8 LATCH 0 to +70 10 Lead DFN L10.3x3

0.6 LATCH -40 to +85 8 Lead SOIC M8.15

0.6 RETRY -40 to +85 8 Lead SOIC M8.15

1.5 LATCH -40 to +85 8 Lead SOIC M8.15

0.6 LATCH -40 to +85 8 Lead DFN L8.3x3J

LATCH/AUTO

RETRY

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

3

FN6937.3

March 8, 2012

ISL6185

Ordering Information (Continued)

V

= 5V

IN

PART

NUMBER

(Notes 1, 2, 3) PART MARKING

ISL61852FIRZ 52FI EN 0.6 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852GIRZ 52GI EN 1.1 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852HIRZ 52HI EN

ISL61852IIRZ 52II EN 1.5 LATCH -40 to +85 8 Lead DFN L8.3x3J

ISL61852JIRZ 52JI EN 1.5 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61852KIRZ 52KI EN

ISL61852LIRZ 52LI EN 1.5 RETRY -40 to +85 8 Lead DFN L8.3x3J

ISL61853AIRZ 53AI EN 0.6 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853BIRZ 53BI EN 0.6 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853CIRZ 53CI EN 1.1 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853DIRZ 53DI EN 1.1 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853EIRZ 53EI EN

ISL61853FIRZ 53FI EN 0.6 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853GIRZ 53GI EN

ISL61853HIRZ 53HI EN 1.1 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853IIRZ 53II EN 1.5 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853JIRZ 53JI EN 1.5 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853KIRZ 53KI EN

ISL61853LIRZ 53LI EN 1.5 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853MIRZ 53MI EN 1.8 LATCH -40 to +85 10 Lead DFN L10.3x3

ISL61853NIRZ 53NI EN 1.8 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61853OIRZ 53OI EN

ISL61853PIRZ 53PI EN 1.8 RETRY -40 to +85 10 Lead DFN L10.3x3

ISL61851EVAL1Z 8 Lead SOIC Evaluation Platform with ISL61851A installed

ISL61852EVAL1Z 8 Lead DFN Evaluation Platform with ISL61852H installed

ISL61853EVAL1Z 10 Lead DFN Evaluation Platform with ISL61853I installed

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb­free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL6185XXC
For more information on MSL please see techbrief TB363

EN/EN

INPUT

MAXIMUM

CONTINUOUS IOUT

(A)

1.1 RETRY -40 to +85 8 Lead DFN L8.3x3J

1.5 LATCH -40 to +85 8 Lead DFN L8.3x3J

0.6 LATCH -40 to +85 10 Lead DFN L10.3x3

1.1 LATCH -40 to +85 10 Lead DFN L10.3x3

1.5 LATCH -40 to +85 10 Lead DFN L10.3x3

1.8 LATCH -40 to +85 10 Lead DFN L10.3x3

for details on reel specifications.

.

LATCH/AUTO

RETRY

(commercial version) and ISL6185XXI (industrial version).

TEMP.

RANGE (°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

4

FN6937.3

March 8, 2012

Pin Configurations

ISL6185

ISL6185

(8 LD SOIC/DFN)

TOP VIEW

GND

1

2

3

4

(GND)
EPAD

DFN Only

VIN OUT1

EN1/EN1

EN2/EN2

FLT1

8

7

6

OUT2

5

FLT2

GND

VIN OUT1

VIN NC

EN1/EN1

EN2/EN2

ISL6185

(10 LD DFN)

TOP VIEW

1

2

3

4

5

(GND)

EPAD

FLT1

10

9

8

7

OUT2

6

FLT2

Pin Descriptions

PIN NUMBER

8 Ld

SOIC/DFN 10 Ld DFN

1 1 GND IC ground reference.

2 2, 3 VIN Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip bias voltage. At

SYMBOL DESCRIPTION

VIN < 1.7V chip functionality is disabled, FLT

is active and floating, and OUT is held low. Range 0V to

5.5V.

3,

4

5,

8

10

4,

6,

EN1, EN1

5

EN2, EN2

FLT2
FLT1

/

Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power switch. These
inputs have internal 1MΩ pull-off resistors. Range 0V to VIN.

Overcurrent Fault Indicator. FLT floats and is disabled until VIN >V
the current limit time-out period has expired. Fault is not signaled due to over-temperature shut down.
Range 0V to VIN.

6,

7

7,

OUT2,

9

OUT1

Controlled Supply Output. Upon an OC condition, I
within 200µs. This output remains in current limit for a nominal 12ms before being turned off either for
the latch or auto retry versions. Range 0V to VIN.

- 8 NC This pin is not electrically connected internally.

PD

PD EPAD Thermal Dissipation Exposed PAD Range: Connect to GND.

(DFN only)

. This output is pulled low after

UVLO

is current limited. Current limit response time is

OUT

5

FN6937.3

March 8, 2012

ISL6185

Absolute Maximum Ratings Thermal Information

Supply Voltage (VIN to GND, Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V

EN, FAULT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VIN 0.3V

Output Current . . . . . . . . . . . Short Circuit Protected Current Limit of 2.5A

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . 3kV

Machine Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . 300V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

Operating Conditions

Commercial Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 5.5V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.

NOTES:

4. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

5. θ

JA

Brief TB379

6. For θ

7. All voltages are relative to GND, unless otherwise specified.

.

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Thermal Resistance (Typical, Note 4)

θ

(°C/W) θJC (°C/W)

JA

8 Lead SOIC Package (Note 4). . . . . . . . . . 120 N/A

8 Lead 3x3 DFN Package (Notes 5, 6) . . . 48 6

10 Lead 3x3 DFN Package (Notes 5, 6) . . 53 6

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Electrical Specifications V

range, 0°C to +75°C or -40°C to +85°C.

= 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

IN

SYMBOL PARAMETER TEST CONDITIONS

POWER SWITCH

r

DS(ON)_50

r

DS(ON)_33

r

DS(ON)_25

V

OUT_DIS

R

OUT_PU

t

R

t

F

t

F_fast

ON-Resistance at 5.0V (Pulse Tested) VIN = 5V, I

= TJ = +85°C - 110 mΩ

T

A

ON-Resistance at 3.3V (Pulse Tested) VIN = 3.3V, I

= TJ = +85°C - 130 mΩ

T

A

On Resistance at 2.5V (Pulse Tested) VIN = 2.5V, I

= TJ = +85°C - 150 mΩ

T

A

= 0.1A, TA = TJ = +25°C - 71 87 mΩ

OUT

= 0.1A, TA = TJ = +25°C - 90 105 mΩ

OUT

= 0.1A, TA = TJ = +25°C - 114 127 mΩ

OUT

Disabled Output Voltage VIN = 5V, Switch Disabled, 50µA Load - 50 70 mV

Output Pull-Down Resistor VIN = 5V, Switch Disabled 8 9.6 12 kΩ

V

Rise Time RL = 10Ω, CL = 10µF, 10% to 90% - 100 - µs

OUT

Slow V

Fast V

Turn-off Fall Time RL = 10Ω, CL = 10µF, 90% to 10% - 200 - µs

OUT

Turn- off Fa ll Time RL = 1Ω, CL = 10µF, 80% to 20% - 23 - µs

OUT

CURRENT CONTROL

I

OUT_CONT_5

I

OUT_CONT_5

I

OUT_CONT_5

I

OUT_CONT_5

I

OUT_CONT_3

I

OUT_CONT_3

I

OUT_CONT_3

I

OUT_CONT_3

Maximum Continuous Current, VIN=
5V.
Guaranteed by Itrip minimum
specification.

Maximum Continuous Current, VIN =

3.3V.
Guaranteed by Itrip minimum
specification.

ISL6185xA,B,E,F - 0.6 A

ISL6185xC,D,G,H - 1.1 A

ISL6185xI,J,K,L - 1.5 A

ISL61853M,N,O,P (10 Ld DFN) - 1.8 A

ISL6185xA,B,E,F - 0.6 A

ISL6185xC,D,G,H - 0.9 A

ISL61851I,J,K,L (SOIC) - 1.3 A

ISL61852, ISL61853 (DFN) - 1.5 A

MIN

(Note 8) TYP

MAX

(Note 8) UNITS

6

FN6937.3

March 8, 2012

ISL6185

Electrical Specifications V

range, 0°C to +75°C or -40°C to +85°C. (Continued)

= 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

IN

SYMBOL PARAMETER TEST CONDITIONS

I

OUT_CONT_2

I

OUT_CONT_2

I

OUT_CONT_2

I

OUT_CONT_2

I

OUT_CONT_2

I

TRIP_5

I

TRIP_5

I

TRIP_5

I

TRIP_5

I

TRIP_3

I

TRIP_3

I

TRIP_3

I

TRIP_3

I

TRIP_2

I

TRIP_2

I

TRIP_2

I

TRIP_2

I

LIM_5

I

LIM_5

I

LIM_5

I

LIM_5

I

LIM_3

I

LIM_3

I

LIM_3

I

LIM_3

I

LIM_2

I

LIM_2

I

LIM_2

I

LIM_2

I

sc_5

I

sc_5

I

sc_5

I

sc_5

I

sc_3

I

sc_3

I

sc_3

I

sc_3

Maximum Continuous Current, VIN=

2.5V

ISL6185xA,B,E,F - 0.6 - A

ISL61851C,D,G,H,I,J,K,L (SOIC) - 0.9 - A

ISL61852, ISL61853 C,D,G,H (DFN) - 1 - A

ISL61853I,J,K,L (10 Ld DFN) - 1 - A

ISL61853M,N,O,P (10 Ld DFN) - 1 - A

Trip Current, VIN = 5V ISL6185xA,B,E,F 0.70 1.02 1.52 A

ISL6185xC,D,G,H 1.15 1.45 1.95 A

ISL6185xI,J,K,L 1.55 1.82 2.25 A

ISL61853M.N,O,P 1.85 1.99 2.45 A

Trip Current, VIN = 3.3V ISL6185xA,B,E,F 0.65 0.86 1.20 A

ISL6185xC,D,G,H 0.95 1.25 1.60 A

ISL6185xI,J,K,L 1.35 1.60 1.85 A

ISL61853M.N,O,P 1.55 1.89 2.25 A

Trip Current, VIN = 2.5V ISL6185xA,B,E,F - 0.65 - A

ISL6185xC,D,G,H - 1- A

ISL6185xI,J,K,L - 1.2 - A

ISL61853M.N,O,P - 1.6 - A

Current Limit, VIN = 5V ISL6185xA,B,E,F, VIN - V

ISL6185xC,D,G,H, VIN - V

ISL6185xI,J,K,L, VIN - V

OUT

ISL61853M,N,O,P, VIN - V

Current Limit, VIN = 3.3V ISL6185xA,B,E,F, VIN - V

ISL6185xC,D,G,H, VIN - V

ISL6185xI,J,K,L, VIN - V

OUT

ISL61853M,N,O,P, VIN - V

Current Limit, V

= 2.5V ISL6185xA,B,E,F, VIN - V

IN

ISL6185xC,D,G,H, VIN - V

ISL6185xI,J,K,L, VIN - V

OUT

ISL61853M,N,O,P, VIN - V

Short Circuit Current, VIN = 5V ISL6185xA,B,E,F, V

ISL6185xC,D,G,H, V

ISL6185xI,J,K,L, V

ISL61853M,N,O,P, V

Short Circuit Current, VIN= 3.3V ISL6185XA,B,E,F, V

ISL6185XC,D,G,H, V

ISL6185xI,J,K,L, V

ISL61853M,N,O,P, V

= 0V 0.60 0.80 1.00 A

OUT

OUT

= 0V 1.15 1.61 1.85 A

OUT

OUT

= 0V 0.35 0.48 0.60 A

OUT

OUT

= 0V 0.70 1.06 1.25 A

OUT

OUT

MIN

(Note 8) TYP

= 1V 0.50 0.65 0.78 A

OUT

= 1V 0.98 1.14 1.28 A

OUT

MAX

(Note 8) UNITS

= 1V 1.30 1.55 1.72 A

= 1V 1.52 1.83 2.20 A

OUT

= 1V 0.45 0.63 0.75 A

OUT

= 1V 0.90 1.10 1.26 A

OUT

= 1V 1.25 1.50 1.68 A

= 1V 1.48 1.78 2.05 A

OUT

= 1V 0.47 0.61 0.74 A

OUT

= 1V 0.90 1.05 1.17 A

OUT

= 1V 1.15 1.37 1.58 A

= 1V 1.3 1.63 1.90 A

OUT

= 0V 1.00 1.27 1.55 A

= 0V 1.20 1.70 2.5 A

= 0V 0.65 0.80 0.95 A

= 0V 0.90 1.24 1.50 A

7

FN6937.3

March 8, 2012

ISL6185

Electrical Specifications V

range, 0°C to +75°C or -40°C to +85°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

tsett

I

sc_2

I

sc_2

I

sc_2

I

sc_2

I

sc_5.5

tsett

Ilim_sev

t

t

RTY

Ilim

CL

Short Circuit Current, VIN= 2.5V ISL6185xA,B,E,F, V

Short Circuit Current, VIN= 5.5V All ISL6185X Variants --2.5A

OC to Limit Settling Time VIN/RL = 2I

Severe OC to Limit Settling Time VIN/RL = 4I

Current Limit Duration I

Automatic Retry Period 0.80 1 1.35 s

= 5V, TA = TJ, Unless Otherwise Specified. Boldface limits apply over the operating temperature

IN

ISL6185xC,D,G,H, V

ISL6185xI,J,K,L, V

ISL61853M,N,O,P, V

, CL = 10µF to within 10% of I

LIM

, CL = 10µF to within 10% of I

LIM

= I

OUT

9.2 12 15 ms

LIM

MIN

(Note 8) TYP

= 0V - 0.61 A

OUT

= 0V - 1.06 - A

OUT

= 0V - 1.30 - A

OUT

= 0V - 1.39 - A

OUT

LIM

LIM

-200- µs

-30- µs

MAX

(Note 8) UNITS

I/O PARAMETERS

Vfault_lo Fault Output Voltage Fault I

= 10mA - - 0.4 V

OUT

Ifault Fault Leakage -5- µA

Venr_5 EN / EN

Hys_Venr_5 EN / EN

Venr_3 EN / EN

Hys_Venr_3 EN / EN

Venr_2 EN / EN

Hys_Venr_2 EN / EN

Rising Threshold VIN = 5V 1.5 1.8 2 V

Rising Threshold Hysteresis VIN = 5V 80 140 175 mV

Rising Threshold VIN = 3.3V 1.0 1.3 1.6 V

Rising Threshold Hysteresis VIN = 3.3V 58 80 120 mV

Rising Threshold VIN = 2.5V 0.95 1.1 1.3 V

Rising Threshold Hysteresis VIN = 2.5V 30 70 110 mV

Ren_h ENABLE Pull-Down Resistor Enable asserted high options 0.6 1 1.55 MΩ

Ren_l ENABLE

t

ON

t

OFF

Pull-Up Resistor Enable asserted low options 0.6 1 1.55 MΩ

Enable to Output Turn-on Time RL = 10Ω, CL = 10µF, Enable 50% to Output 90% - 0.1 - ms

Enable to Output Turn-off Time RL = 10Ω, CL = 10µF, Enable 50% to Output 10% - 0.25 - ms

BIAS PARAMETERS

I

I

V

VDD

VDD

UVLO

I

VR

Enabled VIN Current Switches Closed, OUTPUT = OPEN 50 75 µA

Disabled VIN Current Switches Open, OUTPUT = OPEN - 2 5 µA

Rising POR Threshold VIN Rising to functional operation 1.7 2.1 2.3 V

Reverse Blocking Leakage Current VIN = 0V, V

= 5V - 2 µA

OUT

Temp_dis Over-Temperature Disable - 150 - °C

Temp_hys Over-Temperature Hysteresis - 20 - °C

NOTE:

8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

8

FN6937.3

March 8, 2012

ISL6185

Introduction

The ISL6185 is a dual channel fully independent overcurrent (OC)
fault protection IC for the +2.5V to +5V environment. Each
ISL6185 incorporates in a single package two 85mΩ P-channel
MOSFET power switches for power control. Independent enabling
inputs and fault reporting outputs compatible with 2.5V to 5V
logic allow for external control and reporting. This device features
integrated power switches with current monitoring, accurate
current limiting, reverse bias protection and current limited
timed delay to turn-off for system reliability. See Figures 13
through 28 for typical operational waveforms including both
under-current and over-current situations.

The ISL6185 offers current sense and limiting, with V
guaranteed continuous current product variants of 0.6A, 1.1A, 1.5A
and 1.8A, making these devices well suited for a myriad of USB and
other low power (9W max) port power management applications
and configurations.

The ISL6185 also provides thermally insensitive timed OC turn-off
and fault notification. This isolates and protects the voltage bus in
the event of a peripheral OC event or short circuit event,
independent of the adjoining switch’s electrical or the ambient
thermal condition.

The ISL6185 undervoltage lockout feature prevents turn-on of
the outputs unless the correct ENABLE state and V
are present. During initial turn-on, the ISL6185 prevents fault
reporting by blanking the fault signal.

During operation, once an OC condition is detected, the output
is current limited for t
pass. If still in current limit after the current limit period has
elapsed, the output is turned off, and the fault is reported by
pulling the corresponding FAULT
options, after turn-off, both the output and the FAULT signal are
latched low until reset by the enable signal being de-asserted or
until a POR occurs. At this time, the FAULT
the switch is ready to be turned back on. On the auto restart
options, the ISL6185 attempts to periodically turn on the
output, as long as the enable is asserted.

When disabled, the ISL6185 has a low quiescent supply current
and an output-to-input reverse current flow blocking capability.

The ISL6185 family is provided with enable polarity options and
an industry-standard 8 lead SOIC pinout, along with two versions
in the 70% smaller 3x3 DFN. The 8 Ld DFN package offers the
same performance as the 8 Ld SOIC, whereas the 10 Ld DFN
offers higher current capability in the smallest possible package
because of lower package electrical and thermal resistance.

to allow transient OC conditions to

CL

output low. On the latch-off

signal clears, and

IN

IN

=5V

> V

UVLO

Functional Description

Power On Preset (POR)

The ISL6185 POR feature inhibits device functionality when
VIN < V

Reverse Polarity Protection

In any event in which the power switch is disabled and
V

OUT>VIN,

the output voltage appear on the input.

Soft-Start

Upon enable, the switch passes a constant current to the load.
The voltage on the VOUT pin ramps up according the equation,
I

LIM/COUT

toward the top of its curve.

Fault Blanking On Start-Up

During initial turn-on, the ISL6185 prevents nuisance faults from
being reported to the system controller by blanking the fault
signal until the internal FET is fully enhanced.

Current Trip and Limiting Levels

The ISL6185 provides integrated current sensing in the MOSFET
that allows for rapid control of OC events. Once an OC condition is
detected, the ISL6185 goes into its current limiting (CL) control
mode. The ISL6185 is variant specified to allow a continuous
current (I
current increases past its continuous current rating, it will reach
a level that causes the device to enter its current limit mode; that
is, the current trip level. The current trip level is in all cases
adequately above the I
false faults. The current limit is specified at V
a known representative condition and is featured at a nominal
value slightly higher than the continuous current rating. The
speed of this current limiting control is inversely related to the
magnitude of the OC fault. Thus, a hard overcurrent is more
quickly pulled to its limiting value than a marginal OC condition.

Over-Temperature Shutdown

Although the ISL6185 has an over-temperature shutdown and
lockout feature, because of the 12ms timed shutdown, the
thermal shutdown is likely to be invoked only in extremely high
ambient temperatures.

The over-temperature protection invokes and disables the switch
turn-on operation once the die temperature is ~+140°C. It turns
off an already on switch at ~+150°C and releases the part to
operation once the die temperature falls to ~+120°C.

.

UVLO

there will be no output-to-input current flow, nor will

(V/s). Resistive or active load slows the V

) operation of 0.6A, 1.1A, 1.5A or 1.8A. As the

CONT

rating so as not to cause unintended

CONT

OUT

= VIN - 1V to test

OUT

ramp-up

9

FN6937.3

March 8, 2012

ISL6185

Turn-off Time Delay

During operation, once an OC condition is detected, the output
is current limited for ~12ms to allow transient OC conditions to
pass. If still in current limit and after the current limit period
has elapsed, the output is turned off, and the fault is reported
by pulling the corresponding FAULT

low. The internal 12ms timer
starts upon current limiting and is independent of ambient or IC
thermal conditions, thus providing more consistent operation
over the entire temperature range.

Typical Performance Curves

150

140

130

120

110

100

90

@ 0.5A (mΩ)

80

70

DS(ON)

r

60

50

-40-25 0 25457585115
TEMPERATURE (°C)

FIGURE 3. SWITCH ON-RESISTANCE AT 0.5A

VIN = 2.5V

V

= 3.3V

IN

VIN = 5V

Latch-off Restart/Auto-Restart Start

After turn-off, with the latch-off options, both the output and the
FAULT signal are latched low until they are reset by the enable
signal being de-asserted. At this time, the FAULT

signal clears,
and the IC is ready for enable to assert. On the auto restart
options, the ISL6185 attempts to periodically turn-on the
output at approximately 1s intervals, as long as the enable is
asserted. If the OC condition remains indefinitely, the fault
indication and the restart attempts also continue until the
thermal protection feature is invoked, thus increasing the
restart period.

Active Output Pull-down

Another ISL6185 feature is the 10kΩ active pull-down on the
outputs to <60mV above GND when the device is disabled, thus
ensuring discharge of the load.

1.3

1.2

1.1

DS(ON)

1.0

0.9

NORMALIZED r

0.8

0.7

-40-25 0 25457585115

FIGURE 4. NORMALIZED SWITCH RESISTANCE

TEMPERATURE (°C)

1.2

5V I

1.1

1.0

0.9

0.8

0.7

0.6

OUTPUT CURRENT (A)

0.5

0.4

TRIP

3.3V I

TRIP

5V I

SC

5V I

LIM

3.3V I

LIM

3.3V I

SC

-40-25 0 25457585115
TEMPERATURE (°C)

FIGURE 5. 0.6A CONTINUOUS CURRENT CHARACTERISTICS

10

1.6

1.5

5V I

TRIP

5V I

3.3V I

SC

SC

3.3V I

TRIP

5V I

LIM

3.3V I

LIM

-40-25 0 25457585115
TEMPERATURE (°C)

OUTPUT CURRENT (A)

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

FIGURE 6. 1.1A CONTINUOUS CURRENT CHARACTERISTICS

FN6937.3

March 8, 2012

ISL6185

Typical Performance Curves (Continued)

2.0

1.8

5V I

TRIP

3.3V I

1.6

1.4

1.2

OUTPUT CURRENT (A)

1.0

0.8

TRIP

3.3V I

LIM

-40-25 0 25457585115

TEMPERATURE (°C)

5V I

LIM

3.3V I

5V I

SC

SC

2.2

5V I

TRIP

3.3V I

TRIP

3.3V I

LIM

-40-25 0 25457585115
TEMPERATURE (°C)

5V I

LIM

OUTPUT CURRENT (A)

2.0

1.8

1.6

1.4

1.2

1.0

3.3V I

5V I

SC

SC

FIGURE 7. 1.5A CONTINUOUS CURRENT CHARACTERISTICS FIGURE 8. 1 .8A CONTINUOUS CURRENT CHARACTERISTICS

0.75

0.70

A
M
G

0.65

I
S

3
±

T

0.60

I
M

I
L

I

0.55

0.6A CONTINUOUS I

VERSION

OUT

+3 SIGMA

TYPICAL

-3 SIGMA

1.25

1.1A CONTINUOUS I

1.20

A
M
G

1.15

I
S

3
±

T

1.10

I
M

I

L

I

1.05

OUT

VERSION

+3 SIGMA

TYPICAL

-3 SIGMA

0.50

-40-25 0 25457585115
TEMPERATURE (°C)

FIGURE 9. LIMITING CURRENT ±3 SIGMA, V

1.65

1.60

A

1.55

M
G

I
S

1.50

3
±

T

I
M

1.45

I
L

I

1.40

1.35

1.5A CONTINUOUS I

-40-25 0 25457585115

TEMPERATURE (°C)

OUT

VERSION

FIGURE 11. LIMITING CURRENT ±3 SIGMA, V

1.00

-40-25 0 25457585115

= 5V FIGURE 10. LIMITING CURRENT ±3 SIGMA, V

IN

+3 SIGMA

TYPICAL

-3 SIGMA

= 5V

IN

2.00

1.95

1.90

A
M

1.85

G

I
S

1.80

3
±

T

I

1.75

M

I
L

I

1.70

1.65

1.60

FIGURE 12. LIMITING CURRENT ±3 SIGMA, V

1.8A CONTINUOUS I

-40-25 0 25457585115

TEMPERATURE (°C)

VERSION

OUT

TEMPERATURE (°C)

= 5V

IN

+3 SIGMA

TYPICAL

-3 SIGMA

= 5V

IN

11

FN6937.3

March 8, 2012

ISL6185

Typical Performance Curves (Continued)

CL=1µF

VOU T

1V/DIV

FIGURE 13. V

V

OUT

1V/DIV

ENABLE

CL= 10µF

TURN-ON/RISE TIME vs C

OUT

R

= 10Ω

L

CL=10µF

CL= 100µF

CL= 100µF

LOAD

. VIN= 5V,

V

OUT

1V/DIV

CL=1µF

FIGURE 14. V

0.6A I

CONT

VARIANT

ENABLE

CL= 10µF

TURN-OFF/FALL TIME

OUT

vs C

. VIN = 5V, RL = 10Ω

LOAD

CL= 100µF

FLT

V

OUT

FIGURE 15. LATCH-OFF vs C

0.6A I

0.53A LOAD CURRENT

CONT

0.08A/ms

IIN 2A/DIV

VARIANT

0.6A/ms

FIGURE 17. OC RAMP RATE I

CL=1µF

LOAD

6A/ms

0.72A CURRENT LIMIT

WAVEFORMS

LIM

FIGURE 16. I

0.6A I

VARIANT

CONT

0.56A LOAD CURRENT

2A OC 27µs

WAVEFORM

LIM

1A OC 57µs

0.66A CURRENT LIMIT

FIGURE 18. PEAK CURRENT SETTLING TIMES

I

IN

0.5A OC 200µs

12

FN6937.3

March 8, 2012

ISL6185

Typical Performance Curves (Continued)

0.6A I

ENABLE

VARIANT

CONT

I

IN

LIMITED TO 0.64A

FIGURE 19. TURN-ON INTO A SHORT

FAULT

V

OUT

V

OUT

FLT

ENABLE

0.6A I

CONT

VARIANT

FIGURE 20. TURN-ON INTO MOMENTARY OC

1.1A I

V

CONT

OUT

VARIANT

FLT

V

I

OUT

FAULT

IN

FIGURE 21. ISL6185 RETRY FUNCTION

ENABLE

FAULT

V

OUT

I

IN

1.8A I

CONT

VARIANT

I

I

IN

ENABLE

FAULT

V

OUT

Iin

IN

FIGURE 22. I

WAVEFORM

LIM

1.8A I

CONT

VARIANT

FIGURE 23. V

= 2.5V TURN-ON INTO 2.2Ω

IN

13

FIGURE 24. V

= 5V TURN-ON INTO 2.7Ω

IN

FN6937.3

March 8, 2012

ISL6185

Typical Performance Curves (Continued)

ENABLE

V

OUT

FAULT

1.8A I

I

IN

LIMITED TO 1.7A

VARIANT

CONT

FIGURE 25. TURN-ON INTO A SHORT

V

OUT

FLT

CH1 and CH2 ON
(3.6A TOTAL I

CH1 ON
(1.8A)

ENABLE

V

OUT

I

IN

FIGURE 26. TURN-ON 2ND OUTPUT TO FULL LOAD

1.1A I

V

CONT

OUT

VARIANT

FLT

)

IN

FAU LT

FIGURE 27. ISL6185 RETRY FUNCTION

Test Circuits

5V

r

DS(ON)

VIN

EN

= V/(VOUT/10W)

FIGURE 29A. r

10k

ISL6185

I

IN

FIGURE 28. ILIM WAVEFORM

FIGURE 28. PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

-

+

V

FLT

OUT

DS(ON)

10µF

OUTPUT

10

5V

VIN

EN

FIGURE 29B. CURRENT LIMITING

FIGURE 29. DC TEST CIRCUIT

I

IN

10k

ISL6185

FLT

OUT

10µF

10

OUTPUT

RL sized
for desired
OC level

R

L

14

FN6937.3

March 8, 2012

Test Circuits (Continued)

10k

ISL6185

EN

0.5VIN

VIN

0.5VIN

0V

FLT

0-V

5V

IN

VIN

EN

ISL6185

OUT

10µF

OUTPUT

10

FIGURE 30. TRANSIENT TEST CIRCUIT FIGURE 31. TRANSIENT WAVEFORM MEASUREMENT POINTS

ISL6185xEVAL1Z Schematic and Photo

R1

10k

AGND

V+

A

NOTE: EXPOSED PAD on DFN packages only

C1

2.2µF

A

AGND

V+

EN1

EN2

A

U1

ISL6185

R2

10k

FLT1
OUT1

OUT2
FLT2

10µF

10µF

R4

10

R3

10
C2

C3

FLT1
OUT1

A

OUT2

A

FLT2

OUTPUT

OUTPUT

t

ON

90%

90% 90%

10% 10%

t

R

t

OFF

10%

VIN

GND

VIN

-GND

t

F

FIGURE 32A. ISL6185xEVAL SCHEMATIC FIGURE 32B. ISL61851EVAL1Z BOARD PHOTO

FIGURE 32. ISL6185xEVAL1Z SCHEMATIC and ISL61851EVAL1Z PHOTOGRAPH

15

March 8, 2012

FN6937.3

ISL6185

Application Information

Using the ISL6185xEVAL1Z Platform
General and Biasing Information

There are three evaluation platforms for the ISL6185 family.
There is one platform for each package style, each with a
different continuous output current level and a mix of enable
polarity and output retry or latch options. See page 4, at the end
of the “Ordering Information” table, for information on the
standard available evaluation board options. Figure 32A shows
the common schematic for all three evaluation boards. See “Pin
Configurations” on page 5 for details and differences.

The evaluation platform is biased and monitored through
numerous labeled test points. See Table 1 for test point
assignments and descriptions.

TABLE 1. ISL61851EVAL1Z TEST POINT ASSIGNMENTS

TP NAME DESCRIPTION

GND Eval Board and IC Gnd

V+ Eval Board and IC Bias

EN1 Enable Switch 1

EN2 Enable Switch 2

FLT2 Switch 2 Fault

OUT2 Switch Out 2

OUT1 Switch Out 1

FLT1 Switch 1 Fault

Upon proper bias of the evaluation platform and correct enabling
of the IC, the ISL6185 will have a nominal V
that is lower than the continuous current rating passing through
each enabled switch. See Figures 13 and 14 for typical ISL6185
turn-on and turn-off waveforms.

External current loading in excess of the trip current level for the
particular part being evaluated will result in the ISL6185 entering
the current limiting mode. Figure 16 illustrates the current
limiting mode for the ISL6185 product variants with 0.6A of
continuous load current rating. The scope shot shows current
limiting for ~12ms before it is turned off and the fault signal is
asserted.

/10Ω load current

IN

Application Considerations

The application considerations for the ISL6185 family are widely
accepted best industry practices. Good decoupling practices on
the VIN pin must be followed: placement close to the IC, with at
least 2.2µF recommended. It is recommended to reduce the
input and output inductance to the ISL6185 with good PCB
layout practices.

When designing with the 1.5A and 1.8A versions in an
implementation in which the output may be unloaded (open)
while the ISL6185 is turned on, a minimum of 4.7µF of
capacitive output load is recommended to prevent high dv/dt
from unnecessarily activating the surge/ESD control circuit.

The ISL6185 provides several continuous current rated devices
specified at V
options that are capable over the entire temperature extreme. At

= 3.3V, the current capability is degraded, and the ISL6185 is

V

IN

specified at 0.6A, 1.1A, 1.3A and 1.5A, respectively. At

= 2.5V, there are no minimum specifications, but a typical

V

IN

value is provided for +25°C operation (see “Electrical
Specifications” on page 6). This degraded capability is due to the
higher r

The enhanced thermal characteristics and increased number of
bond wires allow the 10 Ld DFN to have a higher current
capability than either the 8 Ld SOIC or the DFN.

TABLE 2. ISL6185XEVAL1Z BOARD COMPONENT LISTING

COMPONENT

DESIGNATOR

R3 - R4 Output Load

R1 - R2 FLT Output Pull-up

C2 - C3 Load Capacitor 10µF 16V Electrolytic,

= 5V; these are 0.6A, 1.1A, 1.5A and 1.8A

IN

of the FET switch at the lower bias voltage.

DS(ON)

COMPONENT

FUNCTION COMPONENT DESCRIPTION

U1 ISL6185 Intersil, ISL6185

10Ω, 5%, 3W

Resistors

Resistor

C1 Decoupling

Capacitor

10kΩ, 0805

2.2µF, 0805

Radial Lead

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

in the quality certifications found at www.intersil.com/design/quality

For information regarding Intersil Corporation and its products, see www.intersil.com

16

FN6937.3

March 8, 2012

ISL6185

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.

DATE REVISION CHANGE

March 1, 2012 FN6937.3 In “Features” on page 1 changed from:

UL Recognized, File Number: E333469
(Applies to DFN Packages, SOIC Package to be Qualified Shortly)
to:
UL Recognized, File Number : E333469

In “Absolute Maximum Ratings” on page 6:
Changed from:

Output Current . . . . . . . . . Short Circuit Protected

to:

Output Current . . . . . . . . . .Short Circuit Protected Current Limit of 2.5A

Updated “Package Outline Drawing” on page 20. Changed Note 1 "1982" to "1994".

December 2, 2011 FN6937.2 Page 1: Added "UL Recognized, File Number: E333469 (Applies to DFN packages, SOIC pkg to be qualified

June 14, 2011 FN6937.1 Page 2: “Ordering Information”: added part numbers of parts installed on evaluation boards to Description

October 22, 2010 FN6937.0 Initial release.

shortly)" to "Features"
Page 8: Added Isc_5.5, Short Circuit Current with max of 2.5A to “Electrical Specifications”
Page 19: Updated package outline drawing to most updated revision. Removed package outline and included
center to center distance between lands on recommended land pattern. Removed Note 4 "Dimension b applies
to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is
not applicable to this package. Renumbered notes accordingly.

column.
Page 7: “Electrical Specifications” table:

- For “Maximum Continuous Current, VIN = 2.5V,” changed “ISL61851C,D,G,H (SOIC)” to
“ISL61851C,D,G,H,I,J,K,L (SOIC)”

- For “Trip Current, V
MAX from “2.15” to “2.45”.

- For “Trip Current, VIN = 3.3V” and “Trip Current, VIN = 2.5V” changed “ISL61853I,J,K,L“ to “ISL6185xI,J,K,L“.

- For “Current Limit, VIN = 5V”, “Current Limit, VIN = 3.3V”, and “Current Limit, VIN = 2.5V”, changed
“ISL61853I,J,K,L, VIN - VOUT = 1V” to “ISL6185xI,J,K,L, VIN - VOUT = 1V”

- For “Short Circuit Current, VIN = 5V”, “Short Circuit Current, VIN = 3.3V” and “Short Circuit Current, VIN = 2.5V”
changed “ISL61853I,J,K,L, VOUT = 0V” to “ISL6185xI,J,K,L, VOUT = 0V”
Page 8: “Electrical Specifications” table: For the I/O Parameters Venr_5, Hys_Venr_5, Venr_3, Hys_Venr_3,
Venr_2, and Hys_Venr_2: changed "ENABLE Rising Threshold" and "ENABLE Rising Threshold Hysteresis" to "EN
/ EN

Rising Threshold" and "EN / EN Rising Threshold Hysteresis," for clarity.
Page 8: Electrical Specifications table: Removed UV
Page 20: Replaced Rev. 1 of M8.15 package outline drawing, dated 6/05, with Rev 2 (latest version), dated
11/10.
Applied current Intersil datasheet template to document.

= 5V”, changed “ISL61853I,J,K,L” to “ISL6185xI,J,K,L”. For “ISL61853M.N,O,P” changed

IN

, POR Hysteresis specification.

HYS

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17

for a

FN6937.3

March 8, 2012

Package Outline Drawing

L8.3x3J

8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 0 9/09

3.00

(4X) 0.15

A

B

ISL6185

2X 1.950

6X 0.65

5

8

( 2.80 )

6

PIN 1

INDEX AREA

(1.64)

TOP VIEW

( 2.38 )

( 1.95)

3.00

( 8X 0.60)

8X 0.400 ± 0.10

Max 1.00

4

2.38

+0.10/ - 0.15

BOTTOM VIEW

SIDE VIEW

1.64 +0.10/ - 0.15

0.08

6

C

1

PIN #1 INDEX AREA

8X 0.30

0.10

SEE DETAIL "X"

C

0.10

4

AMC B

C

PIN 1

(6x 0.65)

( 8 X 0.30)

TYPICAL RECOMMENDED LAND PATTERN

18

C

0 . 2 REF

0 . 00 MIN.
0 . 05 MAX.

DETAIL "X"

5

NOTES:

Dimensions are in millimeters.1.
Dimensions in ( ) for Reference Only.

2.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

Dimension applies to the metallized terminal and is measured

4.

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

The configuration of the pin #1 identifier is optional, but must be

6.
located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN6937.3

March 8, 2012

Package Outline Drawing

L10.3x3

10 LEAD DUAL FLAT PACKAGE (DFN)

Rev 7, 10/11

A

B

5

PIN 1

INDEX AREA

(4X) 0.10

3.00

TOP VIEW

ISL6185

3.00

0.23

0.200

2.00

0.415

5

PIN #1 INDEX AREA

1

2

8x 0.50

1.60

BOTTOM VIEW

10 x 0.23

10x 0.35

(4X) 0.10

AB

C

M

(8x 0.50)

(10 x 0.55)

(10x 0.23)

1.60

2.85 TYP

TYPICAL RECOMMENDED LAND PATTERN

0.35

1.00

MAX

0.20

2.00

NOTES:

Dimensions are in millimeters.1.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

2.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

4.

The configuration of the pin #1 identifier is optional, but must be

5.
located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

C

SIDE VIEW

0.20 REF

0.05

DETAIL "X"

4

SEE DETAIL "X"

0.10

C

BASE PLANE

SEATING PLANE

C

0.08

C

19

FN6937.3

March 8, 2012

Package Outline Drawing

M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12

ISL6185

DETAIL "A"

1.27 (0.050)

0.40 (0.016)

INDEX

AREA

123

TOP VIEW

5.00 (0.197)

4.80 (0.189)

1.27 (0.050)

0.51(0.020)

0.33(0.013)

4.00 (0.157)

3.80 (0.150)

SEATING PLANE

1.75 (0.069)

1.35 (0.053)

-C-

6.20 (0.244)

5.80 (0.228)

0.25(0.010)

0.10(0.004)

0.50 (0.20)

0.25 (0.01)

8°
0°

SIDE VIEW “B”

1

2

3

4

5.20(0.205)

x 45°

0.25 (0.010)

0.19 (0.008)

2.20 (0.087)

8

7

6

5

0.60 (0.023)

1.27 (0.050)

SIDE VIEW “A

20

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

5. Terminal numbers are shown for reference only.

6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.

8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.

FN6937.3

March 8, 2012