intersil ISL6173 DATA SHEET

®

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ISL6173

Data Sheet

Dual Low Voltage Hot Swap Controller

This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V. It features a
charge pump for driving external N-Channel MOSFETs,
regulated current protection and duration, output undervoltage
monitoring and reporting, optional latch-off or retry response,
and adjustable soft-start.

The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6173 offers a
latched output or indefinite auto retry mode of operation.

Ordering Information

TEMP.

PART NUMBER

(Note)

ISL6173DRZA ISL6173DRZ 0 to +85 28 Ld 5x5 QFN L28.5x5

ISL6173DRZA-T ISL6173DRZ 0 to +85 28 Ld 5x5 QFN

ISL6173EVAL3 Evaluation Platform

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PAR T

MARKING

RANGE

(°C)

PACKAGE

(Pb-Free)

Tape & Reel

PKG.

DWG. #

L28.5x5

January 3, 2006

FN9186.3

Features

• Fast Current Regulation amplifier quickly responds to
overcurrent fault conditions

• Less than 1µs response Time to Dead Short

• Programmable Current Regulation Level and Duration

• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions

• Overcurrent Circuit Breaker and Fault Isolation functions

• Adjustable Current Regulation Threshold as low as 20mV

• Selectable Latch-off or Auto Retry Response to Fault
conditions

• Adjustable voltage ramp-up for In-rush Protection During
Turn-On

• Rail Independent Control, Monitoring and Reporting I/O

• Dual Supply Hot Swap Power Distribution Control to <1V

• Charge Pump Allows the use of N-Channel MOSFETs

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Power Supply Sequencing, Distribution and Control

• Hot Swap/Electronic Breaker Circuits

Pinout

SNS1

VO1

SS1

GT1

FLT1

PG1

CT1

ISL6173 (28 LD QFN) TOP VIEW

OCREF

CPQ-

EN2

BIAS

VS1

UV1

EN1

28 27 26 25 24 23 22

1

2

3

4

5

6

7

8 9 10 11 12 13 14

GND

PGND

RTR/LTCH

1

UV2

CPQ+

VS2

CPVDD

21

SNS2

20

VO2

19

SS2

GT2

18

17

FLT2

16

PG2

15

CT2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

V1(in)

V2(in)

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Rsns1

Rset1

VS1 SNS1

EN2

EN1
RTR/LTCH
BIAS

CPQ+

CPQ­CPVDD

PGND
GND

CT1 CT2 VS2 SNS2 GT2 VO2

FIGURE 1. TYPICAL APPLICATION

Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved

ISL6173

Rset2

Rsns2

GT1 VO 1

UV1

PG1

FLT1

SS1

OCREF

SS2

FLT2

PG2
UV2

V1(out)

V2(OUT)

Block Diagram

www.BDTIC.com/Intersil

ISL6173

Io

Vin Vo

Limit

WOC

OC

42µA

QRsn s

10V

GT1

24µA

OC Timer

&

Logic

Soft Start
Amplifier

-

+

CPVDD

10µA

VO1

CPV DD

10µA

SS1

Css

FLT1

PG1

Ire f

Rref

OCREF

1. 178V

Cu rren t

Mi rror

I set

Rset

3K

VS1

Iref

SNS1

Cu rren t

Amplifier

-

+

-

+

Co mpar ato r

+

-

4

Co mpar ato r

LOAD

RT R/ LT CH

Cp

Cv

EN1

BI AS

CPQ +

CPQ -

CPV DD

10K

10K

PGND

BI AS

BI AS

Ch arge

Pump

GND

+

-

Timeout
Co mpar ato r

UV

Co mpar ato r

X2

Ch arg e

Pump

POR and
Bandgap

10V(o u t)

X2

633mV

1. 178V

1. 178V

-

633mV

+

ISL6173

CT 1

Ct

Rs1

UV1

Rs2

FIGURE 2. ISL6173 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY

2

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January 3, 2006

Pinout

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SNS1

ISL6173

28 LEAD QFN

TOP VIEW

OCREF

VS1

UV1

EN1

28 27 26 25 24 23 22

1

EN2

UV2

VS2

21

SNS2

CPVDD

20

VO2

19

SS2

GT2

18

17

FLT2

16

PG2

15

CT2

VO1

SS1

GT1

FLT1

PG1

CT1

2

3

4

5

6

7

8 9 10 11 12 13 14

GND

RTR/LTCH

CPQ-

PGND

BIAS

CPQ+

Pin Descriptions

PIN NAME FUNCTION DESCRIPTION

1 SNS1 Current Sense Input This pin is connected to the current sense resistor and control MOSFET Drain node. It provides

2 VO1 Output Voltage 1 This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this

3 SS1 Soft-Start Duration Set

Input

current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.

voltage is used for SS control.

A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.

4 GT1 Gate Drive Output Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to

4 X Vbias or 10V(max) from the 24µA source.

5FLT1

Fault Output This is an open drain output. It asserts (pulls low) once the current regulation duration (determined

by the CTx timeout cap) has expired. This output is valid for Vbias>1V.

6PG1

Power Good Output This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on

UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.

7 CT1 Timer Capacitor A capacitor from this pin to ground controls the current regulation duration from the onset of current

regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches

the GATE output is pulled down and the FLT is asserted.

V

CT_Vth

The duration of current limit time-out = (C

When the OC comparator trips AND the RTR

*1.178)/10µA

TIM

/LTCH pin is pulled low, the IC’s faulty channel remains

shut down for 64 cycles (each cycle length is equal to the current limit time-out duration).

/

8RTR

LTC H

Retry Or Latch Input This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left

floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after
an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for
64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.

9 GND Chip Gnd This pin is also internally shorted to the metal tab at the bottom of the IC.

10 PGND Charge pump ground. Both GND and PGND must be tied together externally.

3

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ISL6173

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Pin Descriptions (Continued)

PIN NAME FUNCTION DESCRIPTION

11 CPQ- Charge Pump Capacitor

Low Side

12 BIAS Chip Bias Voltage Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a

13 CPQ+ Charge Pump Capacitor

14 CPVDD Charge Pump Output This is the voltage used for some internal pullups and bias. Use of 0.47µF (minimum) is

15 CT2 Timer Capacitor Same function as pin 7

16 PG2

17 FLT2

18 GT2 Gate Drive Output Same as pin 4

19 SS2 Soft-Start Duration Set

20 VO2 Output Voltage 2 Same as pin 2

21 SNS2 Current Sense Input Same as pin 1

22 VS2 Current Sense

23 UV2 Undervoltage Monitor

High Side

Power Good Output Same function as pin 6

Fault Output Same as pin 5

Input

Reference

Input

Flying cap lowside.

supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.

Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.

recommended.

Same as pin 3

Voltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.

This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2

is deasserted.

24 EN2

25 OCREF Ref. Current Adj. Allows adjustment of the reference current through R

26 EN1

27 UV1 Undervoltage Monitor

28 VS1 Current Sense

Enable This is an active low input. When asserted (pulled low), the SS and gate drive are released and the

output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.

resistor, thus setting the thresholds for CR, OC and WOC.

Enable Input Same as pin 24

Same as pin 23

Input

Same as pin 22

Reference

and the internal current regulation set

SET

4

FN9186.3

January 3, 2006

ISL6173

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V

GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V

, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,

ENx

SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC

Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1750V

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . 125V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1750V

Operating Conditions

VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . . +2.25V to +3.63V

Temperature Range (T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

1. θ

JA

Tech Brief TB379.

2. All voltages are relative to GND, unless otherwise specified.

3. 1V (min) on the BIAS pin required for FLT

4. For θ

, the “case temp” location is the center of the exposed metal pad on the package underside.

JC

) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C

A

to be valid.

Thermal Resistance (Typical, Notes 1, 4) θ

5x5 QFN Package . . . . . . . . . . . . . . . . 42 12.5

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C

For recommended soldering conditions, see Tech Brief TB389.

(QFN - Leads Only)

(°C/W) θJC (°C/W)

JA

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

CURRENT REGULATION CONTROL

ISET Current I

Partial Temp Range I

Current Limit Amp Offset Voltage Vio_ft V

Partial Temp. Current Limit Amp Offset
Voltage

Current Regulation Threshold Voltage V

Current Regulation Accuracy V

Current Regulation Threshold Voltage V

Current Regulation Accuracy V

Current Regulation Threshold Voltage V

Current Regulation Accuracy V

CT Threshold Voltage V

CT Charging Current I

GATE DRIVE

GATE Response Time from WOC (Open) pd_woc_open GATE open

GATE Response Time from WOC
(Loaded)

GATE Response Time in Current
Regulation mode (Loaded)

GATE Turn-On Current IGATE GATE = 2V, V

Current I

SET

= 2.5V to +3.3V, VS = 1V ,TA = T

DD

SET_ft

SET_pt

Vio_pt V

CRVTH_1

CRVTH_1

CRVTH_2

CRVTH_2

CRVTH_3

CRVTH_3

CT_Vth

CT

pd_woc_load GATE = 1nF 100 ns

pd_cr_load GATE = 1nF

R

R
TJ = 25oC to 60oC

T

RISET = 1.25K, I

R RISET = 1.25K, I

RISET = 2.50K, I

R RISET = 2.50K, I

RISET = 0.499K, I

R RISET = 0.499K, I

100mV of overdrive on the WOC
comparator

120% Load Current

J

= 14.7kΩ 18.7 20 21.3 µA

OCREF

= 14.7kΩ

OCREF

- V

VS

SNS

- V

VS

SNS

= 25°C to 60°C

J

= 0°C - 85°C, Unless Otherwise Specified.

19 20 21 µA

with I

with I

VS

= 0A -2 2 mV

OUT

= 0A

OUT

= 20µA 23 25 27 mV

SET

= 20µA -8 +8 %

SET

= 20µA 48 50 52 mV

SET

= 20µA -4 +4 %

SET

= 20µA 8 10 12 mV

SET

= 20µA -20 +20 %

SET

= 2V, V

= 2.1V 21 24 27 µA

SNS

-1 1 mV

1.128 1.178 1.202 V

10 µA

3ns

5µs

5

FN9186.3

January 3, 2006

ISL6173

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

GATE Voltage V

BIAS

Supply Current I

POR Rising Threshold VIN_POR_L2H 2.12 V

POR Falling Threshold VIN_POR_H2L 2.10 V

POR Threshold Hysteresis VIN_POR_HYS 5 mV

I/O

Undervoltage Comparator Falling
Threshold

Undervoltage Comparator Hysteresis V

EN Rising Threshold PWR_Vth_R V

Falling Threshold PWR_Vth_F V

EN

Hysteresis PWR_HYST V

EN

PG Pull-Down Voltage

Pull-Down Voltage (Note 3)

FLT

Soft-Start Charging Current IQ_SS VSS = 1V 10 µA

CHARGE PUMP

CPVDD V_CPVDD V

CPVDD V_CPVDD V

= 2.5V to +3.3V, VS = 1V ,TA = T

DD

GATE

BIAS

V

UV_VTHF

UV_HYST

VOL_PG

VOL_FLT

Bias = 2.5V (see graph on page 7) 7.5 9.0 V

2.1 < Bias < 2.5
(see graph on page 7)

V

I

PG

I

FLT

T = 25°C
External User Load = 6mA

= 0°C - 85°C, Unless Otherwise Specified. (Continued)

J

8V

= 3.3V 9 17 mA

BIAS

620 635 650 mV

71625mV

= 2.5V 1.55 1.95 2.19 V

BIAS

= 2.5V 0.97 1.10 1.30 V

BIAS

= 2.5V 600 850 1100 mV

BIAS

= 8mA 0.047 0.4 V

= 8mA 0.047 0.4 V

= 3.3V 4.9 5.2 5.5 V

BIAS

BIAS

= 3.3V

5.0 V

6

FN9186.3

January 3, 2006