intersil ISL6144 DATA SHEET

®

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ISL6144

Data Sheet February 15, 2007

High Voltage ORing MOSFET Controller

The ISL6144 ORing MOSFET Controller and a suitably sized
N-Channel power MOSFET(s) increases power distribution
efficiency and availability when replacing a power ORing diode
in high current applications.

In a multiple supply, fault tolerant, redundant power distribution
system, paralleled similar power supplies contribute equally to
the load current through various power sharing schemes.
Regardless of the scheme, a common design practice is to
include discrete ORing power diodes to protect against reverse
current flow should one of the power supplies develop a
catastrophic output short to ground. In addition, reverse current
can occur if the current sharing scheme fails and an individual
power supply voltage falls significantly below the others.

Although the discrete ORing diode solution has been used for
some time and is inexpensive to implement, it has some
drawbacks. The primary downside is the increased power
dissipation loss in the ORing diodes as power requirements for
systems increase. Another disadvantage when using an ORing
diode would be failure to detect a shorted or open ORing diode,
jeopardizing power system reliability . An open diode reduces
the system to single point of failure while a diode short might
pose a hazard to technical personnel servicing the system
while unaware of this failure.

The ISL6144 can be used in 10V to 75V systems having similar
power sources and has an internal charge pump to provide a
floating gate drive for the N-Channel ORing MOSFET . The High
Speed (HS) Comparator protects the common bus from
individual power supply shorts by turning off the shorted feed’s
ORing MOSFET in less than 300ns and ensuring low reverse
current.

An external resistor-programmable detection level for the HS
Comparator allows users to set the N-Channel MOSFET
“V

- VIN” trip point to adjust control sensitivity to power

OUT

supply noise.
The Hysteretic Regulating (HR) Amplifier provides a slow turn-

off of the ORing MOSFET. This turn-off is achieved in less than
100μs when one of the sourcing power supplies is shutdown
slowly for system diagnostics, ensuring zero reverse current.
This slow turn-off mechanism also reacts to output voltage
droop, degradation, or power-down.

An open drain FAUL T
The fault detection circuitry covers different types of failures;
including dead short in the sourcing supply, a short of any two
ORing MOSFET terminals, or a blown fuse in the power
distribution path.

pin will indicate that a fault has occurred.

FN9131.3

Features

• Wide Supply Voltage Range +10V to +75V

• Transient Rating to +100V

• Reverse Current Fault Isolation

• Internal Charge Pump Allows the use of N-Channel
MOSFET

• HS Comparator Provides Very Fast <0.3µs Response
Time to Dead Shorts on Sourcing Supply. HS Comparator
also has Resistor-adjustable Trip Level

• HR Amplifier allows Quiet, <100µs MOSFET Turn-off for
Power Supply Slow Shut Down

• Open Drain, Active Low Fault Output with 120µs Delay

• Provided in Packages Compliant to UL60950 (UL1950)
Creepage Requirements

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• ORing MOSFET Control in Power Distribution Systems

• N + 1 Redundant Distributed Power Systems

• File and Network Servers (12V and 48V)

• Telecom/Datacom Systems

Ordering Information

PART

NUMBER

ISL6144IV* ISL61 44IV -40 to +105 16 Ld TSSOP M16.173
ISL6144IVZA*

(See Note)
ISL6144IR* ISL 6144IR -40 to +105 20 Ld 5x5 QFN L20.5x5
ISL6144IRZA*

(See Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

*Add “-T” suffix for tape and reel.

PART

MARKING

ISL61 44IVZ -40 to +105 16 Ld TSSOP

ISL6144 IRZ -40 to +105 20 Ld 5x5 QFN

TEMP.

RANGE

(°C) PACKAGE

(Pb-Free)

(Pb-Free)

PKG.

DWG. #

M16.173

L20.5x5

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2004, 2006-2007. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ISL6144

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Pinouts

GATE

VIN

HVREF

NC

NC

NC

NC

GND

ISL6144

(16 LD TSSOP)

TOP VIEW

1

2

3

4

5

6

7

8

16

VOUT

15

COMP

1

14

VSET

13

NC

12

NC

11

NC

10

NC

9

FAULT

VIN

HVREF

NC

NC

NC

2

3

4

5

ISL6144

(20 LD 5x5 QFN)

TOP VIEW

NC

20 19 18 17 16

678910

NC

GATE

GND

NC

NC

NC

FAULT

NC

NC

15

VOUT

14

COMP

13

VSET

12

NC

NC

11

Pin Descriptions

TSSOP

PIN #

1 19 GATE External FET Gate Drive Allows active control of extern al N -Chan nel FET ga te to p erform ORing

21
3 2 HVREF Chip High Voltage Reference Low side of floating high voltage reference for all of the HV chip circuitry.

8 7 GND Chip Ground Reference Chip ground reference point.
99FAULT

14 13 VSET Low Side Connection for Trip Level Resistor connected to COMP provides adjustable “Vd-Vs” trip level along

15 14 COMP High Side Connection for HS

16 15 VOUT Chip Bi as and Loa d Co nn ec ti on Provides the second sensing node for external FET control and chip output

4-7,

10-13

QFN

PIN # SYMBOL FUNCTION DESCRIPTION

function.

VIN

Power Supply Connection Chip bias input. Also provides a sensing node for external FET control.

Fault Output Provides an open drain active low output as an indication that a fault has

V

occurred: GATE is OFF (GATE <
resulting in

V

- V

> 0.41V.

OUT

IN

+ 0.37V) or other types of faults

IN

with pin COMP.

provides sense point for the adjustable Vd-Vs

OUT

Comparator Trip Level

Resistor connected to V
trip level along with pin VSET.

bias.

3-6, 8,

NC No Connection

10-12,

16-18, 20

2

FN9131.3

February 15, 2007

General Application Circuit

www.BDTIC.com/Intersil

+

-

ISL6144

LOAD “+48V”

AC/DC

1

AC POWER

AC/DC

N + 1

5V

5V

VIN

ISL6144

HVREF

FAULT

VIN

HVREF

FAULT

GATE

GND

GATE

ISL6144

GND

VOUT

COMP

VSET

VOUT

COMP

VSET

DC/DC

1

+48VDC BUS

DC/DC

N + 1

5V

5V

VIN

HVREF

FAULT

VIN

HVREF

FAULT

GATE

ISL6144

GND

GATE

ISL6144

GND

VOUT

COMP

VSET

LOAD “+12V”

+12VDC BUS

VOUT

COMP

VSET

NOTES:

5. AC/DC 1 through (N + 1) are multistage AC/DC converters which include AC/DC rectification stage and a DC/DC Converter with a +48VDC
output (also might include a Power Factor Correction stage).

6. DC/DC Converter 1 through (N + 1) are DC/DC converters to provide additional Intermediate Bus

7. Load “+12V” and Load “+48V” might include other DC/DC converter stages to provide lower voltages such as ±15V, ±5V, +3.3V, +2.5V,
+1.8V etc.

8. Fuse location might vary depending on power system architecture.

FIGURE 1. ISL6144 GENERAL APPLICATION CIRCUIT IN A DISTRIBUTED POWER SYSTEM

3

FN9131.3

February 15, 2007

Simplified Block Diagram

www.BDTIC.com/Intersil

ISL6144

SOURCE 2
10V TO 75V

SOURCE 1

10V TO 75V

C

C

1

VIN GATE

GATE LOGIC AND

CHARGE PUMP

1

DETECTION

5.5V

LEVEL

SHIFT

2A*

5mA

HVREF

VIN

HVREF

FAULT

FAULT

HS

COMP

D2*

GATE

ISL6144

GND

-

+
REG

AMPLIFIER

-

+

VOUT

COMP

VSET

D1*

F2**

R

1C2

R

2

* D

, D2 PARASITIC DIODES

1

**F1, F2 FUSES COULD ALSO BE PLACED
ON THE INPUT SIDE BEFORE THE VIN PIN. THIS
PLACEMENT DEPENDS ON POWER SYSTEM
ARCHITECTURE.

F1**

VOUT

HIGH

20mV

-

+

VOLTAGE

PASS

AND

CLAMPING

5.3V

0.1mA

COMP

VSET

LOAD

C

R

2

1

R

2

FAULT

1.5mA

GND

DELAY

100µs

4

1.5mA

UV

COMP

-

0.6V

+

BIAS
AND

REF

0.2 mA

FN9131.3

February 15, 2007

ISL6144

www.BDTIC.com/Intersil

Absolute Maximum Ratings T

V

, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +100V

OUT

IN

GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

HVREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V

FAULT

= +25°C Thermal Information

A

Thermal Resistance (Typical, Note 1) θ

+12V

IN

OUT

-5V

IN

OUT

-5V

TSSOP Package (Note 1) . . . . . . . . . . 90 N/A

QFN Package (Notes 3, 4). . . . . . . . . . 35 5

Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(°C/W) θJC (°C/W)

JA

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . +10 to +75V

Temperature Range (T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

+150°C max junction temperature is intended for short periods of time to pr event sho rte ning the lif etime. Opera tio n close to +150° C ju nction ma y t rigger the shu t down of
the device even before +150°C, since this number is specified as typical.

NOTES:

1. θ

is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for

JA

details.)

2. All voltages are relative to GND, unless otherwise specified.

3. For θ

4. θ

, the "case temp" location is the center of the exposed metal pad on the package underside.

JC

is measured in free air with the component mounted on a high effective thermal conductivity test board with “die attach” features. (See Tech

JA

Brief, #TB379 for details.)

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

BIAS “V

POR Rising POR
12V Bias Current I
48V Bias Current I
75V Bias Current I

GATE

Charge Pump Voltage V
Gate Low Voltage Level V
Low Pull Down Current I

High Pull Down Current I

Slow Turn-off Time t
Fast Turn-off Time t

Start-up “Turn-On” Time t
GATE Turn-On Current I

CONTROL AND REGULATION I/O

HR Amplifier Forward Voltage
Regulation

HS COMP Externally
Programmable Threshold

HS Comparator Offset Voltage V

”

IN

) . . . . . . . . . . . . . . . . . . . . -40°C to +105°C

A

= 48V, TA = -40°C to +105°C, Unless Otherwise Specified

IN

L2HVIN
12V
48V
75V

GQP

GL

†

PDL

Rising to V
VIN = 12V, V
VIN = 48V, V
VIN = 75V, V

GATE
GATE
GATE

VIN = 12V to 75V V
VIN - V

< 0V -0.3 V

OUT

Cgs = 39nF, I

(Note 5)

†

PDH

(Note 5)

toffs

toff

ON

ON

(Note 5)

V

FWD_HR

Cgs = 39nF, I

Cgs = 39nF - - 100 µs
Turn-off from V

Cgs = 39nF (includes HS Comparator delay time)
Turn-on from V

†

V

= 10V to 75V - 1 - mA

IN

ISL6144 controls voltage across FET Vds to
V

FWD_HR

during static forward operation at loads

resulting in I * r

†

V

TH(HS)

(Note 5)

OS(HS)

Externally programmable threshold for noise
sensitivity (system dependent), typical 0.05 to 0.3V

> V

GATE

= V

= V

= V

= Cgs * dVgs/T

PDL

= Cgs * dVgs/T

PDH

= V

GATE

= VIN to V

GATE

DS(ON)

+ 7.5V 10 - - V

IN

IN
IN
IN

+ V
+ V
+ V

IN

GQP
GQP
GQP

tofs

toff

+ V

to V

GQP

+ 7.5V into 39nF - 1 - ms

IN

+ 1V with

IN

-3.5-mA

-4.5-mA

-5-mA

IN

+ 9 V

+ 10.5 V

IN

IN

IN

V

IN

-5-mA

-2-A

- 250 300 ns

10 20 30 mV

< V

FWD_HR

0 0.05 5.3 V

-40 0 25 mV

+ 12 V

+ 0.5 V

5

FN9131.3

February 15, 2007

ISL6144

www.BDTIC.com/Intersil

Electrical Specifications V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

COMP Input Current
(bias current)

HVREF Voltage (V
VSET Voltage (V

Low Output Voltage V

Fault
Fault Sink Current I

Leakage Current I

Fault

Delay - Low to High T

Fault

NOTES:

5. The †denotes parameters which are guaranteed by design and not production tested.

6. Specifications to +105°C and -40°C are guaranteed by design and not production tested.

- HVREF) HV

IN

- VSET) V

OUT

Functional Pin Description

GATE

This is the Gate Drive output of the external N-Channel
MOSFET generated by the IC internal charge pump. Gate
turn-on time is typically 1ms.

VIN

Input bias pin connected to the sourcing supply side (ORing

= 48V, TA = -40°C to +105°C, Unless Otherwise Specified (Continued)

IN

I

COMP

REF(VZ)VIN

REF(VSET)VIN

FLT_L

FLT_SINK

FLT_LEAK

FLT

= 10V to 75V - 5.5 - V

= 10V to 75V - 5.3 - V
VIN - V
FAULT = V
FAULT = ”V
GATE = V

OUT

< 0V, V

FLT_L

FLT_H

to FAULT

GL

GATE

, VIN < V

”, VIN > V

= VFLT_L

= V

OUT

OUT

GL

, V

, V

GATE

GATE

FAULT

Open-Drain pull-down F A ULT Output with internal on chip
filtering (

T

down this pin to GND as soon as it detects a fault. Different
types of faults and their detection mechanisms are discussed
in more detail in the Block Diagram Description section.

GND

IC ground reference.

MOSFET Source). Also serves as the sense pin to
determine the sourcing supply voltage. The ORing MOSFET
will be turned off when VIN becomes lower than VOUT by a
value more than the externally set threshold.

VOUT

Connected to the Load side (ORing MOSFET Drain). This is
the VOUT sense pin connected to the load. This is the
common connection point for multiple paralleled supplies.
VOUT is compared to VIN to determine when the ORing
FET has to be turned off.

HVREF

Low side of the internal IC High Voltage Reference used by
internal circuitry, also available as an external pin for
additional external capacitor connection.

COMP

This is the high side connection for the HS Comparator trip
level setting (V
COMP and V
V

OUT

OUT

- VIN trip level (0V to 5V). This provides flexibility to

). Resistor R1, connected between

TH(HS)

along with resistor R2, provides adjustable

externally set the desired level depending on particular
system requirement.

VSET

Low side connection for the HS Comparator trip level setting
A second resistor R
provides adjustable “V

connected between VSET and COMP

2

- V

IN

” level along with R1.

OUT

Detailed Description

The ISL6144 and a suitably sized N-Channel power
MOSFET(s) increases power distribution efficiency and
availability when replacing a power ORing diode in high current
applications. Refer to the Application Consideration section for
power saving when using ISL6144 with an N-channel ORing
MOSFET compared to a typical ORing diode.

Functional Block Description

Regulating Amplifier-Slow (Quiet) Turn-off

A Hysteretic Regulating (HR) Amplifier is used for a
Quiet/ Slow turn-off mechanism. This slow turn-off is initiated
when the sourcing power supply is turned off slowly for
system diagnostics. Under normal operating conditions as
V

pulls up to 20mV below VIN (V

OUT

HR Amplifier regulates the gate voltage to keep the 20mV
(

V

FWD_HR

(Vs - Vd). This will continue until the load current exceeds
the MOSFET ability to deliver the current with Vsd of 20mV.
In this case, Gate will be charged to the full charge pump
voltage (V
the MOSFET will be fully enhanced and behave as a
constant resistor valued at the r
drop below V
output of the HR Amp is pulled high and the gate is pulled
down to V
ORing FET is turned off, avoiding reverse current as well as
voltage and current stresses on supply components.

-1.1-µA

--0.5V

= V

GL

= V

+ V

IN

GQP

). The ISL6144 fault detection circuitry will pull

FLT

4--mA

--10µA

- 120 - µs

- 20mV > V

IN

OUT

), the

) forward voltage drop across the ORing MOSFET

) to fully enhance the MOSFET. At this point,

GQP

. Once VIN starts to

, regulation cannot be maintained and the

OUT

slowly in less than a 100µs. As a result, the

IN

DS(ON)

6

FN9131.3

February 15, 2007

ISL6144

www.BDTIC.com/Intersil

The slow turn-off is achieved in two stages. The first stage
starts with a slow turn-off action and lasts for up to 20µs. The
gate pull down current for the first stage is 2mA. The second
slow turn-off stage completes the gate turn-off with a 10mA
pull down current. The 20µs delay filters out any false trip off
due to noise or glitches that might be present on the supply
line.

The gate turn-on and gate turn-off drivers have a 50kHz filter
to reduce the variation in FET forward voltage drop (and FET
gate voltage) due to normal SMPS system switching noises
(typically higher than 50kHz). These filters do not affect the
total turn-on or slow turn-off times.

Special system design precautions must be taken to insure
that no AC mains related low frequency noise will be present
at the input or output of ISL6144. Filters and multiple power
conversion stages, which are part of any distributed DC
power system, normally filter out all such noise.

HS Comparator-Fast Turn-off

There is a High Speed (HS) Comparator used for fast turn­off of the ORing MOSFET to protect the common bus
against hard short faults at a sourcing power supply output
(refer to Figure 3).

During normal operation the gate of the ORing MOSFET is
charge pumped to a voltage that depends on whether it is in
the 20mV regulation mode or fully enhanced. In this case:

V

OUTVINIOUT

– r

•=

DS(ON)

If a dead short fault occurs in the sourcing supply, it causes
V

to drop very quickly while V

IN

is not affected as more

OUT

than one supply are paralleled. In the absence of the
ISL6144 functionality, a very high reverse current will flow
from Output to the Input supply pulling down the common
DC Bus, resulting in an overall “catastrophic” system failure.

FROM
SOURCING
SUPPLY

VIN

GATE

2A*

DRIVER

VIN

-

+

HS

COMP

V

TH(HS)

HV PASS

AND

CLAMP

5.3V

VOUT

COMP

VSET

BIAS

(EQ. 1)

TO SHARED

LOAD

R

1

R

2

R1 + R2 = 50kΩ

C

The fault can be detected and isolated by using the ISL6144
and an N-Channel ORing MOSFET . V
V

, and whenever:

COMP

VINV

<

V

COMPVOUTVTH

V

TH(HS)

;

where

COMP

–=

is defined below

HS()

is compared to

IN

(EQ. 2)

The fast turn-off mechanism will be activated and the
MOSFET(s) will be turned off very quickly. The speed of this
turn-off depends on the amount of equivalent gate loading
capacitance. For an equivalent Cgs = 39nF . The gate turn-off
time is <300ns and gate pull down current is 2A.

The level of V
by means of external resistors R

(HS Comparator trip level) is adjustable

TH(HS)

and R2 to a value

1

theoretically ranging from 0V to 5.3V. Typical values are

0.05V to 0.3V. This is done in order to avoid false turn-off
due to noise or minor glitches present in the DC switching
power supply. The threshold voltage is calculated as:

R

1

------------------------- -

V

TH HS()

Where V
typical) between V

=

R1R2+()

REF(VSET)

OUT

V

REF VSET()

(EQ. 3)

is an internal zener reference (5.3V

and VSET pins. R1 and R2 must be
chosen such that their sum is about 50kΩ. An external
capacitor, C

, is needed between V

2

and COMP pins to

OUT

provide high frequency decoupling. The HS comparator has
an internal delay time on the order of 50ns, which is part of
the <300ns overall turn-off time specification (with
Cgs = 39nF).

Gate Logic and Charge Pump

The IC has two charge pumps:
The first charge pump generates the floating gate drive for

the N-Channel MOSFET. The second charge pump output
current opposes the pull down current of the slow turn-off
transistor to provide regulation of the GATE voltage.

The presence of the charge pump allows the use of an
N-Channel MOSFET with a floating gate drive. The
N-Channel MOSFETs normally have lower r

DS(ON)

(not to

mention cost saving) compared to P-Channel MOSFETs,

2

allowing further reduction of conduction losses.

BIAS AND REF

Bias currents for the two internal zener supplies (HVREF
and VSET) is provided by this block. This block also
provides a 0.6V band-gap reference used in the UV
detection circuit.

Undervoltage Comparator

FIGURE 2. HS COMPARATOR

7

The undervoltage comparator compares HVREF to 0.6V
internal reference. Once it falls below this level the UV
circuitry pulls and holds down the gate pin as long as the
HVREF UV condition is present. Voltage at both VIN and
HVREF pins track each other.

FN9131.3

February 15, 2007

ISL6144

www.BDTIC.com/Intersil

High Voltage Pass and Clamp

A high voltage pass and clamping circuit prevents the high
output voltage from damaging the comparators in case of
quick drop in V
supply between HVREF and V
for 5V and will be damaged if V

. The comparators are running from the 5V

IN

. These devices are rated

IN

is allowed to be present

OUT

(as the output is powered from other parallel supplies), and
does not fall when V
30V, V

remains at 48V and the differential Voltage

OUT

is falling. For example, if VIN falls to

IN

between the “-” and “+” terminals of the comparator would be
18V, exceeding the rating of the devices and causing
permanent damage to the IC.

Fault Detection Block

The fault detection block has two monitoring circuits (refer to
Figure 4):

1. Gate monitoring detects when the GATE < V

2. V

monitoring detects when V

OUT

- 0.41V > V

IN

These two outputs are ORed, inverted, level shifted, and
delayed using an internal filter (

T

FLT

)

The following failures can be detected by the fault detection
circuitry:

1. ORing FET off due to dead short in the sourcing supply,
leading to V

IN

< V

OUT

2. Shorted terminals of the ORing FET

3. Blown fuse in the power path of the sourcing supply

4. Open Gate terminal

5. HVREF UV

The FAULT

pin is not latched off and the pull down will shut
off as soon as the fault is removed and the pin becomes high
impedance. Typically, an external pull-up resistor is
connected to an external voltage source (for example 5V,

3.3V) to pull the pin high, an LED can be used to indicate the
presence of a fault.

FAULT

DELAY

120µs

LEVEL SHIFT

FIGURE 3. FAULT DETECTION BLOCK

­+

0.37V

+

-

0.41V

+ 0.37V

IN

OUT

+

-

+

-

GATE

VIN

VOUT

Application Considerations

ORing MOSFET Selection

Using an ORing MOSFET instead of an ORing diode results
in increased overall power system efficiency as losses
across the ORing elements are reduced. The use of ORing
MOSFETs becomes more important at higher current levels,
as power loss across the traditionally used ORing diode is
very high. The high power dissipation across these diodes
requires special thermal design precautions such as heat
sinks and forced airflow.

For example, in a 48V, 40A (1+1) redundant system with
current sharing, using a Schottky diode as the ORing
(auctioneering) device (Refer to Figure 5), the forward
voltage drop is in the 0.4V to 0.7V range. Let us assume it is

0.5V, power loss across each diode is:

I

OUT

P

loss D1()Ploss D2()

Total power loss across the two ORing diodes is 20W.

INPUT BUS 1

36VDC TO 75 VDC

CIN1

100µF

INPUT BUS 2
36VDC TO 75 VDC

C

IN2

100µF

FIGURE 4. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORing

C

d1

220nF

C

cs1

1nF

C

d2

220nF

C

cs2

1nF

PRIMARY GROUND

If a 5mΩ single MOSFET per feed is used, the power loss
across each MOSFET is:

P

P

loss

loss

M1()

M1()

P

loss M2()

2

20A()

---------------

VF⋅ 20A 0.5V⋅ 10W====

2

DC/DC

#1

+IN

PC

PR

-IN

DC/DC

#2

+IN

PC

PR

-IN

5mΩ⋅ 2W==

+OUT1 = 48V

+OUT

+S

SC

-S

-OUT

SECONDARY

GROUND

+OUT2 = 48V

+OUT

-OUT

+S

SC

-S

2

I

OUT

⎛⎞

---------------

⎝⎠

2

R

pb1

10

(Note 8)
Figure 15

R

pb2

10

(Note 8)
Figure 15

r

⋅==

DS ON()

(EQ. 4)

D

1

0.5V@ 20A

D

0.5V@ 20A

(EQ. 5)

VOUT

(40A)

2

Total power loss across the two ORing MOSFETs is 4W.
In case of failure of current sharing scheme, or failure of

DC/DC #1, the full load will be supplied by DC/DC #2. ORing

8

FN9131.3

February 15, 2007

ISL6144

www.BDTIC.com/Intersil

MOSFET M2 or ORing Diode D2 will be conducting the full
load current. Power loss across the ORing devices is:

P

loss D

P

loss

2()

M2()

I

⋅ 40A 0.5V⋅ 20W===

OUTVF

2

r

I

()

⋅ 40A()25mΩ⋅ 8W===

OUT

DS ON()

(EQ. 6)

This shows that worst-case failure scenario has to be
accounted for when choosing the ORing MOSFET. In this
case we need to use two MOSFETs in parallel per feed to
reduce overall power dissipation and prevent excessive
temperature rise of any single MOSFET . Another alternative
would be to choose a MOSFET with lower r

DS(ON

).

The final choice of the N-Channel ORing MOSFET depends
on the following aspects:

1. Voltage Rating: The drain-source breakdown voltage
V

has to be higher than the maximum input voltage

DSS

including transients and spikes. Also the gate to source
voltage rating has to be considered, The ISL6144
maximum Gate charge voltage is 12V, make sure the
used MOSFET has a maximum V

rating >12V.

GS

2. Power Losses: In this application the ORing MOSFET is
used as a series pass element, which is normally fully
enhanced at high load currents; switching losses are
negligible. The major losses are conduction losses, which
depend on the value of the on-state resistance of the
MOSFET r

, and the per feed load current. For an

DS(ON)

N + 1 redundant system with perfect current sharing, the
per feed MOSFET losses are:

P

loss FET()

The r

DS(ON)

⎛⎞

-----------------

⎝⎠

N1+

r

⋅=

DS ON()

value also depends on junction temperature;

(EQ. 7)

2

I

LOAD

a curve showing this relationship is usually part of any
MOSFET’s data sheet. The increase in the value of the
r

over temperature has to be taken into account.

DS(ON)

3. Current handling capability, steady state and peak, are
also two important parameters that must be considered.
The limitation on the maximum allowable drain current
comes from limitation on the maximum allowable device
junction temperature. The thermal board design has to be
able to dissipate the resulting heat without exceeding the
MOSFET’s allowable junction temperature.

Another important consideration when choosing the ORing
MOSFET is the forward voltage drop across it. If this drop
approaches the 0.41V limit, which is used in the V

OUT

fault
monitoring mechanism, then this will result in a permanent
fault indication. Normally the voltage drop would be chosen
not to exceed a value around 100mV.

“ISL6144 + ORing FET” vs “ORing Diode” Solution

“ISL6144 + ORing FET” solution is more efficient, which will
result in simplified PCB and thermal design. It will also
eliminate the need for a heat sink for the ORing diode. This
will result in cost savings. In addition, the ISL6144 solution
provides a more flexible, reliable and controllable ORing
functionality and protects against system fault scenarios
(refer to “Fault Detection Block” on page 8).

On the other hand, the most common failures caused by
diode ORing include open circuit and short circuit failures. If
one of these diodes (Feed A) has failed open, then the other
Feed B will provide all of the power demand. The system will
continue to operate without any notification of this failure,
reducing the system to a single point of failure. A much more
dangerous failure is where the diode has failed short. The
system will continue to operate without notification that the
short has occurred. With this failure, transients and failures
on Feed B propagate to Feed A. Also, this silent short failure
could pose a significant safety hazard for technical
personnel servicing these feeds.

“ISL6144 + ORing FET” vs “Discrete ORing FET”
Solution

If we compare the ISL6144 integrated solution to discrete
ORing MOSFET solutions, the ISL6144 wins in all aspects.
The main ones are: PCB real estate saving, cost savings,
and reduction in the MTBF of this section of the circuit as the
overall number of components is reduced.

In brief, the solution offered by this IC enhances power
system performance and protection while not adding any
considerable cost. This solution provides both a PCB board
real estate savings and a simple to implement integrated
solution.

Setting the External HS Comparator Threshold
Voltage

In general, paralleled modules in a redundant power system
have some form of active current sharing, to realize the full
benefit of this scheme, including lower operating
temperatures, lower system failure rate, and better transient
response when load step is shared. Current sharing is
realized using different techniques; all of these techniques
will lead to similar modules operating under similar
conditions in terms of switching frequency, duty cycle, output
voltage and current. When paralleled modules are current
sharing, their individual output ripple will be similar in
amplitude and frequency and the common bus will have the
same ripple as these individual modules and will not cause
any of the turn-off mechanisms to be activated, as the same
ripple will be present on both sensing nodes (V
V

). This would allow setting the high speed comparator

OUT

threshold (V
V

of 50mV could be used, the final value of this TH

TH(HS)

) to a very low value. As a starting point, a

TH(HS)

will be system dependant and has to be finalized in the
system prototype stage. If the gate experiences false turn-off
due to system noise, the V

has to be increased.

TH(HS)

The reverse current peak can be estimated as:

I

reverseP

V

------------------------------------------------------------------------ -

=

++

TH HS()VSDVOS HS()

r

DS ON()

where:
V

is the MOSFET forward voltage drop.

SD

IN

and

(EQ. 8)

9

FN9131.3

February 15, 2007