intersil ISL6142, ISL6152 DATA SHEET

®

www.BDTIC.com/Intersil

ISL6142, ISL6152

Data Sheet July 2004

Negative Voltage Hot Plug Controller

The ISL6142/52 are 14 pin, negative voltage hot plug controllers
that allow a board to be safely inserted and removed from a live
backplane. Inrush current is limited to a programmable value by
controlling the gate voltage of an external N-channel pass
transistor. The pass transistor is turned off if the input voltage is
less than the Under-Voltage threshold, or greater than the Over­Voltage threshold. The PWRGD

/PWRGD outputs can be used to
directly enable a power module. When the Gate and DRAIN
voltages are both considered good the output is latched in the
active state.

The IntelliTrip

TM

electronic circuit breaker and programmable
current limit features protect the system against short circuits.
When the Over-Current threshold is exceeded, the output current
is limited for a time-out period before the circuit breaker trips and
shuts down the FET. The time-out period is programmab le with an
external capacitor connected to the CT pin. If the fault disappears
before the programmed time-out, normal operation resumes. In
addition, the IntelliTrip

TM

electronic circuit breaker has a fast Hard
Fault shutdown, with a threshold set at 4 times the Over-Current
trip point. When activated, the GATE is immediately turned off and
then slowly turned back on for a single retry.

The IS+, IS-, and IS

pins combine to provide a load current

OUT

monitor feature that presents a scaled version of the load current
at the IS
by placing a resistor (R9) from IS

pin. Current to voltage conversion is accomplished

OUT

to the negative input (-48V).

OUT

Related Literature

• ISL6142/52EVAL1 Board Set, Document AN1000

• ISL6140/50EVAL1 Board Set, Document AN9967

• ISL6140/41EVAL1 Board Set, Document AN1020

• ISL6141/51 Hot Plug Controller, Document FN9079

• ISL6141/51 Hot Plug Controller, Document FN9039

• ISL6116 Hot Plug Controller, Document FN4778

NOTE: See www.intersil.com/hotplug for more information.

Pinout

ISL6142 OR ISL6152 (14 LEAD SOIC)

PWRGD

/PWRGD

FAULT

DIS

OV

UV

V

1

Top View

2

3

ISL6142/52

4

5

IS-

6

7

EE

14

V

DD

13

CT

IS

12

OUT

11

DRAIN

10

GATE

9

IS+

8

SENSE

FN9086.1

Typical Application

Logic

Supply

R10

R1 = 0.02Ω (1%)
R2 = 10
R3 = 18K
R4 = 549K
R5 = 6.49KΩ

GND GND

V

DD

ISL6142/ISL6152

IS+

SENSE

R7

R8

R1

Ω

(1%)

Ω

(1%)

Ω

(10%)

-48V IN

Ω

(5%)

Ω

(5%)

Ω

R4

R5

R6

R9

(1%)

(1%)

FAULT

DIS
IS

OUT

UV

OV

V

CT

IS-

EE

C3

R6 = 10KΩ (1%)
R7 = R8 = 400
R9 = 4.99K
R10 = 5.1K
C1 = 150nF (25V)

PWRGD
PWRGD

GATE DRAIN

R3

C1

C2

R2

Q1

C2 = 3.3nF (100V)
C3 = 1500pF (25V)
Q1 = IRF530
CL = 100uF (100V)
RL = Equivalent load

LOAD

CL
RL

-48V OUT

Features

• Operates from -20V to -80V (-100V Absolute Max Rating)

• Programmable Inrush Current

• Programmable Time-Out

• Programmable Current Limit

• Programmable Ov er-Voltage Protection

• Programmable Under-Voltage Protection

- 135 mV of hysteresis ~4.7V of hysteresis at the power supply

•V

Under-Voltage Lock-Out (UVLO) ~ 16.5V

DD

TM

• IntelliTrip
severe and moderate faults

- Fast shutdown for short circuit faults with a single retry (fault

current > 4X current limit value).

•FAULT pin reports the occurrence of an Over-Current Time-Out

• Disable input control s GATE shutdo wn a nd resets Ov e r-Current
fault latch

• Load Current Monitor Function

-IS

- A resistor from IS

conversion

• Power Good Control Output

- Output latched “good” when DRAIN and GATE voltage

thresholds are met.

-(PWRGD

- PWRGD active high: ISL6152 (H version)

• Pb-free available

Electronic Circuit Breaker distinguishes between

provides a scaled version of the load current

OUT

to -VIN provides current to voltage

OUT

active low: ISL6142 (L version)

Applications

• Vo IP (Voice over Internet Protocol) Servers

• Telecom systems at -48V

• Negative Power Supply Control

• +24V Wireless Base Station Power

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil and Design is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002, 2004, All Rights Reserved

Intellitrip™ is a trademark of Intersil Americas Inc.

ISL6142, ISL6152

www.BDTIC.com/Intersil

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

ISL6142CB 0 to 70 14 Lead SOIC M14.15
ISL6142CBZA

(See Note)
ISL6152CB 0 to 70 14 Lead SOIC M14.15
ISL6152CBZA

(See Note)
ISL6142IB -40 to 85 14 Lead SOIC M14.15
ISL6142IBZA

(See Note)
ISL6152IB -40 to 85 14 Lead SOIC M14.15
ISL6152IBZA

(See Note)
*Add “-T” suffix to part number for tape and reel packaging.

NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.

0 to 70 14 Lead SOIC

(Pb-free)

0 to 70 14 Lead SOIC

(Pb-free)

-40 to 85 14 Lead SOIC
(Pb-free)

-40 to 85 14 Lead SOIC
(Pb-free)

DWG. #

M14.15

M14.15

M14.15

M14.15

2

ISL6142, ISL6152 Block Diagram

www.BDTIC.com/Intersil

ISL6142, ISL6152

LOGIC
SUPPLY

LOGIC
INPUT

R10

C3

R4

R5

R6

GND

FAULT

UV

OV

DIS

CT

GND

V

DD

-

1.265V

+

+

V

EE

-

V

1.255V

+

­V

1.255V

+

­V

EE

-

+

EE

+

-

EE

UVLO

REGULATOR,

REFERENCES

UV

13V

OV

LOGIC,

TIMING,

GATE
DRIVE

-

210mV

+

+

­V

EE

-

50mV

+

+

­V

EE

V

EE

13V

V

EE+5V

-

8.5V

+

+

-

V

V

EE

EE

HARD
FAULT

GATE

CURRENT

LIMIT

REGULATOR

FAULT

DISABLE

TIMER

GATE

STOP

11. 1V

+

­V

1.3V

+

­V

8.0V

+

­V

-

+

PWRGD

EE

-

+

EE

-

+

EE

LATCH,
LOGIC,
OUTPUT
DRIVE

(ISL6142)

PWRGD

(ISL6152)

CURRENT

TO ADC

-48V IN

R9

IS

OUT

SENSE

V

IS-

EE

R7

R8

IS+

SENSE

C1

R1

GATE DRAIN

C2

R3

R2

Q1

FIGURE 1. BLOCK DIAGRAM

3

LOAD

CL

RL

-48V OUT

ISL6142, ISL6152

www.BDTIC.com/Intersil

Pin Descriptions

PWRGD (ISL6142; L Version) Pin 1 - This digital output is
an open-drain pull-down de vice and can be used to directly
enable an external module. During start-up the DRAIN and
GATE voltages are monitored with two separate comparators.
The first comparator looks at the DRAIN pin v oltage compared
to the internal V
voltage drop across the exte rnal FET and sense resistor.
When the DRAIN to V
first of two conditions required for the po we r to be considered
good are met. In addition, the GATE voltage monitored b y th e
second comparator must be within approxima tely 2.5V of its
normal operating voltage (13.6V). When both criteria are met
the PWRGD
active state, enabling the external module. When this occurs
the two comparators discussed above no longer control the
output. However a third comparator continues to monitor the
DRAIN voltage, and will driv e the PWR GD
the DRAIN voltage raises more than 8V abo ve V
addition, any of the signals that shut off the GATE (Over­V oltag e , Unde r-Voltage, Under-Voltage Lock-Out, Over­Current time-out, pulling the DIS pin high, or powering down)
will reset the latch and drive the PWRGD
disable the module. In this case, the output pull-down device
shuts off, and the pin becomes high impedance. Typically an
external pull-up of some kind is u sed to pull the pin high (man y
brick regulators have a pul l-up functi on built in).

PWRGD (ISL6152; H Version) Pin 1 - This digital output is
used to provide an active high signal to enable an external
module. The Power Good comparators are the same as
described above, but the active state of the output is
reversed (reference figure 37).

When power is considered good (both DRAIN and GATE are
normal) the output is latched in the active high state, the
DMOS device (Q3) turns on and sinks current to V
a 6.2KΩ resistor. The base of Q2 is clamped to V
off. If the external pull-up current is high enough (>1mA, for
example), the voltage drop across th e resistor will be large
enough to produce a logic high output and enable the e xternal
module (in this example, 1mA x 6.2KΩ = 6.2V).

Note that for all H versions, although this is a digital pin
functionally , the logic high lev el is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the V
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
external clamp might be necessary.

If the power good latch is reset (GA TE turns off), the internal
DMOS device (Q3) is turned off, and Q2 (NPN) turns on to
clamp the output one diode drop above the DRAIN voltage to
produce a logic low, indicating power is no longer good.

reference (1.3V); this measures the

PG

voltage drop is less than 1.3V, the

EE

output will transition low and be latched in the

output inactive if

. In

EE

output high to

through

EE

to turn it

EE

voltage.

DD

FAULT

Pin 2- This digital output is an open-drain, pull-down

device, referenced to V
the Over-Current latch is set. It goes to a high impedance
state when the fault latch is reset by toggling the UV or DIS
pins. An external pull-up resistor to a logic supply (5V or
less) is required; the fault outputs of multiple IC’s can be
wire-OR’d together. If the pin is not used it should be left
open.

DIS Pin 3 - This digital input disables the FET when driven to
a logic high state. It has a weak internal pull-up device to an
internal 5V rail (10µA), so an open pin will also act as a logic
high. The input has a nominal trip point of 1.6 V while rising,
and a hysteresis of 1.0V. The threshold voltage is referenced
to V

, and is compatible with CMOS logic levels. A logic

EE

low will allow the GATE to turn on (assuming the 4 other
conditions described in the GA TE section are also true). The
DIS pin can also be used to reset the Over-Current latch
when toggled high to low. If not used the pin should be tied to
the negative supply rail (-V

OV (Over-Voltage) Pin 4 - This analog input compares the
voltage on the pin to an internal voltage reference of 1.255 V
(nominal). When the input goes above the reference the
GATE pin is immediately pulled low to shut off the external
FET . The built in 25mV hysteresis will k eep the GATE off until
the OV pin drops below 1.230V (the nominal high to low
threshold). A typical application will use an external resistor
divider from V
resistor divider can be used to set both OV and UV trip
points to reduce component count.

UV (Under-Voltage) Pin 5 - This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mv. When the UV input goes be low the
nominal reference voltage of 1.120V, the GATE pin is
immediately pulled low to shut off the external FET. The
GATE will remain off until the UV pin rises above a 1.255V
low to high threshold. A typical application will use an
external resistor divider from V
as desired. A three-resistor divider can be used to set both
OV and UV trip points to reduce component count.

The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above

1.255V (nominal) to clear the latch and initiate a normal
start-up sequence.

IS- Pin 6 - This analog pin is the negative input of the current
sense circuit. A sensing resistor (R7) is connected between
this pin and the V
defines the I
sensing is not used in the application, the IS- pin should be
tied directly to the IS+ pin and the node should be left
floating.

to -VIN to set the OV trip level. A three-

DD

EE

SENSE

. It is pulled active low whenever

EE

).

IN

to -VIN to set the UV level

DD

side of resistor R1. The ratio of R1/R7

to IS

current scaling factor . If current

OUT

4

ISL6142, ISL6152

www.BDTIC.com/Intersil

VEE Pin 7 - This is the most Negative Supply Voltage, such
as in a -48V system. Most of the other signals are referenced
relative to this pin, e ven though it may be far aw a y from wh at
is considered a GND reference.

SENSE Pin 8 - This analog input monitors the voltage drop
across the external sense resistor to determine if the current
flowing through it exceeds the programmed Over-Current trip
point (50mV / Rsense). If the Over-Current threshold is
exceeded, the circuit will regulate the current to maintain a
nominal voltage drop of 50mV across the R1 sense resistor,
also referred to as Rsense. If current is limited for more than
the programmed time-out period the IntelliTrip
circuit breaker will trip and turn off the FET.

A second comparator is employed to detect and respond
quickly to hard faults. The threshold of this comparator is set
approximately four times higher (210mV) than the Over­Current trip point. When the hard fault comparator threshold
is exceeded the GATE is immediately (10µs typical) shut off
(V

= VEE), the timer is reset, and a single retry (soft

GATE

start) is initiated.
IS+ Pin 9 - This analog pin is the positive input of the current

sense circuit. A sensing resistor (R8) is connected between
this pin and the output side of R1, which is also connected to
the SENSE pin. It should match the IS- resistor (R7) as
closely as possible (1%) to minimize output current error
(IS

). If current sensing is not used in the application, the

OUT

IS+ pin should be tied directly to the IS- pin and the node
should be left floating.

GATE Pin 10 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is high
(FET is on) when the following conditions are met:

•V

UVLO is above its trip point (~16.5V)

DD

• V oltage on the UV pin is above its trip point (1.255V)

• V oltage on the OV pin is below its trip point (1.255V)

• No Over-Current conditions are present.

• The Disable pin is low.
If any of the 5 conditions are violated, the GATE pin will be

pulled low to shut off or regulate current through the FET.
The GATE is latched off only when an Over-Current event
exceeds the programmed time-out period.

TM

electronic

1.3v and 8.0V. At initial start-up the DRAIN to V
differential must be less than 1.3V, and the GATE voltage
must be within 2.5V of its normal operating voltage (13.6V)
for power to be considered good. When both conditions are
met, the PWRGD
state. At this point only the 8V DRAIN comparator can
control the PWRGD
if the DRAIN voltage exceeds V

IS

Pin 12 - This analog pin is the output of the current

OUT

sense circuit. The current flowing out of this pin (IS
proportional to the current flowing through the R1 sense
resistor (I
defined by the resistor ratio of R1/R7. Current to voltage
conversion is accomplished by placing a resistor from this
pin to -V
the internal 13V regulator and should not exceed 600µA.
The output voltage will clamp at approximately 8V. If current
sensing is not used in the application the pin should be left
open.

CT Pin 13 - This analog I/O pin is used to program the Over­Current Time-Out period with a capacitor connected to the
negative supply rail (-V
normal operation, the pin is pulled down to V
current limiting, the capacitor is charged with a 20µA
(nominal) current source. When the CT pin charges to 8.5V,
it times out and the GATE is latched off. If the short circuit
goes away prior to the time-out, the GATE will remain on. If
no capacitor is connected, the time-out will be much quicker,
with only the package pin capacitance (~ 5 to 10 pF) to
charge. If no external capacitor is connected to the CT pin
the time-out will occur in a few µsec. To set the desired time­out period use:

dt = (C * dV) / I = (C * 8.5) / 20 µA = 0.425*10

NOTE: The printed circuit board’s parasitic capacitance (CT pin to
the negative input, -V
calculating the value of C3 needed for the desired time-out.

VDD Pin 14 - This is the most positive Power Supply pin. It
can range from the Under-Volta ge lockout threshold (16.5V)
to +80V (Relative to V
without damage to the IC.

SENSE

IN

/PWRGD output is latched into the active

/PWRGD output, and will drive it inactive

by more than 8.0V.

EE

). The scaling factor, IS

. The current flowing out of the pin is supplied by

which is equal to VEE). During

IN

) should be taken into consideration when

IN

). The pin can tolerate up to 100V

EE

OUT/ISENSE

EE

. During

EE

6

* C

voltage

) is

OUT

is

The GATE is driven high by a weak (-50µA nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA (nominal) pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull­down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.

DRAIN Pin 11 - This analog input monitors the voltage of
the FET drain for the P ower Good function. The DRAIN input
is tied to two comparators with internal reference voltages of

5

ISL6142, ISL6152

www.BDTIC.com/Intersil

.

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD to VEE). . . . . . . . . . . . . . . . . . . .-0.3V to 100V

DRAIN, PWRGD

UV, OV Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 60V

SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V

, DIS, IS+, IS-, IS

FAULT
ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . .2000V

, PWRGD Voltage. . . . . . . . . . . . . . .-0.3V to 100V

, CT . . . . . . . . . . . . . . . . . -0.3V to 8.0V

OUT

Thermal Resistance (Typical, Note 1) θ

14 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature (Plastic Package) . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

Operating Conditions

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40oC to 85oC

Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

JA

2. PWRGD is referenced to DRAIN; V

PWRGD-VDRAIN

o

C to 70oC

= 0V.

(oC/W)

JA

o

C to 150oC

o

o

C

C

Electrical Specifications V

PARAMETER SYMBOL
DC PARAMETRIC
V

PIN

DD

Supply Operating Range V
Supply Current I

UVLO High V
UVLO Low V
UVLO hysteresis 1.9 V

GATE PIN

GATE Pin Pull-Up Current I
GATE Pin Pull-Down Current I
GATE Pin Pull-Down Current I
GATE Pin Pull-Down Current I
External Gate Drive (at 20V, at 80V) ∆V
GATE High Threshold (PWRGD

SENSE PIN

Current Limit Trip Voltage V
Hard Fault Trip Voltage HFTV HFTV = (V
SENSE Pin Current I

UV PIN

UV Pin High Threshold Voltage V
UV Pin Low Threshold Voltage V
UV Pin Hysteresis V

= +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

DD

Commercial (0

/PWRGD active) V

o

C to 70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC.

TEST CONDITIONS MIN TYP MAX UNITS

DD

UV = 3V; OV = VEE; SENSE = VEE; VDD =

DD

80V

UVLOHVDD

UVLOLVDD

PU
PD1
PD2
PD3

GATE(VGATE - VEE)

GH

CL

SENSEVSENSE

UVH

UVL

UVHY

Low to High transition 15 16.7 19 V
High to Low transition 13 15.0 17 V

GATE Drive on, V
GATE Drive off, UV or OV false 70 mA
GATE Drive off, Over-Current Time-Out 70 mA
GATE Drive off; Hard Fault, Vsense > 210mv 350 mA

∆V

VCL = (V

UV Low to High Transition 1.240 1.255 1.270 V
UV High to Low Transition 1.105 1.120 1.145 V

- V

GATE

= 50mV - 0 -0.5 µA

GATE = VEE

, 20V <=VDD <=80V 12 13.6 15 V

GATE

- VEE) 405060mV

SENSE

- VEE) 210 mV

SENSE

20 - 80 V

-30 -50 -60 µA

2.6 4.0 mA

2.5 V

135 mV

6

ISL6142, ISL6152

www.BDTIC.com/Intersil

Electrical Specifications V

= +48V, VEE = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

DD

Commercial (0

o

C to 70oC) or Industrial (-40oC to 85oC). Typical specs are at 25oC. (Continued)

PARAMETER SYMBOL

UV Pin Input Current I

OV pin

OV Pin High Threshold Voltage V
OV Pin Low Threshold Voltage V
OV Pin Hysteresis V
OV Pin Input Current I

DRAIN Pin

Power Good Threshold (Enable PWRGD

/PWRGD

Output)
Drain Input Bias Current I
DRAIN Pin Comparator Trip Point

(PWRGD

ISL6142 (PWRGD

PWRGD

/PWRGD Inactive)

Pin: L Version)

Output Low Voltage V

Output Leakage I

ISL6152 (PWRGD Pin: H Version)

INUVVUV

OVH
OVL

OVHY

INOVVOV

V

PG

DRAINVDRAIN

VDH

OL1

V

OL5

OH

= V

OV Low to High Transition 1.235 1.255 1.275 V
OV High to Low Transition 1.215 1.230 1.255 V

= V

V

DRAIN

V

DRAIN

(V

DRAIN

(V

DRAIN

V

DRAIN

TEST CONDITIONS MIN TYP MAX UNITS

EE

- -0.05 -0.5 µA

25 mV

EE

- V

EE

- -0.05 -0.5 µA

0.80 1.30 2.00 V

= 48V 10 38 60 µA

- V

> 8.0V 7.0 8.0V 9.0 V

EE

- V

< V

EE)

- V

< V

EE)

= 48V, V

PG; IOUT
PG; IOUT

PWRGD

= 1mA - 0.3 0.8 V

= 5mA - 1.50 3.0 V

= 80V - 0.05 10 µA

PWRGD Output Low Voltage (PWRGD-DRAIN) V
PWRGD Output Impedance R

OL

OUT

V

DRAIN

(V

DRAIN

= 5V, I

- V

EE)

= 1mA - 0.80 1.0 V

OUT

< V

PG

4.5 6.2 7.5 kΩ
DIS PIN
DIS Pin High Threshold Voltage V
DIS Pin Low Threshold Voltage V
DIS Pin Hysteresis V
DIS Pin Input High Leakage I
DIS Pin Input Low Current I

PIN

FAULT

FAULT

Output Voltage VF
Output Leakage IF

FAULT

DISH

DISHY
DISINH
DISINL

DIS Low to High Transition 1.60 2.20 3.00 V
DIS High to Low Transition 1.1 1.50 V

DISL

DIS Hysteresis 1.0 V
Input Voltage = 5V 0.1 1.0 µA
Input Voltage = 0V 10 µA

I = 1.6 mA 0.4 V

VOL

V = 5.0V 10 µA

IOH

CT PIN

CT Pin Charging Current I
CT Pin Input Threshold V

IS PINS (IS-, IS+, IS

IS

Error VSENSE = 50mV, R7 = 400Ω, R8 = 404Ω 2.0 %

OUT

Error VSENSE = 200mV, R7 = 400Ω, R8 = 404Ω 1.0 %

IS

OUT

OUT

)

CTINLVCT

CT

= 0V 20 µA

7.5 8.5 9.5 V

ISOUT Offset Current VSENSE = 0.0mV, R7 = 400Ω, R8 = 404Ω 4.5 µA
Output Voltage Range (IS

Pin) 058V

OUT

7