intersil ISL6112 DATA SHEET

www.BDTIC.com/Intersil

ISL6112

Data Sheet September 28, 2007

Dual Slot PCI-Express Power Controller

The ISL6112 targets the PCI-Express add-in card hot plug application. Together with two each of N-Channel and P-Channel MOSFETs, four current sense resistors and several external passive components the ISL6112 provides a compliant hot plug power control solution to any combination of two PCI-Express X1, X4, X8 or X16 slots.

The ISL6112 features the ability to program a maximum current regulated level for each of the MAIN outputs for a common programmable duration so that both fault isolation protection and imperviousness to electrical transients (OC and soft-start protection) are provided to each system supply. For each 12VMAIN supply, the curre nt regulated (CR) level is set by a resistor value dependant on the size of the PCI-Express connector (X1, X4/X8 or X16) to be powered. This resistor is a sub ohm standard value current sense resistor one each for each of the 3VMAIN and 12VMAIN supplies. The voltage across this resistor is compared to a 50mV reference providing a nominal CR protection level which would be set above the maximum specified slot limits. The 3.3V supply can use a 15mΩ sense resistor compared to a 50mV reference to provide a nominal regulated current limit of 3.3A to all connector sizes. A shutdown without a CR duration delay is invoked if R voltage is >100mV. The VAUX is internally monitored and controlled to provide nominal limiting to 1A of load current.

The ISL6112 is System Management Interface (SMI) capable with an integrated SMBus link for communication, control, monitoring and reporting of IC and slot conditions. Information such as UV, OC, STATUS, power level etc. are available. Additionally the IC has a minimum of I/O for implementations where Hot-Plug Hardware Interface (HPI) is implemented.

SENSE

FN6456.0

Features

• Supports Two Independent PCI Express Slots

• Highest Available Accuracy External RSENSE Current Monitoring on Main Supplies

• Programmable Current Regulation Pr otect ion F unction for X1, X4, X8, X16 Connectors

• 12V, 3.3V, and 3.3VAUX Supplies Supported per PCI Express Specification V1.0A

• Voltage Tolerant I/O SMBus Interface for Slot Power Control and Status, compatible with SMBus 2.0 Systems

• Programmable Current Regulation D urati on

• Programmable In-rush Current Limiting

• Dual Level Fault Detection for Quick Fault Response without Nuisance Tripping

• Slot to Slot Electrical and Thermal Isolation

• Two General Purpose Input Pins Suitable for Interface to Logic and Switches.

• TQFP or QFN Pb-Free Package Options

- TQFP is pin for pin equivalent to MIC2592B-2YTQ and

is compatible with the TPS2363 pinout

- The QFN package is 40% smaller and has lower die to

case thermal impedance than the TQFP

• Pb-Free (RoHS Compliant)

Applications

• PCI Express V1.0A hot-plug power control

• PCI-Express Servers

• Power Supply Distribution and Control

Ordering Information

PART NUMBER

(Note) PART MARKING TEMP RANGE (°C)

ISL6112IRZA ISL6112 IRZ -40 to +85 48 Ld 7x7 QFN L48.7x7 ISL61 12I RZA-T* ISL6112 IRZ -40 to +85 48 Ld 7x7 QFN Tape and Reel L48.7x7 ISL6112INZA ISL6112 INZ -40 to +85 48 Ld 7x7 TQFP Q48.7x7 ISL6112INZA-T* ISL6112 INZ -40 to +85 48 Ld 7x7 TQFP T ape and Reel Q48.7x7 ISL6112EVAL1Z Evaluation Platform *Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

PACKAGE

(Pb-Free) PKG. DWG. #

Functional Block Diagram (1 Channel)

www.BDTIC.com/Intersil

ISL6112

12VSENSE

12VIN

3VSENSE

3VIN

CFILTER

50mV

100mV*

VSTBY

REF

1.25V

ON AUXEN

ON/OFF

/OFF

12V

UVLO

ON/OFF

POWER-ON

RESET 250µs

UVLO

ON/ OFF

VSTBY

UVLO

LOGIC CIRCUITS

DIGITAL CORE/SERIAL INTERFACE

VSTBY

VAUX CHARGE

PUMP AND

MOSFET

VAUX

OVERCURRENT

THERMAL

SHUTDOWN

VAUX

PWRGD

12VIN

3VIN

12V BIAS

ON/OFF

12VPWRGD

3VPWRGD

10.5V

2.8V

12VGATE

VAUX

3VGATE

PWRGD

FAULT

12VOUT

3VOUT

INT

FORCE

_ON

GPI

BOTH A AND B SLOTS SHARE THE SCL, SDA, A0, A1, A2, INT PINS.

SCL

40kΩ x 3

GND

A0A1A2SDA

FN6456.0

September 28, 2007

Pinouts

www.BDTIC.com/Intersil

(48 LD 7X7 TQFP)

GND

SCL

SDA

ISL6112

TOP VIEW

ONA

AUXENA

ONB

AUXENB

A1A2GPI_B0

INT

FAULTA

CFILTERA

12VGATEA

GPI_A0 12VINA

PWRGD

12VSENSEA

FORCE_ON

12VOUTA

VSTBYA

3VINA

48 47 45 44 42 41

1 2 3

4 5

6 7 8

9 10

11 12

13 17 20

14 15 16 18 19 23 24

GND

VAUXA

3VOUTA

3VGATEA

3VSENSEA

NCNCNC

40 39 3746 43 38

21 22

VAUXB

3VOUTB

FAULT

36 35

CFILTERB

12VGATEB

GND

12VINB

PWRGD

31 30 29 28 27 26 25

3VGATEB

3VSENSEB

12VSENSEB

FORCE_ON

12VOUTB

VSTBYB

3VINB

ISL6112

(48 LD 7X7 QFN)

TOP VIEW

12VGATEA

12VSENSEA

FORCE_ON

FAULT

CFILTERA

GPI_A0 12VINA

PWRGD

12VOUTA

VSTBYA

3VINA

ONB

SCL

GND

SDA

48 47 46 45 44 43 42 41 40 39 38 37

2 3 4 5 6

7 8 9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

3VSENSEA

AUXENA

(EXPOSED BOTTOM PAD)

VAUXA

3VOUTA

3VGATEA

ONA

GND

AUXENB

A1A2GPI_B0

3VOUTB

INT

FAULTB

CFILTERB

12VGATEB

GND

12VINB

PWRGD

12VSENSEB

FORCE_ON

12VOUTB

VSTBYB

3VINB

VAUXB

3VGATEB

3VSENSEB

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Pin Descriptions (Pin Numbers and Names are Related)

PIN NUMBER PIN NAME PIN FUNCTION

5, 32 12VINA, 12VINB Provides 12VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin

connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches from turning on while this input is less than its lockout threshold.

12, 25 3VINA, 3VINB Provides 3.3VMAIN power supply and the high side of the sense resistor inputs. This must be a Kelvin

connection between IC and sense resistor. An undervoltage lockout circuit (UVLO) prevents the switches from turning on while this input is less than its lockout threshold.

16, 21 3VOUTA, 3VOUTB 3.3VOUT. Connected to 3.3V FET source. These are used to monitor the 3.3V output voltages for Power

Good status.

10, 27 12VOUTA,

12VOUTB

8, 29 12VSENSEA,

12VSENSEB

13, 24 3VSENSEA,

3VSENSEB

3, 34 12VGATEA

12VGATEB

14, 23 3VGATEA

3VGATEB

11, 26 VSTBYA, VSTBYB 3.3V Standby Input V oltage: Required to support PCI Express V AUX output. Additionally , the SMBus logic

15, 22 VAUXA, VAUXB 3.3VAUX Output s to PCI Express Card Slots: These outputs connect the 3.3AUX pin of the PCI Express

44, 43 ONA, ONB Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA and MAINB (+3.3V and +12V)

45, 42 AUXENA, AUXENB Level sensitive auxiliary enable Inputs. Used to enable or disable the VAUX outputs. Taking AUXEN low

2, 35 CFILTERA,

CFILTERB

6, 31 PWRGDA

PWRGD

12VOUT. Connected to 12V FET drain. These are used to monitor the 3.3V output voltages for Power Good status.

12VMAIN low side of sense resistor connection. When either current limit threshold of the load current across the sense resistor = 50mV is reached, the related 12VGATE pin is modulated to maintain a constant voltage across the sense resistor and thus a constant current into the load. If the 50mV threshold is exceeded for tFLT, the isolation protection is tripped and the GATE pin for the affected supply’s external MOSFET is immediately pulled high. This must be a Kelvin connection between IC and sense resistor.

3.3VMAIN low side of sense resistor connection. When either current limit threshold of the load current across the sense resistor = 50mV is reached, the related 3V GATE pin is modulated to maintain a constant voltage across the sense resistor and thus a constant current into the load. If the 50mV threshold is exceeded for tFLT, the isolation protection is tripped and the GATE pin for the affected supply’s external MOSFET is immediately pulled low. This must be a Kelvin connection between IC and sense resistor.

12V Gate Drive Outputs: Each pin connects to the gate of an external P-Channel MOSFET. During power-up, the CGATE and the CGS of the MOSFETs are connected to a 25µA current sink. This controls the value of dv/dt seen at the source of the MOSFETs. During current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of tFLT. Whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the GATE pin for the affected slot is immediately brought high. These pins are charged by an internal current source during power-down.

3V Gate Drive Outputs: Each pin connects to the gate of an external N-Channel MOSFET. During powerup, the CGATE and the CGS of the MOSFETs are connected to a 25µA current source. This controls the value of dv/dt seen at the source of the MOSFET s, and hence the current flowing into the load capacitance. During current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of tFLT. Whenever an overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the GATE pin for the af fected slot is immediately brought low . During power-down, these pins are discharged by an internal current source.

and internal registers run off of VSTBY to ensure that the chip is accessible during standby modes. A UVLO circuit prevents turn-on of this supply until VSTBY rises above its UVLO threshold. Both pins must be externally connected together at the ISL6112 controller.

connectors to VSTBY via internal 400mΩ MOSFETs. These outputs are 1A current limited and protected against short-circuit faults.

outputs. Taking ON low after a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie these pins to GND if using SMI power control. Also, see pin description for FAULT

after a fault resets the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also, see pin description for FAULT

Overcurrent Timers: Capacitors connected between these pins and GND set the duration of CR

is the amount of time for which a slot remains in current limit before its isolation protection is

TIM

invoked. Power-is-Good Outputs: Open-drain, active-low. Asserted when a slot has been commanded to turn on

and has successfully begun delivering power to its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external pull-up resistor to V

A and FAULTB.

STBY

A and FAULTB.

TIM

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Pin Descriptions (Pin Numbers and Names are Related) (Continued)

PIN NUMBER PIN NAME PIN FUNCTION

1, 36 FAULTA, FAULTB Fault Outputs: Open-drain, active-low. Asserted whenever the isolation protection trips due to a fault

9, 28 FORCE_ONA

FORCE_ON

4, 38 GPI_A0, GPI_B0 General Purpose Inputs: The states of these two inputs are available by reading the Common Status

39, 40, 41 A2, A1, A0 SMBus Address Select Pins. Connect to ground or leave open in order to program device SMBus base

48 SDA Bidirectional SMBus data line. 47 SCL SMBus Clock Input. 37 INT

17, 33, 46 GND IC Reference pins. Connect together and tie directly to the system’s analog GND plane directly at the

7, 18, 19, 20, 30 NC Reserved: Make no external connections to these pins.

Interrupt Output. Open-drain, active-low. output. Asserted whenever a power fault is detected if the

condition (overcurrent, input undervoltage, over-temperature). Each pin requires an external pull-up resistor to V fault condition on one of the slot’s MAIN outputs (+12V or +3.3V). FAULT AUXEN pin low if FAULT condition occurred on both the MAIN and VAUX output s of the same slot, then both ON and AUXEN must be brought low to de-assert the FAULT

Enable Inputs: Active-low, level-sensitive. Asserting a FORCE_ON

respective slot’s outputs (+12V, +3.3V, and VAUX), while specifically defeating all protections on those supplies. This explicitly includes all overcurrent and short circuit protections, and on-chip thermal protection for the VAUX supplies. Additionally included are the UVLO protections for the +3.3V and +12VMAIN supplies. The FORCE_ON input pins are intended for diagnostic purposes only. Asserting FORCE_ON PWRGD reflect the actual state of each slot’s supplies. There is a pair of register bits, accessible via the SMBus, which can be set to disable (unconditionally de-assert) either or both of the FORCE_ON CNTRL Register Bit D[2].

address. These inputs have internal pull-up resistors to VSTBY. Address programmed on rising VSTBY.

INTMSK bit (CS Register Bit D[3]) is a logical “0”. This output is cleared by performing an “echo reset” to the appropriate fault bit(s) in the STAT and/or CS registers. This pin requires an external pull-up resistor to VSTBY.

device.

. Bringing the slot’s ON pin low resets FAULT if FAULT was asserted in response to a

STBY

was asserted in response to a fault condition on the slot’s VAUX output. If a fault

output.

pins do not disable UVLO protection for the VAUX supplies. These

and FAUL T pins to enter their open-drain state. Note that the SMBus register set will continue to

is reset by bringing the slot’s

input will turn on all three of the

will cause the respective slot’s

pins -- See

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Absolute Maximum Ratings (Note 4) Thermal Information

12VIN, 12VSENSE, 12VOUT . . . . . . . . . . . . . . . . . . . . . . . . +14.5V

VSTBY, 3VIN, 3VSENSE, 3VOUT. . . . . . . . . . . . . . . . . . . . . . . +7V

12VGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI

3VGATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 12VI

Logic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +5.5V

VAUX Output Current . . . . . . . . . . . . . . . . . .Short Circuit Protected

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

1. θ

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

2. θ

Tech Brief TB379.

3. For θ

4. All voltages are relative to GND, unless otherwise specified.

, the “case temp” location is the center of the exposed metal pad on the package underside.

Thermal Resistance (Typical) θ

48 Ld 7x7 TQFP Package (Note 1) . . . 57 N/A

48 Ld 7x7 QFN Package (Notes 2, 3) . 27 3

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

12VMAIN Supply Voltage Range. . . . . . . . . . . . . . . . . +12V ± -10%

3.3VMAIN Supply Voltage Range . . . . . . . . . . . . . . . . +3.3V ± -10%

AUXI Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +3.3V ± -10%

Temperature Range (T

) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

(°C/W) θJC (°C/W)

Electrical Specifications 12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, T

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

POWER CONTROL AND LOGIC SECTIONS

Supply Current ICC12 HPI Enabled or SMI enabled with no load 0.9 1.5 mA

ICC3.3 0.1 0.2 mA

ICCSTBY 5 6 mA

Undervoltage Lockout Thresholds VUVLO(12V) 12VIN increasing 8 9 10 V

VUVLO(3V) 3VIN increasing 2.1 2.5 2.75 V

VUVLO(STBY) VSTBY increasing 2.8 2.9 2.96 V

Undervoltage Lockout Hysteresis 12VIN, 3VIN

Undervoltage Lockout Hysteresis VSTBY

Power-Good Undervoltage Thresholds

Power-Good Detect Hysteresis VHYSPG 30 mV 12VGATE Voltage VGATE (12V) Max. Gate Voltage when Enabled 0 0.4 0.55 V 12VGATE Sink Current IGATE(12VSINK) Start Cycle 17 25 35 µA 12VGATE Pull-up Current (Fault Off) IGATE

3VGATE Voltage VGATE(3V) Minimum Gate Voltage when Enabled 12VIN – 0.3 12VIN – 0.2 12VIN V 3VGATE Charge Current IGATE

3VGATE Sink Current (Fault Off) IGATE(3VSINK) Any fault condition

VHYSUV 180 mV

VHYSSTBY 50 mV

VUVTH(12V) 12VOUT decreasing 10.15 10.5 10.75 V

VUVTH(3V) 3VOUT decreasing 2.7 2.8 2.9 V

VUVTH(VAUX) VAUX decreasing 2.55 2.8 3 V

Any fault condition

(12VPULL-UP)

(3VCHARGE)

(VDD – VGATE) = 2.5V

Start Cycle 17 25 35 µA

VGATE = 2.5V

= TJ = -40°C to +85°C, Unless Otherwise Noted.

35 72 - mA

80 105 mA

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Electrical Specifications 12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, T

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

CFILTER OVERCURRENT DELAY TIME PINS 2 AND 35 FLOATING

CFILTER Threshold Voltage VFILTER 1.20 1.25 1.30 V CFILTER Charging Current

Nominal Current Limit Duration = C

CFILTER

Current Limit Threshold Voltages VTHILIMIT VXIN – VXVSENSE 47.5 50 52.5 mV Fast-Trip Threshold Voltages VTHFAST VXVIN – VXVSENSE 85 100 115 mV XVSENSE Input Current ISENSE 0.1 µA LOW-Level Input Voltage ON,

AUXEN, GPI, FORCE_ON Output LOW Voltage FAULT

PWRGD HIGH-Level Input Voltage ON,

AUXEN, GPI, FORCE_ON Internal Pull-ups to VSTBY (Note 5) RPULL-UP 40 50 kΩ 12VIN, 3VIN Input Leakage Current ILKG,OFF XVIN VSTBY = +3.3V, 12VIN = OFF; 3VIN = OFF 0.5 1 µA Input Leakage Current, ON, AUXEN,

FORCE_ON Off-State Leakage Current FAULT

PWRGD Over-temperature Shutdown and

Reset Thresholds, with Overcurrent On Slot

Over-temperature Shutdown and Reset Thresholds, All Other Conditions (All Outputs Will Latch Off)

Output MOSFET Resistance VAUX MOSFET

Off-St ate Output Offset Voltage V AUX VOFF(V AUX) VAUX = Off 25 40 mV Regulated Current Level ILIM(AUX) 0.8 11.2A Output Discharge Resistance RDIS(12V) 12VOUT = 6.0V 1400 1850 Ω

12V Current Limit Response Time (See “Typical Application Diagram” on page 9).

3.3V Current Limit Response Time (See “Typical Application Diagram” on page 9).

VAUX Current Limit Response Time (See “Typical Application Diagram” on page 9).

Delay from MAIN Overcurrent to FAULT

Delay from VAUX Overcurrent to FAULT

ON, AUXEN, PRSNT Width

Power-On Reset Time after VSTBY Becomes Valid

x 550k

, PRSNT

, GPI

Output

Minimum Pulse

IFILTER VXVIN – VXSENSE > VTHILIMIT 2 2.5 3 µA

tFILTER CFILTER Open 10 µs

VIL 0.8 V

VOL IOL = 3mA 0.4 V

VIH 2.1. 5 V

IIL -2 2 µA

ILKG(OFF) GPI ILKG for these two pins measured with

TOV T

(AUX) IDS = 375mA 350 mΩ

RDIS(3V) 3VOUT = 1.65V 140 180 Ω

RDIS(VAUX) 3VAUX = 1.65V 350 400 Ω

tOFF(12V) CGATE = 25pF

tOFF(3V) CGATE = 25pF

tSC VAUX = 0V, VSTBY = +3.3V 2.5 µs

tPROP

(12V FAUL T or 3V

FAULT)

tPROP

(VAUXFAULT)

tW (Note 5) 100 ns

tPOR (Note 5) 250 µs

VAUX OFF

increasing, each slot (Note 5) 140 °C

decreasing, each slot (Note 5) 130 °C

increasing, each slot (Note 5) 160 °C

decreasing, each slot (Note 5) 150 °C

VIN – VSENSE = 140mV

CFILTER = 0 VIN – VSENSE = 140mV

LIM(AUX)

VAUX Output Grounded

to FAULT output CFILTER = 0

= TJ = -40°C to +85°C, Unless Otherwise Noted. (Continued)

-2 2 µA

1 2.1 µs

0.3 1 µs

1 µs

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Electrical Specifications 12VIN = 12V, 3VIN = 3.3V, VSTBY = 3.3V, T

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

SMBUS TIMING

SCL (clock) period t1 (Note 5) 2.5 µs Data In setup time to SCL HIGH t2 (Note 5) 100 ns Data Out stable after SCL LOW t3 (Note 5) 300 ns Data LOW setup time to SCL LOW t4 (Note 5) 100 ns Data HIGH hold time after SCL HIGH t5 (Note 5) 100 ns

NOTE:

5. Limits established by design and are not production tested.

= TJ = -40°C to +85°C, Unless Otherwise Noted. (Continued)

FN6456.0

September 28, 2007

Typical Application Diagram

www.BDTIC.com/Intersil

ISL6112

FORCE_ONA FORCE_ON

GPI_A0 GPI_B0

SMBUS I/O

100k 100k100k100k

AUXENA AUXENB

HOT-PLUG CONTROLLER

PWRGDA PWRGDB

SMBUS BASE ADDRESS

SYSTEM POWER SUPPLY

ONA ONB

FAULTA FAULTB

10k x 3

SDA

SCL INT

STBY

+12V

+3.3V

VSTBY

STBY

10k x 4

0.1µF

CFILTERA

CFILTERB

FORCE_ON

GPI_A0

GPI_B0

AUXENA

AUXENB

ONA

ONB

PWRGD

FAULT

FAULTB

INT

SCL

SDA

SCL INT

11 26

VSTBYBVSTBYA VAUXA

12VSENSEA

12VGATEA

A B

3VSENSEA

ISL6112

12VSENSEB

12VGATEB

A B

MANAGEMENT

CONTROLLER

3VSENSEB

0.1µF

12VINA

12VOUTA

3VINA

3VGATEA

3VOUTA

12VINB

12VOUTB

3VINB

3VGATEB

3VOUTB

VAUXB

GND GND

GND

PCI-EXPRESS CONNECTOR

0.1µF 5

#CGS

*R12VGATEA

22nF

#CGD

6800pF 10

14 16 #

GATE

22nF

#CGS

22nF

25 24

23 21

22 17 33 46

* Values for R

depending upon the C # These components are not required for ISL6112 operation but can be implemented for GATE output slew rate control (application specific)

• Bold lines indicate high current paths ^ R

15Ω

0.1µF

*R3VGATEA

15Ω

0.1µF

*R12VGATEB

15Ω

CGD

6800pF

0.1µF

*R3VGATEB

15Ω

#CGATE 22nF

12VGATE

value is application specific

SENSE

RSENSE^

0.015Ω

RSENSE^

0.015Ω

PCI-EXPRESS CONNECTOR

and R

may vary

3VGATE

of the external MOSFETs.

PCI EXPRESS BUS

3.3AUX 375mA

12V

2.1A (x4/x8)

3.3V

3.0A

12V

2.1A (x4/x8)

3.3V

3.0A

3.3AUX 375mA

PCI EXPRESS DATA BUS

FN6456.0

September 28, 2007

ISL6112

www.BDTIC.com/Intersil

Functional Description

The ISL6112 protects the power supplies in PCI-Express systems that utilize hot-pluggable add-in cards. This IC together with two each of N-Channel and P-Channel MOSFETs, four current sense resistors and a few external passive components, provide a compliant hot plug power control solution to any combination of two PCI-Express X1, X4, X8 or X16 slots.

The ISL6112 primarily features start-up in-rush current protection, maximum current regulated (CR) levels for each of the MAIN and AUX outputs, programmable CR duration so that both fault isolation protection and imperviousness to electrical transients are provided. The ISL6112 also offers input and output voltage supervisory functions and two operational system interfaces for implementation flexibility.

In-Rush Current Protection

When any electronic circuitry is powered up, there is an in-rush of current due to the charging of bulk capacitance that resides across the circuit board’s supply pins. This transient in-rush current may cause the systems supply voltages to temporarily droop out of regulation, causing data loss or system lock-up. The ISL6112 addresses these iss ues by limiting the in-rush currents to the PCI-Express add-in cards, and thereby controlling the rate at which the loads circuits turn-on. See Figures 2, 3, 4, 5, 6 and 7 for AUX and MAIN turn-on examples illustrating the current limiting capabilities across a variety of compensation component values.

MAIN Supply Overcurrent Protection

For each of the 3VMAIN and 12VMAIN supplies, the current regulated (CR) levels are set by a sub ohm value sense resistor. The value for the 12VMAIN is dependant on the size of the PCI-Express connector (X1, X4/X8 or X16) to be powered. The voltage across this resistor is compared to a 50mV internal reference providing a nominal CR protection level which would be set above the maximum specified slot limits. The 3.3VMAIN supply can use a 15mΩ sense resistor compared to a 50mV reference to provide a nominal regulated current limit of 3.3A, as this supply has a common 3A maximum across all slot sizes. For both MAIN supplies, there is a Way Overcurrent (WOC) shutdown protocol that is without a CR duration. WOC is invoked if the load current causes the RSENSE voltage to be >100mV. See Figures 10 and 11.

VAUX Supply Overcurrent Protection

The VAUX load current is internally monitored and controlled via an internal power FET. This FET has a typical r 320mW at a VAUX current of 375mA to minimize distribution losses to typically <100mV through the IC. Using active monitoring and control, the ISL6112 provides nominal limiting to ~1000mA of load current across the temperature range and for various loading conditions. See Figures 2, 12 and 13 for examples of this performance.

DS(ON)

Current Regulation (CR) Duration

The CR duration for each slot is set by an external capacitor between the associated CFILTER pin and ground. This feature masks current transients and overcurrents prior to supply turn-off. Once the CR duration has expired, the IC then quickly turns-off the associated MAIN outputs via its external FET s or the failed AUX output, unloading the faulted load card from the supply voltage rails.

UVLO, Power Good and FAULT

The ISL6112 incorporates undervoltage lock out (UVLO) protections on each of the four MAIN VIN and two VSTBY supplies to prevent operation during a ‘brown out’ condition. Likewise on the outputs are minimum voltage compliances that must be satisfied for the Power Good output, PWRGD to be asserted. There is some hysteresis on the UVLO levels as the voltage on VIN decreases to ensure IC operation below the minimum operating supply standards. The FAULT output is asserted (low) whenever there is an OC, OT or UV condition. The FAUL T is deasserted.

is cleared once the appropriate enable

Operational System Interfaces

The ISL6112 employs two system interfaces: the hardware Hot-Plug Interface (HPI) and the System Management Interface (SMI). The HPI I/O includes ON, AUXEN, FAULT and PWRGD whose signals conform to the levels and timing of the SMBus specification; see “SMI only Control Applications” on page 17 The ISL6112 can be operated exclusively from either the SMI or HPI, or can employ the HPl for power control while continuing to use the SMI for access to all but the power control registers.

In addition to the basic power control features of the ISL6112 accessible by the HPI, the SMI also gives the host access to the following information from the part:

• Fault conditions occurring on each supply. These faults include Overcurrent, Over-Temperature and undervoltage

• GPI pin status when using the System

When using the System Management Interface for power control, do not use the Hot-Plug Interface. Conversely, when using the Hot-Plug Interface for power control, do not execute power control commands over the System Management Interface bus (all other register accesses via the SMI bus remain permissible while in the HPI control mode). When utilizing the SMI exclusively, the HPI input pins (ON, AUXEN, and FORCE_ON (disabling HPI when SMI control is used). This configuration safeguards the power slots in the event that the SMBus communication link is disconnected for any reason.

Additionally, when utilizing the HPI exclusively, the SMBus (or SMI) will be inactive if the input pins (SDA, SCL, A0, A1, and A2) are configured as shown in Figure 1.

]; the SMI I/O consists of SDA, SCL, and INT,

) should be configured, as shown in Figure 1

FN6456.0

September 28, 2007

+ 21 hidden pages