Intersil Corporation ICM7170 Datasheet

ICM7170

[ /Title
(ICM7

170)
/Sub­ject
(Micro
proces­sor­Com­pati­ble,
Real­Time
Clock)
/Autho
r ()
/Key­words
(Inter­sil
Corpo­ration,
Real
Time
Clock,
Bat­tery
Backu
p,
Inter­nal
Oscil­lator,
Micro­proces­sor
inter­face,
Data

August 1997

Microprocessor-Compatible, Real-Time Clock

Features

• 8-Bit, µP Bus Compatible

- Multiplexed or Direct Addressing

• Regulated Oscillator Supply Ensures Frequency
Stability and Low Power

• Time From 1/100 Seconds to 99 Years

• Software Selectable 12/24 Hour Format

• Latched Time Data Ensures No Roll Over During Read

• Full Calendar with Automatic Leap Year Correction

• On-Chip Battery Backup Switchover Circuit

• Access Time Less than 300ns

• 4 Programmable Crystal Oscillator Frequencies Over
Industrial Temperature Range

• 3 Programmable Crystal Oscillator Frequencies Over
Military Temperature Range

• On-Chip Alarm Comparator and RAM

• Interrupts from Alarm and 6 Selectable Periodic
Intervals

• Standby Micro-Power Operation: 1.2µA Typical at 3.0V
and 32kHz Crystal

Applications

• Portable and Personal Computers

• Data Logging

• Industrial Control Systems

• Point Of Sale

Ordering Information

TEMP. RANGE

PART NUMBER

ICM7170IPG -40 to 85 24 Ld PDIP E24.6
ICM7170IDG -40 to 85 24 Ld SBDIP D24.6
ICM7170IBG -40 to 85 24 Ld SOIC M24.3
ICM7170MDG -55 to 125 24 Ld SBDIP D24.6
ICM7170AIPG -40 to 85 24 Ld PDIP E24.6
ICM7170AIDG -40 to 85 24 Ld SBDIP D24.6
ICM7170AIBG -40 to 85 24 Ld SOIC M24.3
ICM7170AMDG -55 to 125 24 Ld SBDIP D24.6

NOTE: “A” Parts Screened to <5µA I

(oC) PACKAGE

at 32kHz.

STBY

PKG.

NO.

Description

The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil’s silicon gate
CMOS LSl process. An 8-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the 8
internal separately addressable and programmable counters

1

from

/

seconds to years. The counters are controlled by

100

a pulse train divided down from a crystal oscillator circuit,
and the frequency of the crystal is selectable with the on­chip command register. An extremely stable oscillator
frequency is achieved through the use of an on-chip
regulated power supply.

The device access time (t
for wait states or software overhead with most
microprocessors. Furthermore, an ALE (Address Latch
Enable) input is provided for interfacing to microprocessors
with a multiplexed address/data bus. With these two special
features, the ICM7170 can be easily interfaced to any
available microprocessor.

The ICM7170 generates two types of interrupts, periodic and
alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be
programmed by the internal interrupt control register to
provide 6 different output signals. The alarm interrupt is set
by loading an on-chip 51-bit RAM that activates an interrupt
output through a comparator. The alarm interrupt occurs
when the real time counter and alarm RAM time are equal. A
status register is available to indicate the interrupt source.

An on-chip Power Down Detector eliminates the need for
external components to support the battery back-up
function. When a power down or power failure occurs,
internal logic switches the on-chip counters to battery back­up operation. Read/write functions become disabled and
operation is limited to time-keeping and interrupt generation,
resulting in low power consumption.

Internal latches prevent clock roll-over during a read cycle.
Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.

) of 300ns eliminates the need

ACC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

12-5

File Number 3019.3

Pinouts

ICM7170

(PDIP, SBDIP)

TOP VIEW

ICM7170

ICM7170

(SOIC)

TOP VIEW

1

WR

2

ALE

3

CS

4

A4

5

A3

6

A2

7

A1
A0

8

OSC OUT

OSC IN

INT SOURCE

INTERRUPT

9
10
11
12

Functional Block Diagram

24

RD

1

V

BACKUP

WR

ALE

CS

V

DD

V

SS

2
3

23
14
13

µP

CONTROL

POWER
SUPPLY

CONTROL

24

RD

23

V

DD

D7

22

D6

21

D5

20

D4

19
18

D3
D2

17
16

D1

15

D0
V

14

BACKUP

13

VSS (GND)

OSCILLATOR
CRYSTAL

OSC

OSC
OUT

910

IN

LOW

POWER

OSC

0.01 SEC MIN HOUR DAY DATE MON YEAR

PERIODIC

TIME COUNTERS

8-BIT BUS

INTERRUPTS

8

8

OSC OUT

INT SOURCE

V

COMPARE

A1
A0

OSC IN

INT

V

SS

BACKUP

D0
D1
D2
D3

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

THREE-STATE

I/O

DRIVERS

A2
A3
A4
CS
ALE
WR
RD
V

DD

D7
D6
D5
D4

15 - 22

8

12

11

INT

INT
SOURCE

DATA I/O
D0 - D7

ADDRESS

INPUTS

A0 - A4

5

8 - 4

ADDRESS

LATCHES

0.01 SEC MIN HOUR DAY DATE MON YEAR
COMPARE RAM

12-6

CMD
REG

STATUS

REG

INTER
MASK

REG

ICM7170

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Power Dissipation (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to 150oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . 300oC

Input Voltage (Any Terminal) (Note 2) . . . . VDD +0.3V to VSS -0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. TA = 25oC.

2. Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than VDDor less than VSS may cause
destructive device latchup. F or this reason, it is recommended that no inputs from e xternal sources not operating on the same power supply be
applied to the device before its supply is established, and that in m ultiple supply systems , the supply to the ICM7170 be turned on first.

3. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 65 N/A

SBDIP Package. . . . . . . . . . . . . . . . . . 60 18

SOIC Package. . . . . . . . . . . . . . . . . . . 75 N/A

Maximum Junction Temperature

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC

DC Electrical Specifications T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VDD Supply Range, V

Standby Current, I

Standby Current, I

Operating Supply Current, I

Operating Supply Current, I

Input Low Voltage
(Except Osc.), V

Input High Voltage
(Except Osc.), V

Output Low Voltage
(Except Osc.), V

Output High Voltage Except
INTERRUPT
(Except Osc.), V

Input Leakage Current, I
Three-State Leakage Current

(D0 - D7), IOL(1)
Backup Battery Voltage,

V

BATTERY

Backup Battery Voltage,
V

BATTERY

DD

STBY(1)

(2) f

STBY

IL

IH

OL

OH

IL

DD(1)

DD(2)

= -40oC to 85oC, VDD +5V ±10%, V

A

BACKUP VDD

, VSS = 0V Unless Otherwise Specified

All IDD specifications include all input and output leakages (ICM7170 and ICM7170A)

f

= 32kHz 1.9 - 5.5 V

OSC

f

= 1, 2, 4MHz 2.6 - 5.5 V

OSC

f

= 32kHz

OSC

Pins 1 - 8,15 - 22 and 24 = V
VDD = VSS;

V

BACKUP

= VDD - 3.0V

ICM7170 - 1.2 20.0 µA

DD

ICM7170A - 1.2 5.0 µA

For ICM7170A
See General Notes 5

= 4MHz

OSC

Pins 1 - 8,15 - 22 and 24 = V

DD

- 20 150 µA

VDD = VSS;
V

BACKUP

f

OSC

= VDD - 3.0V

= 32kHz

- 0.3 1.2 mA

Read/Write Operation at 100Hz
f

OSC

= 32kHz

- 1.0 2.0 mA

Read/Write Operation at 1MHz
VDD = 5.0V - - 0.8 V

VDD = 5.0V 2.4 - - V

IOL = 1.6mA - - 0.4 V

IOH = -400µA 2.4 - - V

VIN = VDD or V
VO = VDD or V

f

= 1, 2, 4MHz 2.6 - VDD - 1.3 V

OSC

f

= 32kHz 1.9 - VDD - 1.3 V

OSC

SS

SS

-10 0.5 +10 µA

-10 0.5 +10 µA

12-7

ICM7170

DC Electrical Specifications T

= -40oC to 85oC, VDD +5V ±10%, V

A

All IDD specifications include all input and output leakages (ICM7170 and ICM7170A) (Contin-

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Leakage Current INTERRUPT, IOL(2) VO = V

Capacitance D0 - D7, C

I/O

Capacitance A0 - A4,
C

ADDRESS

AC Electrical Specifications T

= -40oC to 85oC, VDD = +5V ± 10%, V

A

D0 - D7 Load Capacitance = 150pF, VIL = 0.4V, VlH = 2.8V, Unless Otherwise Specified

PARAMETER MIN MAX UNITS

READ CYCLE TIMING

READ to DATA Valid, t

ADDRESS Valid to DATA Valid, t

READ Cycle Time, t

Read High Time, t

RD High to Bus Three-State, t

RD

ACC

CYC

RH

RH

DD

BACKUP VDD

INT SOURCE
Connected to V

, VSS = 0V Unless Otherwise Specified

- 0.5 10 µA

SS

-8 - pF

-6 - pF

= VDD,

BACKUP

- 250 ns

- 300 ns

400 - ns

150 - ns

-25ns

ADDRESS to READ Set Up Time, t

ADDRESS HOLD Time After READ, t

WRITE CYCLE TIMING

ADDRESS Valid to WRITE Strobe, t

ADDRESS Hold Time for WRITE, t

WRITE Pulse Width, Low, t

WRITE High Time, t

WH

DATA IN to WRITE Set Up Time, t

DATA IN Hold Time After WRITE, t

WRITE Cycle Time, t

CYC

WA

WL

DW

WD

MULTIPLEXED MODE TIMING

ALE Pulse Width, High, t

ADDRESS to ALE Set Up Time, t

ADDRESS Hold Time After ALE, t

LL

AL

LA

AS

AD

AR

50 - ns

0-ns

50 - ns

0-ns

100 - ns

300 - ns

100 - ns

30 - ns

400 - ns

50 - ns

30 - ns

30 - ns

12-8