Intersil Corporation ICL7134BJIJI, ICL7134BJMJI, ICL7134BKCJI, ICL7134BKIJI, ICL7134BKMJI Datasheet

December 1997

®

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ICL7134

14-Bit Multiplying

Microprocessor-Compatible D/A Converter

Features

• 14-Bit Linearity (0.003% FSR)

• No Gain Adjustment Necessary

• Microprocessor-Compatible with Double Buffered
Inputs

• Bipolar Application Requires No Extra Adjustments or
External Resistors

• Low Linearity and Gain Temperature Coefficients

• Low Power Dissipation

• Full Four-Quadrant Multiplication

• 883B Processed Versions Available

Description

The ICL7134 combines a four-quadrant multiplying DAC
using thin film resistor and CMOS circuitry with an on-chip
PROM-controlled correction circuit to achieve true 14-bit
linearity without laser trimming.

Microprocessor bus interfacing is eased using standard
memory WRITE cycle timing and control signal use. Two
input buffer registers are separately loaded with the 8 least
significant bits (LS register) and the 6 most significant bits
(MS register). Their contents are then transferred to the
14-bit DAC register, which controls the current switches. The
DAC register can also be loaded directly from the data
inputs, in which case the MS and LS registers are
transparent.

The ICL7134 is available in two versions. The ICL7134U is
programmed for unipolar operation while the ICL7134B is
programmed for bipolar applications. The V
most significant bit of the DAC is separated from the
reference input to the remainder of the ladder. For unipolar
use, the two reference inputs are tied together, while for
bipolar operation, the polarity of the MSB reference is
reversed, giving the DAC a true 2’s complement input
transfer function. Two resistors which facilitate the reference
inversion are included on the chip, so only an external
op-amp is needed. The PROM is coded to correct for errors
in these resistors as well as the inversion of the MSB.

input to the

REF

Ordering Information

TEMPERATURE RANGE (oC)

NON-LINEARITY AT 25oC

BIPOLAR VERSIONS

0.01% (12-bit) ICL7134BJCJI ICL7134BJIJI ICL7134BJMJI 28 Ld CERDIP

0.006% (13-bit) ICL7134BKCJI ICL7134BKIJI ICL7134BKMJI 28 Ld CERDIP

0.003% (14-bit) ICL7134BLCJI ICL7134BLIJI ICL7134BLMJI 28 Ld CERDIP

UNIPLAR VERSIONS

0.01% (12-bit) ICL7134UJCJI ICL7134UJIJI ICL7134UJMJI 28 Ld CERDIP

0.006% (13-bit) ICL7134UKCJI ICL7134UKIJI ICL7134UKMJI 28 Ld CERDIP

0.003% (14-bit) ICL7134ULCJI ICL7134ULIJI ICL7134ULMJI 28 Ld CERDIP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

PACKAGE0 to 70 -25 to 85 -55 to 125

File Number 3113.1

Pinout

ICL7134

ICL7134

(OUTLINE DWG JI)

TOP VIEW

Functional Block Diagram

WR

(LSB) D

D

D

CS

D

D

D

D

D

D

D

D

D

1

2

3

0

4

1

5

2

6

3

7

4

8

5

9

6

10

7

11

8

12

9

13

10

14

11

28

27

26

25

24

23

22

21

20

19

18

17

16

15

A

0

A

1

V+

I

OUT

AGND

AGND

DGND

R

FB

V

RFM

R

INV

V

RFL

PROG

(MSB)

D

13

D

12

S

F

2

Pin Descriptions

ICL7134

28 LEAD

CERDIP

PIN

NAME PIN DESCRIPTION

1CS

2WR

3D

4D

5D

6D

7D

8D

9D

10 D

11 D

12 D

13 D

14 D

10

11

Chip Select (active low). Enables register write.

WRITE, (active low). Writes in register. Equivalent to CS.

0

1

2

3

4

5

6

7

8

9

Bit 0 Least Significant

Bit1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Input Data Bits (High = True)

15 D

16 D

12

13

Bit 12

Bit 13 Most significant

17 PROG Used for programming only. Tie to +5V for normal operation.

18 V

19 R

20 V

21 R

RFLVREF

INV

RFM

FB

for lower bits.

Summing node for reference inverting amplifier.

FV

for MSB only (bipolar)

REF

Feedback resistor for voltage output applications.

22 DGND Digital Ground Return.

23 AGND

24 AGND

25 I

Analog Ground force lines. Use to carry current from internal Analog GND connections. Tied internally to AGNDS.

F

Analog Ground sense line. Reference point for external circuitry. Pin should carry minimal current; tied internally to

S

AGND

.

F

Current output pin.

OUT

26 V+ Positive Supply.

27 A

28 A

Address 1 Registers Select Lines

1

Address 0

0

3

ICL7134

Absolute Maximum Ratings (Note 1) Thermal Information

Supply Voltage (V+ to DGND) . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V

V

, V

, R

RFL

RFM

I

, AGNDF, AGNDS . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to V+

OUT

Current in AGND
An, Dn, WR

, RFB to DGND . . . . . . . . . . . . . . . . . . . . . . . . ±15V

INV

, AGNDF . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

S

, CS, PROG. . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Derate Linearly Above 70

o

C @10mW/oC

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300

Operating Conditions

Temperature Range

ICL7134XXC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

ICL7134XXI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25

ICL7134XXM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. All voltages with respect to DGND.

2. Assumes all leads soldered or welded to printed circuit board.

o

C to 70oC

o

C to 85oC

o

C to 125oC

o

C to 150oC

o

C

Electrical Specification V+ = +5V, V

= +10V, TA = 25oC, AGND = DGND, I

REF

at Ground Potential,

OUT

Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution 14 - - Bits

Non-Linearity (Notes 3 and 4) Figure 2 J - - ±0.012 %FSR

K- -±0.006 %FSR

L- -±0.003 %FSR

Non-Linearity Temperature

Operating Temperature Range (Note 5) - ±1 ±2 ppm/

Coefficient

Monotonicity (Note 5) J 12 - - Bits

K13 - - Bits

L14 - - Bits

Gain Error (Notes 3 and 4)

Figure 1

J- -±0.024 %FSR

K- -±0.012 %FSR

L- -±0.006 %FSR

Gain Error Temperature

(Note 5) - ±2 ±8 ppm/

Coefficient

Output Leakage Current
(I

Terminal)

OUT

= 25oC--±10 nA

T

A

Operating Temperature Range - ±60 - nA

o

C

o

C

Long Term Stability of I

OUT

1000 Hours, 125oC, (Note 5) - ±10 - ppm/month

AC ACCURACY

Power Supply Rejection ∆V+ = ±10%, Figure 2, T

= 25oC-±10 ±100 ppm/V

A

Operating Temperature Range - - ±150 ppm/V

Feedthrough Error V

REF

= 20V

, 2kHz U - 250 - µV

P-P

Sinewave, Figure 3 B - 500 - µV

Output Current Setting Time To 1/2 LSB, Figure 4 - 1 - µs

Output Noise Equivalent to Johnson Noise of 7kΩ Resistor, Typical

4

P-P

P-P

ICL7134

Electrical Specification V+ = +5V, V

= +10V, TA = 25oC, AGND = DGND, I

REF

at Ground Potential,

OUT

Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE INPUT

Input Resistance V

RFL

= V

RFM

, I

at Ground 4 7 10 kΩ

OUT

ANALOG OUTPUT

Output Capacitance
(I

Terminal)

OUT

DAC Register Outputs All LOW - 160 - pF

DAC Register Outputs All HIGH - 235 - pF

DIGITAL INPUTS

Low State Threshold Operating Temperature Range - - 0.8 V

High State Threshold 2.4 - - V

Input Current Inputs between DGND to V+ - - ±1 µA

Input Capacitance (Note 5) - 15 - pF

POWER SUPPLY

Supply Voltage Range Functional Operation, (Note 6) 3.5 - 6.0 V

Supply Current Excluding Ladder Network (Note 7) - 1.0 2.5 mA

NOTES:

3. Full-Scale Range (FSR) is 10V for unipolar mode, 20V (±10V) for bipolar mode.

4. Using internal feedback and reference inverting resistors.

5. Guaranteed by design, not production tested.

6. Gain error tested to 0.040% FSR, Specifications are not guaranteed.

7. D0 - D13 connected to 2.4V.

Switching Specifications V+ = 5V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Address-WRITE

Address-WRITE

CHIP SELECT

CHIP SELECT

Pulse Width Low t

WRITE

Data-WRITE

Data-WRITE

Set-Up Time t

Hold Time t

-WRITE Set-Up Time t

-WRITE Hold Time t

Set-Up Time t

Hold Time t

= 25oC, See Timing Diagram

A

AWs

AWh

CWs

CWh

WR

DWs

DWh

Note 5 0 - - ns

Note 5 0 - - ns

Note 5 0 - - ns

Note 5 0 - - ns

150 - - ns

200 - - ns

200 - - ns

5

Test Circuits

ICL7134

FIGURE 1. NON-LINEARITY TEST CIRCUIT

FIGURE 2. POWER SUPPLY REJECTION TEST CIRCUIT

6

Test Circuits (Continued)

ICL7134

FIGURE 3. FEEDTHROUGH ERROR TEST CIRCUIT

Timing Diagrams

FIGURE 4. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT

FIGURE 5A. USING 14-BIT TRANSPARENT ADDRESSING

7

Timing Diagrams

ICL7134

FIGURE 5B. USING FULL BUFFER 8-BIT ADDRESSING CAPABILITY

8

ICL7134

Definition of Terms

Nonlinearity - Error contributed by deviation of the DAC
transfer function from a straight line through the end points of
the actual plot of transfer function. Normally expressed as a
percentage of full scale range or in (sub)multiples of 1 LSB.

Resolution - It is addressing the smallest distinct analog out­put change that a D/A converter can produce. It is commonly
expressed as the number of converter bits. A converter with
resolution of n bits can resolve output changes of 2
full-scale range, e.g. 2

-n

V

for a unipolar conversion. Res-

REF

-n

of the

olution by no means implies linearity.

Settling Time - Time required for the output of a DAC to
settle to within specified error band around its final value
(e.g. 1/2 LSB) for a given digital input change, i.e. all digital
inputs LOW to HIGH and HIGH to LOW.

Gain Error - The difference between actual and ideal analog
output values at full-scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full-scale
range or in (sub)multiples of 1 LSB.

Feedthrough Error - Error caused by capacitive coupling
from V

Output Capacitance - Capacitance from I

REF

to I

with all digital inputs LOW.

OUT

terminal to

OUT

ground.

Output Leakage Current - Current which appears on I

OUT

terminal when all DAC register outputs are LOW.

Detailed Description

The ICL7134 consists of 14-bit primary DAC, two PROM
controlled correction DACs, input buffer registers, and
microprocessor interface logic (See Functional Block
Diagram). The 14-bit primary DAC is an R-2R thin film
resistor ladder with N-channel MOS SPDT current steering
switches. Precise balancing of the switch resistances, and
all other resistances in the ladder, results in excellent
temperature stability.

True 14-bit linearity is achieved by programming a floating poly­silicon gate PROM array which controls two correction DAC cir­cuits. A 6-bit gain correction DAC, or G-DAC, diverts up to 2%
of the feedback resistor’s current to Analog GND and reduces
the gain error to less than 1 LSB, or 0.006%. The 5 most

significant outputs of the DAC register address a 31-word
PROM array that controls a 12-bit linearity correction DAC, or
C-DAC. For every combination of the primary DAC’s 5 most
significant bits, a different C-DAC code is selected. This allows
correction of superposition errors, caused by bit interaction on
the primary resistor ladder’s current output bus and by voltage
non-linearity in the feedback resistor. Superposition errors can­not be corrected by any method which corrects individual bits
only, such as laser trimming. Since the PROM programming
occurs in packaged form, it corrects for resistor shifts caused by
the thermal stresses of packaging. These packaging shifts limit
the accuracy that can be achieved using wafer level correction
methods such as laser trimming, which has also been found to
degrade the time stability of thin film resistors at the 14-bit level.

Analog Section

The ICL7134 inherently provides both unipolar and bipolar
operation. The bipolar application circuit (Figure 6) requires
one additional op-amp but no external resistors. The two on­chip resistors, R

INV1

and R

, together with the op-amp,

INV2

form a voltage inverter which drives the MSG reference ter­minal, V
the less significant bits’ reference terminal, V
values of 1.95R and 2R for the R
absolute value is about 2.5% higher than the V

RFM

, to -V

REF

, where V

is the voltage applied at

REF

INV1

and R

RFL

INV2

. The V

RFL

. Notice the

RFM

. This is
necessary so that the gain error can be corrected. This
reverses the weight of the MSG, and gives the DAC a 2’s
complement transfer function. The op-amp and reference
connection to V

RFM

and V

can be reversed, without

RFL

affecting linearity, but a small gain error will be introduced.
For unipolar operation the V
both tied to V

, and the R

REF

and V

RFM

pin is left unconnected.

INV

terminals are

RFL

Since the PROM correction codes required are different for
bipolar and unipolar operation, the ICL7134 is available in
two different versions; the ICL7134U, which is corrected for
unipolar operation, and the ICL7134B, which is programmed
for bipolar application. The feedback resistance is also differ­ent in the two versions, and is switched under PROM control
from ‘R’ in the unipolar device to ‘2R’ in the bipolar part.
These feedback resistors have a dummy (always ON) switch
in series to compensate for the effect of the ladder switches.
This greatly improves the gain temperature coefficient and
the power supply rejection of the device.

FIGURE 6. BIPOLAR OPERATION WITH INVERTED V

9

REF

TO MSB

ICL7134

Digital Section

Two levels of input buffer registers allow loading of data from
an 8-bit or 16-bit data bus. The A

and A1, pins select one of

0

four operations: 1) load the LS-buffer register with the data
at inputs D
data at inputs D

to D7; 2) load the MS-buffer register with the

0

to D13; 3) load the DAC register with the

8

contents of the MS and LS-buffer registers and 4) load the
DAC register directly from the data input pins (See Table 1).
The CS
occur. When direct loading is selected (CS

and WR pins must be low to allow data transfers to

, WR, A0 and A
low) the registers are transparent, and the data input pins
control the DAC output directly. The other modes of opera­tion allow double buffered loading of the DAC from an 8-bit
bus.

These input data pins are also used to program the PROM
under control of the PROG pin. This is done in manufactur­ing, and for normal operation the PROG pin should be tied to
V+ (+5V).

TABLE 1. DATA LOADING CONTROLS

CONTROL I/P

0A1

X X X 1 No Operation, Device Not Selected.

XX1X

0 0 0 0 Load All Registers from Data Bus.

0 1 0 0 Load LS Register from Data Bus.

1 0 0 0 Load MS Register from Data Bus.

1 1 0 0 Load DAC Register from MS and LS

NOTE: Data is latched on LO-HI transition of either WR

CS WR

ICL7134 OPERATIONA

Register.

or CS.

Applications

GENERAL RECOMMENDATIONS

Grounding

Careful consideration must be given to grounding in any
14-bit accuracy system. The current into the analog ground
point inside the chip varies significantly with the input code
value, and the inevitable resistances between this point and
any external connection pint can lead to significant voltage
drop errors. For this reason, two separate leads are brought
out from this point on the IC, the AGND
The varying current should be absorbed through the AGND
pin, and the AGNDS pin will then accurately reflect the
voltage on the internal current summing point, as shown in
Figure 7. Thus output signals should be referenced to the
sense pin AGND

, as shown in the various application

S

circuits.

Operational Amplifier Selection

To maintain static accuracy, the I
exactly equal to the AGND

potential. Thus output amplifier

S

selection is critical, in particular low input bias current (less
than 2nA), low offset voltage (less than 25µV) are advisable
if the highest accuracy is needed. Maintaining a low input
offset over a 0V to 10V range also requires that the output
amplifier has a high open loop gain (A

and AGNDS pins.

F

potential must be

OUT

> 400k for

VOL

effective input offset less than 25µV).

1

FIGURE 7. GROUND CONNECTIONS

The reference inverting amplifier used in the bipolar mode
circuit must also be selected carefully. If 14-bit accuracy is
desired without adjustment, low input bias current (less than
1nA), low offset voltage (less than 50µV), and high gain
(greater than 400k) are recommended. If a fixed reference
voltage is used, the gain requirement can be relaxed. For
highest accuracy (better than 13-bits), and additional
op-amp may be needed to correct for IR drop on the Analog
GROUND line (op-amp A

in Figure 9). This op-amp should

2

be selected for low bias current (less than 2nA) and low
offset voltage (less than 50µV).

The op-amp requirements can be readily met by use of an
ICL7650 chopper stabilized device. For faster setting time,
an HA26XX can be used with an ICL7650 providing
automatic offset null (see A053 applications note for details)

The output amplifier’s non-inverting input should be tied
directly to AGND

. A bias current compensation resistor is of

S

limited use since the output impedance at the summing node
depends on the code being converted in an unpredictable
way. If gain adjustment is required, low tempco (approxi­mately 50ppm/

o

C) resistors or trim-pots should be selected.

Power Supplies

F

The V+ (pin 25) power supply should have a low noise level,
and no transients exceeding 7 volts. Note that the absolute
maximum for digital input voltage is V+ +0.3V, therefore V+
must be applied before digital inputs are allowed to go high.
Unused digital inputs must be connected to GND or V+ for
proper operation.

Unipolar Binary Operation (ICL7134U)

The circuit configuration for unipolar mode operation
(ICL7134U) is shown in Figure 8. With positive and negative
V

values the circuit is capable of two-quadrant

REF

multiplication. The “digital input code/analog output value”
table for unipolar mode is given in Table 2. The Schottky
diode (HP5082-2811 or equivalent) protects I

OUT

from

10

ICL7134

negative excursions which could damage the device, and is
only necessary with certain high spped amplifiers. For
applications where the output reference ground point is
established somewhere other than at the DAC, the circuit of
Figure 9 can be used. Here, op-amp A

removes the slight

2

error due to IR voltage drop between the internal Analog
GrouND node and the external ground connection. For
13-bit or lower accuracy, omit A
AGND

directly to ground through as low a resistance as

S

and connect AGNDF and

2

possible.

FIGURE 8. UNIPOLAR BINARY, TWO-QUADRANT

MULTIPLYING CIRCUIT

TABLE 2. CODE TABLE - UNIPOLAR BINARY OPERATION

DIGITAL INPUT ANALOG OUTPUT

1 1 1 1 1 1 1 1 1 1 1 1 1 1 -V

1 0 0 0 0 0 0 0 0 0 0 0 0 1 -V

1 0 0 0 0 0 0 0 0 0 0 0 0 0 -V

0 1 1 1 1 1 1 1 1 1 1 1 1 1 -V

0 0 0 0 0 0 0 0 0 0 0 0 0 1 -V

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(1 - 1/214)

REF

(1/2 + 1/214)

REF

/2

REF

(1/2 - 1/214)

REF

(1/214)

REF

Zero Offset Adjustment

1. Connect all data inputs and WR

, CS, A0 and A1 to

DGND.

2. Adjust offset zero-adjust trim-pot of the operational ampli­fier A

, if used, for a maximum of 0V ±50µV at AGNDS.

2

3. Adjust the offset zero-adjust trim-pot of the output
op-amp, A

, for a maximum of 0V ±50µV at V

1

OUT

.

Gain Adjustment (Optional)

1. Connect all data inputs to V+, connect WR

, CS, A0 and A

to DGND.

2. Monitor V

3. To decrease V
between the reference voltage and the V

OUT

for a -V

OUT

(1 - 1/214) reading.

REF

, connect a series resistor of 5Ω or less

RFM

and V

RFL

terminals (pins 20 and 18).

4. To increase V
between A

, connect a series resistor of 5Ω or less

OUT

output and the RFB terminal (pin 21).

1

1

FIGURE 9. UNIPOLAR BINARY OPERATION WITH FORCED

GROUND

Bipolar (2’s Complement) Operation (ICL7134B)

The circuit configuration for bipolar mode operation
(ICL7134B) is shown in Figure 10. Using 2’s complement
digital input codes and positive and negative reference
voltage values, four-quadrant multiplication is obtained. The
“digital input code/analog output value” table for bipolar
mode is given in Table 3. Amplifier A
resistors R

INV1

and R

, forms a simple voltage inverter

INV2

, together with internal

3

circuit. The MSB ladder leg sees a reference input of
approximately -V

, so the MSB’s weight is reversed from

REF

the polarity of the other bits. In addition, the ICL7134B’s
feedback resistance is switched to 2R under PROM control,
so that the bipolar output range is +V

13

1/2

). Again, the grounding arrangement of Figure 9 can be

REF

to -V

REF

(1 -

used if necessary.

TABLE 3. CODE TABLE - BIPOLAR (2’S COMPLEMENT)

0 1 1 1 1 1 1 1 1 1 1 1 1 1 -V

0 0 0 0 0 0 0 0 0 0 0 0 0 1 -V

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 V

1 0 0 0 0 0 0 0 0 0 0 0 0 1 V

1 0 0 0 0 0 0 0 0 0 0 0 0 0 V

OPERATION

DIGITIAL INPUT ANALOG OUTPUT

(1 - 1/213)

REF

(1/213)

REF

(1/213)

REF

(1 - 1/213)

REF

REF

11

ICL7134

FIGURE 10. BIPOLAR (2’S COMPLEMENT), FOUR-QUADRANT MULTIPLYING CIRCUIT

Offset Adjustment

1. Connect all data inputs and WR

, CS, A0 and A1 to

DGND.

2. Adjust the offset zero-adjust trim-pot of the operational
amplifier A
AGND

, if used, for a maximum of 0V ±50µV at

2

.

S

3. Set data to 000000....00. Adjust the offset zero-adjust

trim-pot of any output op-amp A
±50µV at V

4. Connect D

.

OUT

(MSB) data input to V+.

13

5. Adjust the offset zero-adjust trim-pot of op-amp A
maximum of 0V ±50µV at the R

, for a maximum of 0V

1

terminal (pin 19).

INV

for a

3

Gain Adjustment (Optional)

1. Connect WR

2. Connect D

3. Monitor V

4. To increase V
less between the A

5 To decrease V

less between the reference voltage and the V

, CS, A0 and A1 to DGND.

, D1 ... D12 to V+, D13 (MSB) to DGND.

0

OUT

for a -V

OUT

OUT

(1 - 1/213) reading.

REF

, connect a series resistor of 10Ω or

output and the RFB terminal (pin 21).

1

, connect a series resistor of 5Ω or

RFL

termi-

nal (pin 18).

Processor Interfacing

The ease of interfacing to a processor can be seen from
Figure 11, which shows the ICL7134 connected to an 8035
or any other processor such as an 8049. The data bus feeds
into both register inputs; three port lines, in combination with
the WR

line, control the byte-wide loading into these
registers and then the DAC register. A complete DAC set-up
requies 4 write instructions to the port, to set up the address
and CS

lines, and 3 external data transfers, one a dummy

for the final transfer to the DAC register.

A similar arrangement can be used with an 8080A, 8228,
and 8224 chip set. Figure 12 shows the circuit, which can be
arranged as a memory-mapped interface (using MEMW
as an I/O-mapped interface (using I/O WRITE

). See A020

) or

and R005 for discussions of the relative merits of memory­mapped versus I/O-mapped interfacing, as well as some
other ideas on interfacing with 8080 processors. The 8085
processor has a very similar interface, except that the con­trol lines available are slightly different, as shown in Figure

13. The decoding of the IO/M line, which controls memory­mapped or I/O-mapped operation, is arbitrary, and can be
omitted if not necessary. Neither the MC680X nor R650X
processor families offer specific I/O operations. Figure 14
shows a suitable interface to either of these systems, using a
direct connection. Several other decoding options can be
used, depending on the other control signals generated in
the system. Note that the R650X family does not require
VMA to be decoded with the address lines.

12

ICL7134

FIGURE 11. ICL7134 INTERFACE TO 8048 SYSTEM FIGURE 12. INTERFACE TO 8080 SYSTEM

FIGURE 13. 8085 SYSTEM INTERFACE

13

ICL7134

FIGURE 14. R650X AND MC680X FAMILIES’ INTERFACE TO

ICL7134

FIGURE 16. ICL7134 TO 8048/80/85 INTERFACE WITH LOW FEEDTHROUGH

Digital Feedthrough

All of the direct interfaces shown above can suffer from a
capacitive coupling problem. The 14 data pins, and 4 control
pins, all tied to active lines on a microprocessor bus, and in
close proximity to the sensitive DAC circuitry, can couple
pseudo-random spikes into the analog output. Careful board
layout and shielding can minimize the problems (see PC
layout), and clearly wire-wrap type sockets should never be
used. Nevertheless, the inherent capacitance of the package
alone can lead to unacceptable digital feedthrough in many
cases. The only solution is to keep the digital input lines as
inactive as possible. One easy way to do this is to use the
peripheral interface circuitry available with all the systems
previously discussed. These generally allow only 8 bits to be
updated at any one time, but a little ingenuity will avoid diffi­culties with DAC steps that would result from partial updates.
The problem can be solved for the 8048 family by tying the
14 port lines to the data input lines, with CS
low, and using only the WR
DAC (as shown in Figure 15). WR

line to enter the data into the

is well separated from the

, A0 and A1 held

analog lines on the ICL7134, and is usually not a very active
line in 8048 systems. Additional “protection” can be achieved
by gating the processor WR

line with another port line. The
same type of technique can be employed in the 8080/85
systems by using an 8255 PIA (peripheral Interface adaptor)
(Figure 16) and in the MC680X and R650X systems by using

FIGURE 15. AVOIDING DIGITAL FEEDTHROUGH IN AN 8048

TO ICL7134 INTERFACE

an MC6820 (R6520) PIA.

Successive Approximation A/D Converters

Figure 17 shows an ICL7134B-based circuit for a bipolar
input high speed A/D converter, using two AM25LO3s to
form a 14-bit successive approximation register. The
comparator is a two-stage circuit with and HA2605 front-end
amplifier, used to reduce setting time problems at the
summing node (see A020). Careful offset-nulling of this
amplifier is needed, and if wide temperature range operation
is desired, and auto-null circuit using an ICL7650 is probably
advisable (see A053). The clock, using two Schmitt trigger
TTL gates, runs at a slower rate for the first 8 bits, where
setting-time is most critical, than for the last 6 bits. The short­cycle line is shown tied to the 15th bit; if fewer bits are
required, it can be moved up accordingly. The circuit will
free-run if the HOLD/RUN

input is held low, but will stop after
completing a conversion if the pin is high at that time. A low­going pulse will restart it. The STATUS output indicates
when the device is operating, and the falling edge indicates
the availability of new data. A unipolar version may be con­structed by tying the MSB (D

) on an ICL7134U to pin 14

13

on the first AM25L03, deleting the reference inversion
amplifier A

, and tying V

4

RFM

and V

RFL

.

14

ICL7134

FIGURE 17. SUCCESSIVE APPROXIMATION A/D CONVERTER

15

FIGURE 18A. PRONTED CIRCUIT SIDE OF CARD (SINGLE

SIDED BOARD)

FIGURE 18. PRINTED CIRCUIT BOARD LAYOUT (BIPOLAR CIRCUIT, SEE FIGURE 10)

FIGURE 18B. TOP SIDE WITH COMPONENT PLACEMENT

PC Board Layout

Great care should be taken in the board layout to minimize
ground loop and similar “hidden resistor” problems, as well
as to minimize digital signal feedthrough. A suitable layout
for the immediate vicinity of the ICL7134 is shown in Figure
18, and may be used as a guide.

Application Notes

Some applications bulletins that may be found useful are listed here:

A002 “Principles of Data Acquisition and Conversion”

A018 “Do’s and Don’ts of Applying A/D Converters”, by

Peter Bradshaw and Skip Osgood.

A020 “A Cookbook Approach to High Speed Data

Acquisition and Microprocessor Interfacing,”, by Ed
Sliger.

A042 “Interpretation of Data Converters Accuracy

Specifications”

R005 “Interfacing Data Converters & Microprocessor”, by

Peter Bradshaw et al., Electronics, Dec 9, 1976.

Most of these are avilable in the Intersil Data Acquisition Handbook, together with other material.

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