Intersil Corporation ICL7116, ICL7117 Datasheet

January 1998

ICL7116, ICL7117

31/2 Digit, LCD/LED Display,

A/D Converter with Display Hold

Features

• HOLD Reading Input Allows Indefinite Display Hold

• Guaranteed Zero Reading for 0V Input

• True Polarity at Zero for Precise Null Detection

• 1pA Typical Input Current

• Direct Display Drive

- LCD ICL7116

- LED lCL7117

• Low Noise - Less Than 15µV

P-P

(Typ)

• On Chip Clock and Reference

• Low Power Dissipation - Typically Less Than 10mW

• No Additional Active Circuits Required

• Surface Mount Package Available

Ordering Information

TEMP.

PART NUMBER

ICL7116CPL 0 to 70 40 Ld PDIP E40.6
ICL7116CM44 0 to 70 44 Ld MQFP Q44.10x10
ICL7117CPL 0 to 70 40 Ld PDIP E40.6

RANGE (oC) PACKAGE PKG. NO.

Description

The Intersil ICL7116 and ICL7117 are high performance, low
power, 3
decoders, display drivers, a reference, and a clock. The
ICL7116 is designed to interface with a liquid crystal display
(LCD) and includes a multiplexed backplane drive. The
ICL7117 will directly drive an instrument size, light emitting
diode (LED) display.

The ICL7116 and ICL7117 have all of the features of the
ICL7106 and ICL7107 with the addition of a HOLD Reading
input. With this input, it is possible to make a measurement
and retain the value on the display indefinitely. To make room
for this feature the reference low input has been connected
to Common internally rather than being fully differential.
These circuits retain the accuracy, versatility, and true econ­omy of the ICL7106 and ICL7107. They feature auto-zero to
less than 10µV, zero drift of less than 1µV/
rent of 10pA maximum, and roll over error of less than one
count. The versatility of true differential input is of particular
advantage when measuring load cells, strain gauges and
other bridge-type transducers. And finally, the true economy
of single power supply operation (ICL7116) enables a high
performance panel meter to be built with the addition of only
eleven passive components and a display.

1

/2 digit, A/D converters. Included are seven segment

o

C, input bias cur-

Pinouts

(1’s)

(10’s)

(100’s)

(1000) AB4

(MINUS)

ICL7116, ICL7117 (PDIP)

TOP VIEW

1

HLDR

2

D1

3

C1

4

B1

5

A1

6

F1

7

G1

8

E1

9

D2

10

C2

11

B2

12

A2

13

F2

14

E2

15

D3

16

B3

17

F3

18

E3

19
20

POL

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

OSC 1
OSC 2
OSC 3
TEST
REF HI
V+

+

C

REF

-

C

REF

COMMON
IN HI
IN LO
A-Z
BUFF
INT
V­G2 (10’s)
C3

(100’s)

A3
G3
BP/GND

NC
NC

TEST

OSC 3

NC
OSC 2
OSC 1

HLDR

D1
C1
B1

ICL7116 (MQFP)

TOP VIEW

-

+

REF

REF

C

REF HIV+C

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

A1 F1 G1 E1 D2 C2

COMMON

IN HI

IN LO

A-Z

BUFF

INT

39 38 37 36 35 34

2221201918

B2 A2 F2 E2 D3

V-

33
32
31
30
29

28
27
26
25
24
23

NC
G2
C3
A3
G3

BP
POL
AB4
E3
F3
B3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

File Number 3083.2

ICL7116, ICL7117

Absolute Maximum Ratings Thermal Information

Supply Voltage

ICL7116, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

ICL7117, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

ICL7117, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-

Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-

Clock Input

ICL7116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+

ICL7117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(MQFP - Lead Tips Only)

Electrical Specifications (Note 3) T

= 25oC, f

A

CLOCK

= 48kHz, V

REF

= 100mV

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Zero Input Reading V

= 0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital

IN

Reading

Ratiometric Reading VlN = V

Rollover Error -VIN = +VlN≅ 195mV Difference in Reading for Equal

REF

, V

= 100mV 999 999/

REF

1000 Digital

1000

Reading

- ±0.2 ±1 Counts

Positive and Negative Inputs Near Full Scale

Linearity Full Scale = 200mV or Full Scale = 2V Maximum

- ±0.2 ±1 Counts

Deviation from Best Straight Line Fit (Note 5)
Common Mode Rejection Ratio VCM = ±1V , VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V
Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value

-15-µV

Not Exceeded 95% of Time) (Note 5)
Leakage Current Input VlN = 0 (Note 5) - 1 10 pA
Zero Reading Drift VlN = 0, 0

o

Scale Factor Temperature Coefficient VIN = 199mV, 0

C To 70

o

o

C (Note 5) - 0.2 1 µV/oC

o

C To 70

C (Note 5) - 1 5 ppm/oC
V+ Supply Current VIN = 0 (Does Not Include LED Current for ICL7117) - 1.0 1.8 mA
V- Supply Current ICL7117 Only - 0.6 1.8 mA
COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With

2.4 3.0 3.2 V

Respect to + Supply)

Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With

- 80 - ppm/oC

Respect to + Supply) (Note 5)
DISPLAY DRIVER (ICL7116 ONLY)
Peak-To-Peak Segment Drive Voltage

V+ = to V- = 9V, (Note 4) 4 5.5 6 V
Peak-To-Peak Backplane Drive Voltage

DISPLAY DRIVER (ICL7117 ONLY)
Segment Sinking Current V+ = 5V, Segment Voltage = 3V

(Except Pins 19 and 20) 58-mA
Pin 19 Only 10 16 - mA
Pin 20 Only 47-mA

NOTES:

3. Unless otherwise noted, specifications apply to both the ICL7116 and ICL7117. ICL7116 is tested in the circuit of Figure 1. ICL7117 is
tested in the circuit of Figure 2.

4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times con­version rate. Average DC component is less than 50mV.

5. Not tested, guaranteed by design.

2

ICL7116, ICL7117

Typical Applications and Test Circuits

+ -

9V

IN

+

R

R

1

5

-

C

REF

COM

C

5

IN HI

C

4R

3

4039383736353433323130

OSC 1

OSC 2

OSC 3

TEST

V+

REF HI

R

4

C

1

+

REF

C

C

2

IN LO

-

R

2

C

3

28

29

27262524232221

V-

INT

A-Z

BUFF

DISPLAY

G2

C3

A3

G3

BP

C1 = 0.1µF
C

= 0.47µF

2

C

= 22µF

3

C

= 100pF

4

C

= 0.01µF

5

R

= 24kΩ

1

= 47kΩ

R

2

R

= 100kΩ

3

R

= 1kΩ

4

R

= 1MΩ

5

ICL7116

F1

HLDRD1C1B1A1
123456789

E1D2C2B2A2F2E2D3B3F3E3

G1

101112

DISPLAY

13

14151617181920

AB4

POL

FIGURE 1. ICL7116 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV

FULL SCALE

C1 = 0.1µF
C

= 0.47µF

R

+5V -5V

R

TP

5

TP1TP

R

C

3

4

1

2

R

4

C

1

+ -

IN

R

5

TP

3

C

R

5

2

C

C

2

3

DISPLAY

TP

4

6

TO
DECIMAL
POINT

2

C

= 22µF

3

C

= 100pF

4

C

= 0.01µF

5

R

= 24kΩ

1

= 47kΩ

R

2

R

= 100kΩ

3

R

= 1kΩ

4

R

= 1MΩ

5

R6 = 150Ω

IN LO

28

29

27262524232221

V-

INT

A-Z

BUFF

G2

C3

A3

G3

GND

4039383736353433323130

OSC 2

OSC 3

TEST

REF HI

OSC 1

-

+

V+

REF

C

REF

IN HI

COM

C

ICL7117

HLDR

D1C1B1

123456789

A1F1G1E1D2C2B2

101112

DISPLAY

F2

E2

A2

13

14151617181920

F3

D3

E3

B3

AB4

POL

FIGURE 2. ICL7117 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV

FULL SCALE

3

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

= 0.45/RC

f

OSC

C

> 50pF; R

OSC

f

(Typ) = 48kHz

OSC

• OSCILLATOR PERIOD

= RC/0.45

t

OSC

• INTEGRATION CLOCK FREQUENCY

CLOCK

= f

OSC

f

• INTEGRATION PERIOD

= 1000 x (4/f

t

INT

• 60/50Hz REJECTION CRITERION

t

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 4µA

I

INT

• FULL SCALE ANALOG INPUT VOLTAGE

(Typ) = 200mV or 2V

V

lNFS

• INTEGRATE RESISTOR

V

R

INT

---------------- -=

I

INFS

INT

• INTEGRATE CAPACITOR

t

()I

C

INT

INT

--------------------------------=

V

INT

• INTEGRATOR OUTPUT VOLTAGE SWING

t

()I

()

V

•V

INT

INT

INT

--------------------------------=

C

INT

MAXIMUM SWING:

(V- + 1.0V) < V

> 50kΩ

OSC

/4

)

OSC

lNT/t50Hz

()

INT

INT

< (V+ - 0.5V), V

INT

= Integer

(Typ) = 2V

INT

ICL7116, ICL7117

• DISPLAY COUNT

COUNT 1000

• CONVERSION CYCLE

= t

t

CYC

t

= t

CYC

when f

OSC

• COMMON MODE INPUT VOLTAGE

(V- + 1V) < V

• AUTO-ZERO CAPACITOR

0.01µF < C

• REFERENCE CAPACITOR

0.1µF < C

•V

COM

Biased between V+ and V-.

•V

• ICL7116 POWER SUPPLY: SINGLE 9V

• ICL7116 DISPLAY: LCD

• ICL7117 POWER SUPPLY: DUAL ±5.0V

• ICL7117 DISPLAY: LED

≅ V+ - 2.8V

COM

Regulation lost when V+ to V- < ≅6.8V.
If V

COM

the V

COM

V+ - V- = 9V
Digital supply is generated internally
V

TEST

Type: Direct drive with digital logic supply amplitude.

V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND

Type: Non-Multiplexed Common Anode

V

IN

---------------

×=

V

REF

x 4000

CL0CK

x 16,000

OSC

= 48KHz; t

< (V+ - 0.5V)

lN

< 1µF

AZ

< 1µF

REF

CYC

= 333ms

is externally pulled down to (V + to V -)/2,

circuit will turn off.

≅ V+ - 4.5V

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)
2999 - 1000

SIGNAL INTEGRATE

PHASE FIXED
1000 COUNTS

TOTAL CONVERSION TIME = 4000 x t

4

DE-INTEGRATE PHASE

= 16,000 x t

CLOCK

0 - 1999 COUNTS

OSC

ICL7116, ICL7117

Pin Descriptions

PIN NUMBER

44 PIN

FLATPACK

1 8 HLDR Input Display Hold Control.
2 9 D1 Output Driver Pin for Segment “D” of the display units digit.
3 10 C1 Output Driver Pin for Segment “C” of the display units digit.
4 11 B1 Output Driver Pin for Segment “B” of the display units digit.
5 12 A1 Output Driver Pin for Segment “A” of the display units digit.
6 13 F1 Output Driver Pin for Segment “F” of the display units digit.
7 14 G1 Output Driver Pin for Segment “G” of the display units digit.
8 15 E1 Output Driver Pin for Segment “E” of the display units digit.

9 16 D2 Output Driver Pin for Segment “D” of the display tens digit.
10 17 C2 Output Driver Pin for Segment “C” of the display tens digit.
11 18 B2 Output Driver Pin for Segment “B” of the display tens digit.
12 19 A2 Output Driver Pin for Segment “A” of the display tens digit.
13 20 F2 Output Driver Pin for Segment “F” of the display tens digit.
14 21 E2 Output Driver Pin for Segment “E” of the display tens digit.
15 22 D3 Output Driver pin for segment “D” of the display hundreds digit.
16 23 B3 Output Driver pin for segment “B” of the display hundreds digit.
17 24 F3 Output Driver pin for segment “F” of the display hundreds digit.
18 25 E3 Output Driver pin for segment “E” of the display hundreds digit.
19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit.
20 27 POL Output Driver pin for the negative sign of the display.
21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground.
22 29 G3 Output Driver pin for segment “G” of the display hundreds digit.
23 30 A3 Output Driver pin for segment “A” of the display hundreds digit.
24 31 C3 Output Driver pin for segment “C” of the display hundreds digit.
25 32 G2 Output Driver pin for segment “G” of the display tens digit.
26 34 V- Supply Negative power supply.
27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor.
28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor.
29 37 A-Z Input Integrator amplifier input. To be connected to auto-zero capacitor.
30

31

32 40 COMMON Supply/

33
34

35
36

37 3 TEST Input Display test. Turns on all segments when tied to V+.
38

39
40

38
39

41
42

43
44

4
6
7

NAME FUNCTION DESCRIPTION40 PIN DIP

IN LO

IN HI

C

REF

C

REF

V+

REF HI

OSC3
OSC2
OSC1

Input Differential inputs. To be connected to input voltage to be measured. LO and HI

designators are for reference and do not imply that LO should be connected to
lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.

Internal voltage reference output.

Output

-

+

Supply Power Supply.

Output
Output

Input

Connection pins for reference capacitor.

Device clock generator circuit connection pins.

5