Intersil Corporation ICL7109CPL, ICL7109IDL, ICL7109IJL, ICL7109IPL, ICL7109MDL-883B Datasheet

1

®

November 2000

ICL7109

12-Bit, Microprocessor-

Compatible A/D Converter

Features

• 12-Bit Binary (Plus Polarity and Over-Range) Dual
Slope Integrating Analog-to-Digital Converter

• Byte-Organized, TTL Compatible Three-State Outputs
and UART Handshake Mode for Simple Parallel or
Serial Interfacing to Microprocessor Systems

• RUN/HOLD

Input and STATUS Output Can Be Used to

Monitor and Control Conversion Timing

• True Differential Input and Differential Reference

• Low Noise (Typ) . . . . . . . . . . . . . . . . . . . . . . . . 15µV

P-P

• Input Current (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .1pA

• Operates At Up to 30 Conversions/s

• On-Chip Oscillator Operates with Inexpensive 3.58MHz
TV Crystal Giving 7.5 Conversions/s for 60Hz Rejec­tion. May Also Be Used with An RC Network Oscillator
for Other Clock Frequencies

Description

The ICL7109 is a high performance, CMOS, low power
integrating A/D converter designed to easily interface with
microprocessors.

The output data (12 bits, polarity and over-range) may be
directly accessed under control of two byte enable inputs and a
chip select input for a single parallel bus interface. A UART
handshake mode is provided to allow the ICL7109 to work with
industry-standard UARTs in providing serial data transmission.
The RUN/HOLD

input and STATUS output allow monitoring

and control of conversion timing.

The ICL7109 provides the user with the high accuracy, low
noise, low drift versatility and economy of the dual-slope
integrating A/D converter. Features like true differential input
and reference, drift of less than 1µV/

o

C, maximum input bias
current of 10pA, and typical power consumption of 20mW
make the ICL7109 an attractive per-channel alternative to
analog multiplexing for many data acquisition applications.

Pinout

ICL7109

(CERDIP, PDIP, SBDIP)

TOP VIEW

Part Number Information

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

ICL7109MDL -55 to 125 40 Ld SBDIP D40.6

ICL7109IDL -25 to 85 40 Ld SBDIP D40.6

ICL7109IJL -25 to 85 40 Ld CERDIP F40.6

ICL7109CPL 0 to 70 40 Ld PDIP E40.6

ICL7109MDL/883B -55 to 125 40 Ld SBDIP D40.6

ICL7109IPL -25 to 85 40 Ld PDIP E40.6

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

GND

STATUS

POL

OR

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

TEST

LBEN

HBEN

CE/LOAD

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

V+

REF IN -

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COMMON

INT

AZ

BUF

REF OUT

V-

SEND

RUN/HOLD

BUF OSC OUT

OSC SEL

OSC OUT

OSC IN

MODE

File Number 3092.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2002. All Rights Reserved

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2

Absolute Maximum Ratings Thermal Information

Positive Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . .+6.0V

Negative Supply Voltage (GND to V-) . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to V-

Reference Input Voltage (Either Input) (Note 1) . . . . . . . . . . V+ to V-

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+) +0.3V

Pins 2-27 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V

Operating Conditions

Temperature Range

M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125oC

I Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25

o

C to 85oC

C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0

o

C to 75oC

Thermal Resistance (Typical, Note 1) θ

JA

(oC/W) θJC (oC/W)

SBDIP Package. . . . . . . . . . . . . . . . . . . . 60 20

CERDIP Package . . . . . . . . . . . . . . . . . . 55 18

PDIP Package . . . . . . . . . . . . . . . . . . . . . 50 N/A

Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150

o

C

Maximum Junction Temperature (CERDIP Package). . . . . . . 175

o

C

Maximum Storage Temperature Range . . . . . . . . . . -65

o

C to 150oC

Maximum Lead Temperature (Soldering 10s Max). . . . . . . . . 300

o

C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other condition s above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ

JA

is measured with the component mounted on an evaluation PC board in free air.

Analog Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T

A

= 25oC, f

CLK

= 3.58MHz,

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM PERFORMANCE

Oscillator Output Current

High, O

OH

V

OUT

= 2.5V - 1 - mA

Low, O

OL

V

OUT

= 2.5V - 1.5 - mA

Buffered Oscillator Output Current

High, BO

OH

V

OUT

= 2.5V - 2 - mA

Low, BO

OL

V

OUT

= 2.5V - 5 - mA

Zero Input Reading V

IN

= 0.0000V, V

REF

= 204.8mV -0000 ±0000 +0000 Counts

Ratiometric Error V

lN

= V

REF

, V

REF

= 204.8mV (Note 7) -3 - 0 Counts

Non-Linearity Full Scale = 409.6mV to 2.048mV

Maximum Deviation from Best Straight Line Fit, Over
Full Operating Temperature Range (Notes 4 and 6)

-1 ±0.2 +1 Counts

Rollover Error Full Scale = 409.6mV to 2.048V

Difference in Reading for Equal Positive and Negative
Inputs Near Full Scale (Notes 5 and 6), R

1

= 0Ω

-1 ±0.2 +1 Counts

Linearity Full-Scale = 200mV or Full Scale = 2V Maximum

Deviation from Best Straight Line Fit (Note 4)

- ±0.2 ±1 Counts

Common Mode Rejection Ratio, CMRR V

CM

= ±1V, VIN = 0V, Full Scale = 409.6mV - 50 - µV/V

Input Common Mode Range, VCMR Input HI, Input LO, Common (Note 4) (V-)

+2.0

-(V+)

-2.0

V

Noise, eN V

IN

= 0V, Full-Scale = 409.6mV

(Peak-to-Peak Value Not Exceeded 95% of Time)

-15- µV

Leakage Current Input, I

ILK

VlN = 0V, All Devices at 25oC (Note 4) - 1 10 pA

ICL7109CPL 0

o

C to 70oC (Note 4) - 20 100 pA

ICL7109IDL -25

o

C to 85oC (Note 4) - 100 250 pA

ICL7109MDL -55

o

C to 125oC-2100nA

Zero Reading Drift V

lN

= 0V, R1 - 0Ω (Note 4) - 0.2 1 µV/oC

ICL7109

3

Scale Factor Temperature Coefficient VIN = 408.9mV = > 77708 Reading Ext. Ref. 0ppm/oC

(Note 4)

- 1 5 ppm/oC

REFERENCE VOLTAGE

Ref Out Voltage, V

REF

Referred to V+, 25kΩ Between V+ and REF OUT -2.4 -2.8 -3.2 V

Ref Out Temperature Coefficient 25kΩ Between V+ and REF OUT (Note 4) - 80 - ppm/

o

C

POWER SUPPLY CHARACTERISTICS

Supply Current V+ to GND, I+ V

IN

= 0V, Crystal Osc 3.58MHz Test Circuit - 700 1500 µA

Supply Current V+ to V-, I

SUPP

Pins 2 - 21, 25, 26, 27, 29; Open - 700 1500 µA

Digital Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T

A

= 25oC, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL OUTPUTS

Output High Voltage, V

OH

I

OUT

= 100µA Pins 2 - 16, 18, 19, 20 3.5 4.3 - V

Output Low Voltage, V

OL

I

OUT

= 1.6mA Pins 2 - 16, 18, 19, 20 - ±0.20 ±0.40 V

Output Leakage Current Pins 3 - 16 High Impedance - ±0.01 ±1 µA

Control I/O Pullup Current Pins 18, 19, 20 V

OUT

= V+ -3V MODE Input at GND

(Note 4)

-5- µA

Control I/O Loading HBEN

Pin 19 LBEN Pin 18 (Note 4) - − 50 pF

DIGITAL INPUTS

Input High Voltage, V

IH

Pins 18 - 21, 26, 27 Referred to GND 3.0 - - V

Input Low Voltage, V

IL

Pins 18 - 21, 26, 27 Referred to GND - - 1 V

Input Pull-Up Current Pins 26, 27 V

OUT

= (V+) -3V - 5 - µA

Input Pull-Up Current Pins 17, 24 V

OUT

= (V+) -3V - 25 - µA

Input Pull-Down Current Pin 21 V

OUT

= GND +3V - 5 - µA

TIMING CHARACTERISTICS

MODE Input Pulse Width, t

W

(Note 4) 50 - - ns

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

2. Due to the SCR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages
greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources
other than the same power supply be applied to the ICL7109 before its power supply is established, and that in multiple supply systems
the supply to the ICL7109 be activated first.

3. This limit refers to that of the package and will not be obtained during normal operation.

4. This parameter is not production tested, but is guaranteed by design.

5. Roll-over error for T

A

= -55oC to 125oC is ±10 counts (Max).

6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range.

7. For CERDIP package the Ratiometric error can be -4 (Min).

Analog Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T

A

= 25oC, f

CLK

= 3.58MHz,

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ICL7109

4

Pin Descriptions

PIN SYMBOL DESCRIPTION

1 GND Digital Ground, 0V. Ground return for all digital logic.

2 STATUS Output High during integrate and deintegrate until data is latched. Output Low when analog section

is in Auto-Zero configuration.

3 POL Polarity - HI for positive input. Three-State Output Data Bits

4 OR Overrange - HI if overranged. Three-State Output Data Bits

5 B12 Bit 12 (Most Significant Bit) Three-State Output Data Bits

6 B11 Bit 11 High = True Three-State Output Data Bits

7 B10 Bit 10 High = True Three-State Output Data Bits

8 B9 Bit 9 High = True Three-State Output Data Bits

9 B8 Bit 8 High = True Three-State Output Data Bits

10 B7 Bit 7 High = True Three-State Output Data Bits

11 B6 Bit 6 High = True Three-State Output Data Bits

12 B5 Bit 5 High = True Three-State Output Data Bits

13 B4 Bit 4 High = True Three-State Output Data Bits

14 B3 Bit 3 High = True Three-State Output Data Bits

15 B2 Bit 2 High = True Three-State Output Data Bits

16 B1 Bit 1 (Least Significant Bit) Three-State Output Data Bits

17 TEST Input High - Normal Operation. Input Low - Forces all bit outputs high. Note: This input is used for

test purposes only. Tie high if not used.

18 LBEN

Low Byte Enable - With Mode (Pin 21) low, and CE/LOAD (Pin 20) low, taking this pin low activates
low order byte outputs B1 through B8.
With Mode (Pin 21) high, this pin serves as a low byte flag output used in handshake mode.
See Figures 7, 8, 9.

19 HBEN

High Byte Enable - With Mode (Pin 21) low, and CE/LOAD (Pin 20) low, taking this pin low activates
high order byte outputs B9 through B12, POL, OR.
With Mode (Pin 21) high, this pin serves as a high byte flag output used in handshake mode.
See Figures 7, 8, 9.

20 CE/LOAD

Chip Enable Load - With Mode (Pin 21) low. CE/LOAD serves as a master output enable. When
high, B1 through B12, POL, OR outputs are disabled.
With Mode (Pin 21) high, this pin serves as a load strobe used in handshake mode.
See Figures 7, 8, 9.

21 MODE Input Low - Direct output mode where CE/LOAD

(Pin 20), HBEN (Pin 19) and LBEN (Pin 18) act as
inputs directly controlling byte outputs.
Input Pulsed High - Causes immediate entry into handshake mode and output of data as in Figure 9.
Input High - Enables CE/LOAD

(Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, handshake

mode will be entered and data output as in Figures 7 and 8 at conversion completion.

22 OSC IN Oscillator Input

23 OSC OUT Oscillator Output

ICL7109

5

24 OSC SEL Oscillator Select - Input high configures OSC IN, OSC OUT, BUF OSC OUT as RC oscillator - clock

will be same phase and duty cycle as BUF OSC OUT.
Input low configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of
frequency at BUF OSC OUT.

25 BUF OSC OUT Buffered Oscillator Output

26 RUN/HOLD

Input High - Conversions continuously performed every 8192 clock pulses.
Input Low - Conversion in progress completed, converter will stop in Auto-Zero 7 counts before
integrate.

27 SEND Input - Used in handshake mode to indicate ability of an external device to accept data. Connect to

+5V if not used.

28 V- Analog Negative Supply - Nominally -5V with respect to GND (Pin 1).

29 REF OUT Reference Voltage Output - Nominally 2.8V down from V+ (Pin 40).

30 BUFFER Buffer Amplifier Output.

31 AUTO-ZERO Auto-Zero Node - Inside foil of C

AZ

.

32 INTEGRATOR Integrator Output - Outside foil of C

INT

.

33 COMMON Analog Common - System is Auto-Zeroed to COMMON.

34 INPUT LO Differential Input Low Side.

35 INPUT HI Differential Input High Side.

36 REF IN + Differential Reference Input Positive.

37 REF CAP + Reference Capacitor Positive.

38 REF CAP- Reference Capacitor Negative.

39 REF IN- Differential Reference Input Negative.

40 V+ Positive Supply Voltage - Nominally +5V with respect to GND (Pin 1).

NOTE: All digital levels are positive true.

Pin Descriptions (Continued)

PIN SYMBOL DESCRIPTION

ICL7109

6

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

f

OSC

= 0.45/RC

C

OSC

> 50pF; R

OSC

> 50kΩ

f

OSC

(Typ) = 60kHz
or
f

OSC

(Typ) = 3.58MHz Crystal

• OSCILLATOR PERIOD

t

OSC

= RC/0.45
t

OSC

= 1/3.58MHz (Crystal)

• INTEGRATION CLOCK FREQUENCY

f

CLOCK

= f

OSC

(RC Mode)

f

CLOCK

= f

OSC

/58 (Crystal)

t

CLOCK

= 1/f

CLOCK

• INTEGRATION PERIOD

t

INT

= 2048 x t

CLOCK

• 60/50Hz REJECTION CRITERION

t

INT/t60Hz

or t

lNT/t50Hz

= Integer

• OPTIMUM INTEGRATION CURRENT

I

INT

= 20µA

• FULL-SCALE ANALOG INPUT VOLTAGE

V

lNFS

Typically = 200mV or 2V

• INTEGRATE RESISTOR

• INTEGRATE CAPACITOR

• INTEGRATOR OUTPUT VOLTAGE SWING

•V

INT

MAXIMUM SWING

(V- + 0.5V) < V

INT

< (V+ - 0.5V)

V

INT

(Typ) = 2V

• DISPLAY COUNT

• CONVERSION CYCLE

t

CYC

= t

CL0CK

x 8192

(In Free Run Mode, Run/HOLD

= 1)

when f

CLOCK

= 60kHz, t

CYC

= 133ms

• COMMON MODE INPUT VOLTAGE

(V- + 2.0V) < V

lN

< (V+ - 2V)

• AUTO-ZERO CAPACITOR

0.01µF < C

AZ

< 1µF

• REFERENCE CAPACITOR

0.1µF < C

REF

< 1µF

•V

REF

Biased between V+ and V­V

REF

≅ V+ - 2.8V
Regulation lost when V+ to V- ≤ 6.4V.
If V

REF

is not used, float output pin.

• POWER SUPPLY: DUAL ±5.0V

V+ = +5V to GND
V- = -5V to GND

• OUTPUT TYPE

Binary Amplitude with Polarity and Overrange Bits
Tips: Always tie TEST pin HIGH.
Don’t leave any inputs floating.

R

INT

V

INFS

I

INT

------ ----- ---- --=

C

INT

t

INT

()I

INT

()

V

INT

--------------------------------=

V

INT

t

INT

()I

INT

()

C

INT

--------------------------------=

COUNT 2048

V

IN

V

REF

-----------------×=

ICL7109

7

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)

6143 - 2048

INTEGRATE

PHASE FIXED

2048 COUNTS

DE-INTEGRATE PHASE

0 - 4095 COUNTS

TOTAL CONVERSION TIME = 8192 x t

CLOCK

(IN FREE-RUN MODE)

FIGURE 1A. TYPICAL CONNECTION DIAGRAM UART INTERFACE-TO TRANSMIT LATEST RESULT, SEND ANY WORD TO UART

18

1

25

2

19

17

21

20

27

GND
BUF OSC

STATUS

HBEN

3 - 8
B9 - B12, POL,OR
9 - 16

TEST

LBEN

MODE

CE/LOAD

SEND

28

40

39

38

37

36

35

34

33

32

31

30

29

26

24

23

22

V+

REF IN -

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COMMON

INT

AZ

BUF

REF OUT

V-

RUN/HOLD

OSC SEL

OSC OUT

OSC IN

GND

GND

+5V

1µF

0.01µF

0.33µF

0.15µF

C

AZ

C

INT

R

INT

1MΩ

3.58MHz
CRYSTAL

-

+

+

INPUT

GND

EXTERNAL
REFERENCE

-5V

GND

-

20kΩ 0.2V REF
200kΩ 2V REF

+5V OR OPEN

OUT

/

/

6

8

B1 - B8

1

2

3

4

13

14

15

16

20

25

V+

OSC CONTROL

GND

RRD

5 - 12

PE

FE

OE

SFD

RRI

TRO

18

40

17

39

38

37

36

35

34

31

24

19

23

22

21

XTAL

XTAL

EPE

CLS1

CLS2

SBS

PI

CLR

26 - 33

TRE

DRR

DR

TBRL

TBRE

MR

GND

GND

TBR 1 - 8

+5V

+5V

8

/

GND

1000pF

RBR 1 - 8

SERIAL

OUTPUT

SERIAL

INPUT

+5V

+5V

+5V

IM6403

CMOS UART

ICL7109

CMOS A/D CONVERTER

FOR LOWEST POWER CONSUMPTION
TBR1 - TBR8 INPUTS SHOULD HAVE 100kΩ
PULLUP RESISTORS TO +5V

+5V

ICL7109

8

Detailed Description

Analog Section

Figure 2 shows the equivalent circuit of the Analog Section
for the ICL7109. When the RUN/HOLD

input is left open or
connected to V+, the circuit will perform conversions at a
rate determined by the clock frequency (8192 clock periods
per cycle). Each measurement cycle is divided into three
phases as shown in Figure 3. They are (1) auto-zero (A-Z),
(2) signal integrate (INT) and (3) de-integrate (DE).

Auto-Zero Phase

During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
C

AZ

to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range of the inputs. At the end of this phase,
the polarity of the integrated signal is determined.

FIGURE 1B. TYPICAL CONNECTION DIAGRAM PARALLEL INTERFACE WITH 8048 MICROCOMPUTER

FIGURE 1.

9

25

26

40

39

/

5

20

5

6

17

26

19

18

40

1

2

V+

TEST

3 - 8
B9 - B12,

9 - 16

STATUS

HBEN

CE/LOAD

28

39

38

37

36

35

34

33

32

31

30

29

26

24

23

21

REF IN -

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COMMON

INT

AZ

BUF

REF OUT

V-

RUN/HOLD

OSC SEL

OSC OUT

OSC IN

GND

GND

1µF

0.01µF

0.33µF

0.15µF

C

AZ

C

INT

R

INT

1MΩ

3.58MHz
CRYSTAL

-

+

+

INPUT

GND

EXTERNAL
REFERENCE

-5V

GND

-

20kΩ 0.2V REF
200kΩ 2V REF

+5V OR OPEN

GND

/

/

6

8

B1 - B8

1

4

7

8

11

20

XTAL1

TO

RESET

EA

WR

ALE

GND

28

30

29

27

10

XTAL2

P12

P11

P10

RD

P13

+5V

8

/

27

25

22

MODE

SEND

BUFF OSC OUT

+5V

+5V

SS

INT

2

RUN/HOLD

LBEN

POL,OR

12 - 19

DB0 - DB7

31 - 34

P14 - P17

35 - 38

P20 - P27

/

8

21 - 24

OTHER
I/O

GND

PSEN

GND

PROG

V

DD

V

CC

+5V

TL

+5V

+5V

+5V

ICL7109

8748/9048

3

+5V

ICL7109