Intersil Corporation ICL7109 Datasheet

August 1997

ICL7109

12-Bit, Microprocessor-

Compatible A/D Converter

Features

• 12-Bit Binary (Plus Polarity and Over-Range) Dual
Slope Integrating Analog-to-Digital Converter

• Byte-Organized, TTL Compatible Three-State Outputs
and UART Handshake Mode for Simple Parallel or
Serial Interfacing to Microprocessor Systems

• RUN/

HOLD Input and STATUS Output Can Be Used to

Monitor and Control Conversion Timing

• True Differential Input and Differential Reference

• Low Noise (Typ) . . . . . . . . . . . . . . . . . . . . . . . . 15µV

P-P

• Input Current (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . .1pA

• Operates At Up to 30 Conversions/s

• On-Chip Oscillator Operates with Inexpensive 3.58MHz
TV Crystal Giving 7.5 Conversions/s for 60Hz Rejection.
May Also Be Used with An RC Network Oscillator for
Other Clock Frequencies

Ordering Information

TEMP.

PART NUMBER

ICL7109MDL -55 to 125 40 Ld SBDIP D40.6
ICL7109IDL -25 to 85 40 Ld SBDIP D40.6
ICL7109IJL -25 to 85 40 Ld CERDIP F40.6
ICL7109CPL 0 to 70 40 Ld PDIP E40.6
ICL7109MDL/883B -55 to 125 40 Ld SBDIP D40.6
ICL7109IPL -25 to 85 40 Ld PDIP E40.6

RANGE (oC) PACKAGE

PKG.

NO.

Description

The ICL7109 is a high performance, CMOS, low power
integrating A/D converter designed to easily interface with
microprocessors.

The output data (12 bits, polarity and over-range) may be
directly accessed under control of two byte enable inputs and a
chip select input for a single parallel bus interface. A UART
handshake mode is provided to allow the ICL7109 to work with
industry-standard UARTs in providing serial data transmission.
The RUN/

HOLD input and STATUS output allow monitoring

and control of conversion timing.
The ICL7109 provides the user with the high accuracy, low

noise, low drift versatility and economy of the dual-slope
integrating A/D converter. Features like true differential input
and reference, drift of less than 1µV/

o

C, maximum input bias
current of 10pA, and typical power consumption of 20mW
make the ICL7109 an attractive per-channel alternative to
analog multiplexing for many data acquisition applications.

Pinout

ICL7109

(CERDIP, PDIP, SBDIP)

TOP VIEW

1

GND

STATUS

POL

OR
B12
B11
B10

B9
B8
B7
B6
B5
B4
B3
B2
B1

TEST

LBEN

HBEN

CE/LOAD

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

40

V+

39

REF IN -

38

REF CAP-

37

REF CAP+

36

REF IN+

35

IN HI

34

IN LO

33

COMMON

32

INT

31

AZ

30

BUF

29

REF OUT

28

V-

27

SEND

26

RUN/HOLD

25

BUF OSC OUT

24

OSC SEL

23

OSC OUT

22

OSC IN

21

MODE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

5-4

File Number 3092.1

ICL7109

Absolute Maximum Ratings Thermal Information

Positive Supply Voltage (GND to V+). . . . . . . . . . . . . . . . . . . .+6.0V

Negative Supply Voltage (GND to V-). . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-

Reference Input Voltage (Either Input) (Note 1) . . . . . . . . . . V+ to V-

Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V+) +0.3V

Pins 2-27 (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V

Operating Conditions

Temperature Range

M Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

I Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC

C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

SBDIP Package. . . . . . . . . . . . . . . . . . . . 60 20

CERDIP Package . . . . . . . . . . . . . . . . . . 55 18

PDIP Package. . . . . . . . . . . . . . . . . . . . . 50 N/A

Maximum Junction Temperature (PDIP Package). . . . . . . . . . 150oC

Maximum Junction Temperature (CERDIP Package) . . . . . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s Max). . . . . . . . .300oC

Analog Electrical Specifications V+ = +5V, V - = -5V, GND = 0V, T

= 25oC, f

A

CLK

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM PERFORMANCE

Oscillator Output Current

High, O
Low, O

OH

OL

V

= 2.5V - 1 - mA

OUT

V

= 2.5V - 1.5 - mA

OUT

Buffered Oscillator Output Current

High, BO
Low, BO

OH

OL

Zero Input Reading VIN = 0.0000V, V
Ratiometric Error VlN = V

V

= 2.5V - 2 - mA

OUT

V

= 2.5V - 5 - mA

OUT

= 204.8mV -0000 ±0000 +0000 Counts

REF

, V

REF

= 204.8mV (Note 7) -3 - 0 Counts

REF

Non-Linearity Full Scale = 409.6mV to 2.048mV

Maximum Deviation from Best Straight Line Fit, Over
Full Operating Temperature Range (Notes 4 and 6)

Rollover Error Full Scale = 409.6mV to 2.048V

Difference in Reading for Equal Positive and Negative
Inputs Near Full Scale (Notes 5 and 6), R1 = 0Ω

Linearity Full-Scale = 200mV or Full Scale = 2V Maximum

Deviation from Best Straight Line Fit (Note 4)

= 3.58MHz,

-1 ±0.2 +1 Counts

-1 ±0.2 +1 Counts

- ±0.2 ±1 Counts

Common Mode Rejection Ratio, CMRR VCM = ±1V , VIN = 0V, Full Scale = 409.6mV - 50 - µV/V
Input Common Mode Range, VCMR Input HI, Input LO, Common (Note 4) (V-)

+2.0

Noise, eN VIN = 0V, Full-Scale = 409.6mV

-15- µV

- (V+)

-2.0

V

(Peak-to-Peak Value Not Exceeded 95% of Time)

Leakage Current Input, I

ILK

VlN = 0V, All Devices at 25oC (Note 4) - 1 10 pA
ICL7109CPL 0oC to 70oC (Note 4) - 20 100 pA
ICL7109IDL -25oC to 85oC (Note 4) - 100 250 pA
ICL7109MDL -55oC to 125oC - 2 100 nA

Zero Reading Drift VlN = 0V, R1 - 0Ω (Note 4) - 0.2 1 µV/oC

5-5

ICL7109

Analog Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T

= 25oC, f

A

= 3.58MHz,

CLK

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Scale Factor Temperature Coefficient VIN = 408.9mV = > 77708Reading Ext. Ref. 0ppm/oC

- 1 5 ppm/oC

(Note 4)

REFERENCE VOLTAGE

Ref Out Voltage, V

REF

Referred to V+, 25kΩ Between V+ and REF OUT -2.4 -2.8 -3.2 V

Ref Out Temperature Coefficient 25kΩ Between V+ and REF OUT (Note 4) - 80 - ppm/oC

POWER SUPPLY CHARACTERISTICS

Supply Current V+ to GND, I+ VIN = 0V, Crystal Osc 3.58MHz Test Circuit - 700 1500 µA
Supply Current V+ to V-, I

SUPP

Digital Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T

Pins 2 - 21, 25, 26, 27, 29; Open - 700 1500 µA

= 25oC, Unless Otherwise Specified

A

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL OUTPUTS

Output High Voltage, V
Output Low Voltage, V

OH

OL

I

= 100µA Pins 2 - 16, 18, 19, 20 3.5 4.3 - V

OUT

I

= 1.6mA Pins 2 - 16, 18, 19, 20 - ±0.20 ±0.40 V

OUT

Output Leakage Current Pins 3 - 16 High Impedance - ±0.01 ±1 µA
Control I/O Pullup Current Pins 18, 19, 20 V

= V+ -3V MODE Input at GND

OUT

-5- µA

(Note 4)

Control I/O Loading HBEN Pin 19 LBEN Pin 18 (Note 4) - − 50 pF

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

IH

IL

Input Pull-Up Current Pins 26, 27 V
Input Pull-Up Current Pins 17, 24 V
Input Pull-Down Current Pin 21 V

Pins 18 - 21, 26, 27 Referred to GND 3.0 - - V

Pins 18 - 21, 26, 27 Referred to GND - - 1 V

= (V+) -3V - 5 - µA

OUT

= (V+) -3V - 25 - µA

OUT

= GND +3V - 5 - µA

OUT

TIMING CHARACTERISTICS

MODE Input Pulse Width, t

W

(Note 4) 50 - - ns

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

2. Due to the SCR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages
greater than V+ or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs from sources
other than the same power supply be applied to the ICL7109 before its power supply is established, and that in multiple supply systems
the supply to the ICL7109 be activated first.

3. This limit refers to that of the package and will not be obtained during normal operation.

4. This parameter is not production tested, but is guaranteed by design.

5. Roll-over error for TA = -55oC to 125oC is ±10 counts (Max).

6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range.

7. For CERDIP package the Ratiometric error can be -4 (Min).

5-6

ICL7109

Pin Descriptions

PIN SYMBOL DESCRIPTION

1 GND Digital Ground, 0V. Ground return for all digital logic.
2 STATUS Output High during integrate and deintegrate until data is latched. Output Low when analog section

is in Auto-Zero configuration.
3 POL Polarity - HI for positive input. Three-State Output Data Bits
4 OR Overrange - HI if overranged. Three-State Output Data Bits
5 B12 Bit 12 (Most Significant Bit) Three-State Output Data Bits
6 B11 Bit 11 High = True Three-State Output Data Bits
7 B10 Bit 10 High = True Three-State Output Data Bits
8 B9 Bit 9 High = True Three-State Output Data Bits
9 B8 Bit 8 High = True Three-State Output Data Bits

10 B7 Bit 7 High = True Three-State Output Data Bits
11 B6 Bit 6 High = True Three-State Output Data Bits
12 B5 Bit 5 High = True Three-State Output Data Bits
13 B4 Bit 4 High = True Three-State Output Data Bits
14 B3 Bit 3 High = True Three-State Output Data Bits
15 B2 Bit 2 High = True Three-State Output Data Bits
16 B1 Bit 1 (Least Significant Bit) Three-State Output Data Bits
17 TEST Input High - Normal Operation. Input Low - Forces all bit outputs high. Note: This input is used for

test purposes only. Tie high if not used.

18 LBEN Low Byte Enable - With Mode (Pin 21) low, and CE/LOAD (Pin 20) low, taking this pin low activates

low order byte outputs B1 through B8.

With Mode (Pin 21) high, this pin serves as a low byte flag output used in handshake mode.

See Figures 7, 8, 9.

19 HBEN High Byte Enable - With Mode (Pin 21) low, and CE/LOAD (Pin 20) low, taking this pin low activates

high order byte outputs B9 through B12, POL, OR.

With Mode (Pin 21) high, this pin serves as a high byte flag output used in handshake mode.

See Figures 7, 8, 9.

20 CE/LOAD Chip Enable Load - With Mode (Pin 21) low. CE/LOAD serves as a master output enable. When

high, B1 through B12, POL, OR outputs are disabled.

With Mode (Pin 21) high, this pin serves as a load strobe used in handshake mode.

See Figures 7, 8, 9.

21 MODE Input Low - Direct output mode where CE/LOAD (Pin 20), HBEN (Pin 19) and LBEN (Pin 18) act as

inputs directly controlling byte outputs.

Input Pulsed High - Causes immediate entry into handshake mode and output of data as in Figure 9.

Input High - Enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, handshake

mode will be entered and data output as in Figures 7 and 8 at conversion completion.

22 OSC IN Oscillator Input
23 OSC OUT Oscillator Output

5-7

ICL7109

Pin Descriptions (Continued)

PIN SYMBOL DESCRIPTION

24 OSC SEL Oscillator Select - Input high configures OSC IN, OSC OUT, BUF OSC OUT as RC oscillator - clock

will be same phase and duty cycle as BUF OSC OUT.

Input low configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of

frequency at BUF OSC OUT.

25 BUF OSC OUT Buffered Oscillator Output
26 RUN/HOLD Input High - Conversions continuously performed every 8192 clock pulses.

Input Low - Conversion in progress completed, con verter will stop in Auto-Zero 7 counts before

integrate.

27 SEND Input - Used in handshake mode to indicate ability of an external device to accept data. Connect to

+5V if not used.

28 V- Analog Negative Supply - Nominally -5V with respect to GND (Pin 1).
29 REF OUT Reference Voltage Output - Nominally 2.8V down from V+ (Pin 40).
30 BUFFER Buffer Amplifier Output.
31 AUTO-ZERO Auto-Zero Node - Inside foil of CAZ.
32 INTEGRATOR Integrator Output - Outside foil of C
33 COMMON Analog Common - System is Auto-Zeroed to COMMON.
34 INPUT LO Differential Input Low Side.
35 INPUT HI Differential Input High Side.
36 REF IN + Differential Reference Input Positive.
37 REF CAP + Reference Capacitor Positive.
38 REF CAP- Reference Capacitor Negative.
39 REF IN- Differential Reference Input Negative.
40 V+ Positive Supply Voltage - Nominally +5V with respect to GND (Pin 1).

NOTE: All digital levels are positive true.

INT

.

5-8

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

= 0.45/RC

f

OSC

C

> 50pF; R

OSC

f

(Typ) = 60kHz

OSC

or
f

(Typ) = 3.58MHz Crystal

OSC

• OSCILLATOR PERIOD

= RC/0.45

t

OSC

t

= 1/3.58MHz (Crystal)

OSC

• INTEGRATION CLOCK FREQUENCY

CLOCK
CLOCK
CLOCK

= f
= f
= 1/f

OSC
OSC

CLOCK

f
f
t

• INTEGRATION PERIOD

= 2048 x t

t

INT

• 60/50Hz REJECTION CRITERION

t

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 20µA

I

INT

• FULL-SCALE ANALOG INPUT VOLTAGE

Typically = 200mV or 2V

V

lNFS

• INTEGRATE RESISTOR

V

R

INT

---------------- -=

I

INFS

INT

• INTEGRATE CAPACITOR

t

()I

C

INT

INT

--------------------------------=

V

INT

• INTEGRATOR OUTPUT VOLTAGE SWING

t

()I

V

INT

INT

--------------------------------=

C

INT

> 50kΩ

OSC

(RC Mode)
/58 (Crystal)

CLOCK

lNT/t50Hz

()

INT

()

INT

= Integer

ICL7109

•V

MAXIMUM SWING

INT

(V- + 0.5V) < V
V

(Typ) = 2V

INT

• DISPLAY COUNT

COUNT 2048

• CONVERSION CYCLE

= t

t

CYC

CL0CK

(In Free Run Mode, Run/
when f

CLOCK

• COMMON MODE INPUT VOLTAGE

(V- + 2.0V) < V

• AUTO-ZERO CAPACITOR

0.01µF < C

• REFERENCE CAPACITOR

0.1µF < C

•V

REF

REF

Biased between V+ and V­V

≅ V+ - 2.8V

REF

Regulation lost when V+ to V- ≤ 6.4V.
If V

is not used, float output pin.

REF

• POWER SUPPLY: DUAL ±5.0V

V+ = +5V to GND
V- = -5V to GND

• OUTPUT TYPE

Binary Amplitude with Polarity and Overrange Bits
Tips: Always tie TEST pin HIGH.
Don’t leave any inputs floating.

INT

---------------- -

×=

V

x 8192

= 60kHz, t

< (V+ - 2V)

lN

< 1µF

AZ

< 1µF

< (V+ - 0.5V)

V

REF

IN

HOLD = 1)

= 133ms

CYC

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)
6143 - 2048

TOTAL CONVERSION TIME = 8192 x t

INTEGRATE
PHASE FIXED
2048 COUNTS

5-9

DE-INTEGRATE PHASE

(IN FREE-RUN MODE)

CLOCK

0 - 4095 COUNTS

ICL7109

+5V

GND

+5V

+5V

SERIAL

SERIAL

OUTPUT

INPUT

1

V+

2

OSC CONTROL
GND

3
4

RRD

5 - 12
RBR 1 - 8

13

PE

14

FE

15

OE

16

SFD

20

RRI

25

TRO

CMOS UART

IM6403

XTAL

40

XTAL

17

EPE

39

CLS1

38

CLS2

37

SBS

36

PI

35

CLR

34

26 - 33

TBR 1 - 8

31

TRE

24

DRR

18

DR

19

TBRL

23

TBRE

22

MR

21

FOR LOWEST POWER CONSUMPTION
TBR1 - TBR8 INPUTS SHOULD HAVE 100kΩ
PULLUP RESISTORS TO +5V

GND
+5V

GND

+5V

1000pF

8

/

GND

+5V

1

GND
BUF OSC

25

OUT

2

STATUS

19

HBEN

3 - 8

6

/

B9 - B12, POL,OR

8

9 - 16

/

B1 - B8

17

TEST

18

LBEN

MODE

21

20

CE/LOAD

27

SEND

CMOS A/D CONVERTER

REF CAP-

REF CAP+

COMMON

REF OUT

RUN/

OSC SEL

OSC OUT

ICL7109

V+

REF IN -

REF IN+

IN HI

IN LO

INT

AZ

BUF

HOLD

OSC IN

+5V

40
39
38

1µF

37
36
35
34
33
32
31
30
29
28

V-

26

24
23
22

1MΩ

0.01µF

C

C

0.33µF

-5V

+5V OR OPEN

GND

AZ

0.15µF

R

INT

3.58MHz
CRYSTAL

-

EXTERNAL
REFERENCE

+
+

-

GND

INT

20kΩ 0.2V REF
200kΩ 2V REF

GND

INPUT

FIGURE 1A. TYPICAL CONNECTION DIAGRAM UART INTERFACE-TO TRANSMIT LATEST RESULT, SEND ANY WORD TO UART

+5V

GND

+5V
+5V
+5V
+5V

GND

1
4
5
6

7
8

9
11
25
26
39
40

20

2

XTAL1

TO
RESET
SS
INT

EA
WR
PSEN
ALE
PROG
V

DD

TL
V

CC

GND

XTAL2

21 - 24
35 - 38

P20 - P27

31 - 34

P14 - P17

8748/9048

12 - 19

DB0 - DB7

3

P13
P12
P11
P10

RD

40

+5V

GND

+5V

/

8

OTHER
I/O

/

5

30
29
28
27

8

/

10

V+

-

EXTERNAL
REFERENCE

+
+

-

GND

INT

20kΩ 0.2V REF
200kΩ 2V REF

GND

INPUT

IN HI

IN LO

INT

AZ

BUF

SEND
HOLD

OSC IN

MODE

39
38

1µF

37
36
35
34
33
32
31
30
29
28

V-

27
26
25
24
23
22
21

1MΩ

0.01µF

C

C

0.33µF

-5V
+5V
+5V OR OPEN

GND

AZ

0.15µF

R

INT

3.58MHz
CRYSTAL

1

GND

17

TEST

ICL7109

26

RUN/
STATUS

2

18

LBEN

19

HBEN

3 - 8

6

B9 - B12,

/

POL,OR

8

9 - 16

/

B1 - B8

20

CE/LOAD

REF IN -

REF CAP-

REF CAP+

REF IN+

COMMON

HOLD

REF OUT

RUN/

BUFF OSC OUT

OSC SEL

OSC OUT

FIGURE 1B. TYPICAL CONNECTION DIAGRAM PARALLEL INTERFACE WITH 8048 MICROCOMPUTER

FIGURE 1.

5-10