31/2 Digit, LCD/LED Display, A/D Converters
DATASHEET
ICL7106, ICL7107, ICL7107S
The Intersil ICL7106 and ICL7107 are high performance, low
power, 3
decoders, display drivers, a reference, and a clock. The
ICL7106 is designed to interface with a liquid crystal display
(LCD) and includes a multiplexed backplane drive; the ICL7107
will directly drive an instrument size light emitting diode (LED)
1
/2 digit A/D converters. Included are seven segment
Features
• Guaranteed zero reading for 0V input on all scales
• True polarity at zero for precise null detection
• 1pA typical input current
• True differential input and reference, direct display drive
- LCD ICL7106, LED lCL7107
display.
The ICL7106 and ICL7107 bring together a combination of
high accuracy, versatility, and true economy. It features
auto zero to less than 10µV, zero drift of less than 1µV/°C,
input bias current of 10pA (max) and rollover error of less than
one count. True differential inputs and reference are useful in
all systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
• Low noise - less than 15µV
• On-chip clock and reference
• Low power dissipation - typically less than 10mW
• No additional active circuits required
• Enhanced display stability
• Pb-free (RoHS compliant)
P-P
type transducers. Finally, the true economy of single power
supply operation (ICL7106), enables a high performance panel
meter to be built with the addition of only 10 passive
components and a display.
Ordering Information
PART NUMBE R
(Note 2
)PART MARKING
ICL7106CPLZ ICL7106CPLZ 0 to 70 40 Ld PDIP (Note 3
ICL7106CM44Z (Note 4) ICL7106 CM44Z 0 to 70 44 Ld MQFP Q44.10x10
ICL7106CM44ZT (Notes 4
ICL7107CPLZ ICL7107CPLZ 0 to 70 40 Ld PDIP (Note 3
ICL7107SCPLZ ICL7107SCPLZ 0 to 70 40 Ld PDIP (Notes 1, 3) E40.6
ICL7107CM44Z (Note 4
ICL7107CM44ZT (Notes 4
NOTES:
1. “S” indicates enhanced stability.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
4. For Moisture Sensitivity Level (MSL), please see product information page for ICL7106
tech brief TB363
5. Please refer to TB347
, 5) ICL7106 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10
) ICL7107 CM44Z 0 to 70 44 Ld MQFP Q44.10x10
, 5) ICL7107 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10
.
for details on reel specifications.
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free) PKG. DWG. #
) E40.6
) E40.6
, ICL7107, ICL7107S. For more information on MSL, please see
October 24, 2014
FN3082.9
1
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
| Copyright Intersil Americas LLC 2002, 2004, 2005, 2014. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Pin Configurations
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
(1000) AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2 (10’s)
C3
A3
G3
BP/GND
(1’s)
(10’s)
(100’s)
(MINUS)
(100’s)
OSC 2
NC
OSC 3
TEST
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 1
V+
D1
C1
B1
A1 F1 G1 E1 D2 C2
28
27
26
25
24
23
2221201918
B2 A2 F2 E2 D3
B3
F3
E3
AB4
POL
BP/GND
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
A-Z
BUFF
INT
V-
NC
G2
C3
A3
G3
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
ICL7106, ICL7107, ICL7107S (PDIP)
TOP VIEW
ICL7106, ICL7107, ICL7107S
ICL7106, ICL7107 (MQFP)
TOP VIEW
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2
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
Absolute Maximum Ratings Thermal Information
Supply Voltage
ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
ICL7107, V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V
Analog Input Voltage (Either Input) (Note 6
Reference Input Voltage (Either Input). . . . . . . . . . . . . . . . . . . . . . . . V+ to V-
Clock Input
ICL7106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+
ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+
) . . . . . . . . . . . . . . . . . . . V+ to V-
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.
7.
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications (Note 8)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PERFORMANCE
Zero Input Reading V
Stability (Last Digit) (ICL7107S Only) Fixed input voltage (Note 11
Ratiometric Reading V
Rollover Error -V
Linearity Full scale = 200mV or full scale = 2V maximum deviation
Common Mode Rejection Ratio V
Noise V
Leakage Current Input V
Zero Reading Drift V
Scale Factor Temperature Coefficient V
End Power Supply Character V+ Supply Current V
End Power Supply Character V- Supply Current ICL7107 Only - 0.6 1.8 mA
COMMON Pin Analog Common Voltage 25kΩ between common and positive supply (with respect
Temperature Coefficient of Analog Common 25kΩ between common and positive supply (with respect
DISPLAY DRIVER ICL7106 ONLY
Peak-to-Peak Segment Drive Voltage
Peak-to-Peak Backplane Drive Voltage
= 0.0V, full scale = 200mV -000.0 000.0 +000.0 Digital
IN
= V
lN
Difference in reading for equal positive and negative inputs
near full scale
from best straight line fit (Note 10
CM
IN
(peak-to-peak value not exceeded 95% of time)
lN
lN
IN
(ext. ref. 0ppm/× °C) (Note 10)
IN
to + supply)
to + supply)
V+ = to V- = 9V (Note 9
, V
REF
REF
= +VlN 200mV
IN
= 1V, VIN = 0V, full scale = 200mV (Note 10) - 50 - µV/V
= 0V, full scale = 200mV
= 0 (Note 10)-110pA
= 0, 0°C to +70°C (Note 10) - 0.2 1 µV/°C
= 199mV, 0°C to +70°C,
= 0 (does not include LED current for ICL7107) - 1.0 1.8 mA
Thermal Resistance (Typical)
PDIP Package (Note 7
MQFP Package (Note 7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile (MQFP Package only) . . . . . . . . . . . . . . . see TB493
NO TE: Pb-f ree PDI Ps c an be use d fo r th rou gh h ole wave sold er p roc ess ing
only. They are not intended for use in Reflow solder processing
applications.
) -000.0 000.0 +000.0 Digital
= 100mV 999 999/1000 1000 Digital
)
) 4 5.5 6 V
) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
) . . . . . . . . . . . . . . . . . . . . . . . . . 75
- ±0.2 ±1 Counts
- ±0.2 ±1 Counts
-15 -µV
-15ppm/°C
2.4 3.0 3.2 V
-80 -ppm/°C
(oC/W)
JA
Reading
Reading
Reading
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3
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
13
123456789
101112
14151617181920
28
4039383736353433323130
29
27262524232221
V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COM
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+ -
IN
R
5
R
2
9V
ICL7106
C1 = 0.1µF
C
2
= 0.47µF
C
3
= 0.22µF
C4 = 100pF
C
5
= 0.02µF
R1 = 24kΩ
R
2
= 47kΩ
R3 = 100kΩ
R
4
= 1kΩ
R5 = 1MΩ
+
-
13
123456789
101112
14151617181920
28
4039383736353433323130
29
27262524232221
V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3
E3
AB4
POL
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
+
C
REF
-
COM
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
GND
DISPLAY
DISPLAY
C
1
C
2
C
3
C
4
R
3
R
1
R
4
C
5
+ -
IN
R
5
R
2
ICL7107
+5V -5V
C1 = 0.1µF
C
2
= 0.47µF
C3 = 0.22µF
C
4
= 100pF
C5 = 0.02µF
R
1
= 24kΩ
R
2
= 47kΩ
R
3
= 100kΩ
R
4
= 1kΩ
R5 = 1MΩ
Electrical Specifications (Note 8) (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DISPLAY DRIVER ICL7107 ONLY
Segment Sinking Current V+ = 5V, segment voltage = 3V
Except Pins AB4 and POL 5 8 - mA
Pin AB4 Only 10 16 - mA
Pin POL Only 47 -mA
NOTES:
8. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at T
Figure 1
. ICL7107 is tested in the circuit of Figure 2.
9. Back plane drive is in phase with segment drive for “off” segment, 180 degrees out of phase for “on” segment. Frequency is 20 times conversion rate.
Average DC component is less than 50mV.
10. Limit is not production tested. The maximum was established via characterization and/or design simulations.
11. Sample tested.
= +25°C, f
A
= 48kHz. ICL7106 is tested in the circuit of
CLOCK
Typical Applications and Test Circuits
FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
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FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
R
INT
V
INFS
I
INT
-----------------=
C
INT
t
INT
I
INT
V
INT
--------------------------------=
V
INT
t
INT
I
INT
C
INT
--------------------------------=
COUNT 1000
V
IN
V
REF
---------------=
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DEINTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x t
CLOCK
= 16,000 x t
OSC
Design Information Summary Sheet
• OSCILLATOR FREQUENCY
f
= 0.45/RC
OSC
C
> 50pF; R
OSC
f
(Typ) = 48kHz
OSC
• OSCILLATOR PERIOD
t
= RC/0.45
OSC
• INTEGRATION CLOCK FREQUENCY
f
= f
CLOCK
OSC
• INTEGRATION PERIOD
= 1000 x (4/f
t
INT
• 60/50Hz REJECTION CRITERION
t
INT/t60Hz
or t
• OPTIMUM INTEGRATION CURRENT
I
= 4µA
INT
• FULL SCALE ANALOG INPUT VOLTAGE
(Typ) = 200mV or 2V
V
lNFS
• INTEGRATE RESISTOR
• INTEGRATE CAPACITOR
• INTEGRATOR OUTPUT VOLTAGE SWING
MAXIMUM SWING:
•V
INT
(V- + 0.5V) < V
> 50kΩ
OSC
/4
)
OSC
lNT/t60Hz
< (V+ - 0.5V), V
INT
= Integer
(Typ) = 2V
INT
• DISPLAY COUNT
•CONVERSION CYCLE
t
= t
CYC
t
= t
CYC
when f
CL0CK
x 16,000
OSC
= 48kHz; t
OSC
x 4000
= 333ms
CYC
• COMMON MODE INPUT VOLTAGE
(V- + 1V) < VlN < (V+ - 0.5V)
•AUTO-ZERO CAPACITOR
0.01µF < C
AZ
< 1µF
• REFERENCE CAPACITOR
0.1µF < C
•V
COM
REF
< 1µF
Biased between Vi and V-.
•V
V+ - 2.8V
COM
Regulation lost when V+ to V- < 6.8V
If V
is externally pulled down to (V+ to V-)/2,
COM
the V
circuit will turn off.
COM
• ICL7106 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
V+ - 4.5V
V
GND
• ICL7106 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude.
• ICL7107 POWER SUPPLY: DUAL ±5.0V
V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND
Typical Integrator Amplifier Output Waveform (INT Pin)
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5
• ICL7107 DISPLAY: LED
Type: Nonmultiplexed Common Anode
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
DISPLAY COUNT = 1000
V
IN
V
REF
---------------
(EQ. 1)
FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107
DE-DE+
C
INT
C
AZ
R
INT
BUFFER
A-Z INT
-
+
A-Z
COMPARATOR
IN HI
COMMON
IN LO
31
32
30
DE- DE+
INT
A-Z
34
C
REF
+
36
REF HI
C
REF
REF LO
35
A-Z A-Z
33
C
REF
-
28 29 27
TO
DIGITAL
SECTION
A-Z AND DE(±)
INTEGRATOR
INT
STRAY STRAY
V+
10A
V-
N
INPUT
HIGH
2.8V
6.2V
V+
1
INPUT
LOW
-
+
-
+
-
+
Detailed Description
Analog Section
Figure 3 shows the analog section for the ICL7106 and ICL7107.
Each measurement cycle is divided into three phases. They are
(1) auto-zero (A-Z), (2) signal integrate (INT) and (3) deintegrate
(DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and low are
disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor C
offset voltages in the buffer amplifier, integrator, and comparator.
Since the comparator is included in the loop, the A-Z accuracy is
limited only by the noise of the system. In any case, the offset
referred to the input is less than 10µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the internal
short is removed, and the internal input high and low are connected
to the external pins. The converter then integrates the differential
voltage between IN HI and IN LO for a fixed time. This differential
voltage can be within a wide common mode range: up to 1V from
either supply. If, on the other hand, the input signal has no return
with respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.
Deintegrate Phase
The final phase is deintegrate, or reference integrate. Input low is
internally connected to analog COMMON and input high is
connected across the previously charged reference capacitor.
Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator output
to compensate for
AZ
to return to zero. The time required for the output to return to zero
is proportional to the input signal. Specifically the digital reading
displayed is:
Differential Input
The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from
0.5V below the positive supply to 1V above the negative supply. In
this range, the system has a CMRR of 86dB typical. However, care
must be exercised to assure the integrator output does not
saturate. A worst case condition would be a large positive common
mode voltage with a near full scale negative differential input
voltage. The negative input signal drives the integrator positive
when most of its swing has been used up by the positive common
mode voltage. For these critical applications the integrator output
swing can be reduced to less than the recommended 2V full scale
swing with little loss of accuracy. The integrator output can swing
to within 0.3V of either supply without loss of linearity.
Differential Reference
The reference voltage can be generated anywhere within the power
supply voltage of the converter. The main source of common mode
error is a roll-over voltage caused by the reference capacitor losing or
gaining charge to stray capacity on its nodes. If there is a large
common mode voltage, the reference capacitor can gain charge
(increase voltage) when called up to deintegrate a positive signal but
lose charge (decrease voltage) when called up to deintegrate a
negative input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough in
comparison to the stray capacitance, this error can be held to less
than 0.5 count worst case. (see “
page 10.)
Component Value Selection” on
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6
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
ICL7106
V
REF LO
ICL7107
REF HI
V+
V-
6.8V
ZENER
I
Z
ICL7106
V
REF HI
REF LO
COMMON
V+
ICL8069
1.2V
REFERENCE
6.8kΩ
20kΩ
ICL7107
ICL7106
V+
BP
TEST
21
37
TO LCD
BACKPLANE
TO LCD
DECIMAL
POINT
1MΩ
FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
Analog COMMON
This pin is included primarily to set the common mode voltage
for battery operation (ICL7106) or for any system where the input
signals are floating with respect to the power supply. The
COMMON pin sets a voltage that is approximately 2.8V more
negative than the positive supply. This is selected to give a
minimum end-of-life battery voltage of about 6V. However,
analog COMMON has some of the attributes of a reference
voltage. When the total supply voltage is large enough to cause
the zener to regulate (>7V), the COMMON voltage will have a low
voltage coefficient (0.001%/V), low output impedance (15Ω),
and a temperature coefficient typically less than 80ppm/×°C.
The limitations of the on chip reference should also be recognized,
however. With the ICL7107, the internal heating which results from
the LED drivers can cause some degradation in performance. Due
to their higher thermal resistance, plastic parts are poorer in this
respect than ceramic. The combination of reference Temperature
Coefficient (TC), internal chip dissipation, and package thermal
resistance can increase noise near full scale from 25µV to
80µV
such as 1000 (20 segments on) to a low dissipation count such as
1111(8 segments on) can suffer by a count or more. Devices with
a positive TC reference may require several counts to pull out of an
over-range condition. This is because over-range is a low
dissipation mode, with the three least significant digits blanked.
Similarly, units with a negative TC may cycle between overrange
and a non-overrange count as the die alternately heats and cools.
All these problems are of course eliminated if an external
reference is used.
The ICL7106, with its negligible dissipation, suffers from none of
these problems. In either case, an external reference can easily
be added, as shown in Figure 4
Analog COMMON is also used as the input low return during
auto-zero and deintegrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system and is
taken care of by the excellent CMRR of the converter. However, in
some applications IN LO will be set at a fixed known voltage
(power supply common for instance). In this application, analog
COMMON should be tied to the same point, thus removing the
common mode voltage from the converter. The same holds true
for the reference voltage. If reference can be conveniently tied to
analog COMMON, it should be since this removes the common
mode voltage from the reference system.
Within the lC, analog COMMON is tied to an N-Channel FET that
can sink approximately 30mA of current to hold the voltage 2.8V
below the positive supply (when a load is trying to pull the
common line positive). However, there is only 10µA of source
current, so COMMON may easily be tied to a more negative
voltage thus overriding the internal reference.
. Also the linearity in going from a high dissipation count
P-P
.
FIGURE 4A.
FIGURE 4B.
FIGURE 4. USING AN EXTERNAL REFERENCE
TEST
The TEST pin serves two functions. On the ICL7106 it is coupled
to the internally generated digital supply through a 500Ω resistor.
Thus, it can be used as the negative supply for externally
generated segment drivers such as decimal points or any other
presentation the user may want to include on the LCD display.
Figures 5
load should be applied.
and 6 show such an application. No more than a 1mA
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7
The second function is a “lamp test”. When TEST is pulled high
(to V+) all segments will be turned on and the display should read
“1888”. The TEST pin will sink about 15mA under these
conditions.
CAUTION: In the lamp test mode, the segments have a constant DC
voltage (no square-wave). This may burn the LCD display if maintained for
extended periods.
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
ICL7106
V+
BP
TEST
DECIMAL
POINT
SELECT
CD4030
GND
V+
TO LCD
DECIMAL
POINTS
FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE
7
SEGMENT
DECODE
SEGMENT
OUTPUT
0.5mA
2mA
INTERNAL DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+
LCD PHASE DRIVER
LATCH
7
SEGMENT
DECODE
200
LOGIC CONTROL
INTERNAL
V
TH
= 1V
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
4
CLOCK
40 39 38
OSC 1
OSC 2
OSC 3
BACKPLANE
21
V+
TEST
V-
500Ω
37
26
6.2V
COUNTER
COUNTER COUNTER COUNTER
1
c
a
b
c
d
f
g
e
a
b
a
b
c
d
f
g
e
a
b
c
d
f
g
e
†
†
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
FIGURE 7. ICL7106 DIGITAL SECTION
Digital Section
Figures 7 and 8 show the digital section for the ICL7106 and
ICL7107, respectively. In the ICL7106, an internal digital ground
is generated from a 6V Zener diode and a large P-Channel source
follower. This supply is made stiff to absorb the relatively large
capacitive currents when the back plane (BP) voltage is switched.
The BP frequency is the clock frequency divided by 800. For three
readings/sec., this is a 60Hz square wave with a nominal
amplitude of 5V. The segments are driven at the same frequency
and amplitude and are in phase with BP when OFF, but out of
phase when ON. In all cases negligible DC voltage exists across
the segments.
Figure 8
ICL7106 except that the regulated supply and back plane drive
have been eliminated and the segment drive has been increased
from 2mA to 8mA, typical for instrument size common anode
LED displays. Since the 1000 output (pin 19) must sink current
from two LED segments, it has twice the drive capability or
16mA.
In both devices, the polarity indication is “on” for negative analog
inputs. If IN LO and IN HI are reversed, this indication can be
reversed also, if desired.
is the Digital Section of the ICL7107. It is identical to the
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8
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
7
SEGMENT
DECODE
TO
SEGMENT
0.5mA
8mA
DIGITAL GROUND
TYPICAL SEGMENT OUTPUT
V+
LATCH
7
SEGMENT
DECODE
LOGIC CONTROL
7
SEGMENT
DECODE
1000’s 100’s 10’s 1’s
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
DIGITAL
GROUND
4
CLOCK
40 39 38
OSC 1
OSC 2
OSC 3
V+
TEST
500Ω
COUNTER
COUNTER COUNTER COUNTER
1
V+
37
27
c
a
b
c
d
f
g
e
a
b
a
b
c
d
f
g
e
a
b
c
d
f
g
e
†
†
THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
FIGURE 8. ICL7107 DIGITAL SECTION
CLOCK
INTERNAL TO PART
40 39
38
GND ICL7107
4
CLOCK
INTERNAL TO PART
40 39
38
4
RC OSCILLATOR
R
C
TEST ICL7106
FIGURE 9B.
FIGURE 9. CLOCK CIRCUITS
FIGURE 9A.
System Timing
Figure 9 shows the clocking arrangement used in the ICL7106
and ICL7107. Two basic clocking arrangements can be used:
1. Figure 9A
2. Figure 9B
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000 counts),
reference deintegrate (0 to 2000 counts) and auto-zero (1000 to
3000 counts). For signals less than full scale, auto-zero gets the
unused portion of reference de-integrate. This makes a complete
measure cycle of 4,000 counts (16,000 clock pulses)
independent of input voltage. For three readings/second, an
oscillator frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,
1
/3kHz, etc., should be selected. For 50Hz rejection, oscillator
33
frequencies of 200kHz, 100kHz, 66
would be suitable. Note that 40kHz (2.5 readings/second) will
reject both 50Hz and 60Hz (also 400Hz and 440Hz).
. An external oscillator connected to pin 40.
. An R-C oscillator using all three pins.
2
/3kHz, 50kHz, 40kHz, etc.,
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9
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
f
0.45
RC
----------- For 48kHz Clock (3 Readings/sec),=
C 100pF.=
(EQ. 2)
ICL7107
V+
OSC 1
V-
OSC 2
OSC 3
GND
V+
V- = 3.3V
0.047
µF
10µF
+
-
1N914
1N914
CD4009
FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V
Component Value Selection
Integrating Resistor
Both the buffer amplifier and the integrator have a class A output
stage with 100µA of quiescent current. They can supply 4µA of
drive current with negligible nonlinearity. The integrating resistor
should be large enough to remain in this very linear region over
the input voltage range, but small enough that undue leakage
requirements are not placed on the PC board. For 2V full scale,
470kΩ is near optimum and similarly a 47kΩ for a 200mV scale.
Integrating Capacitor
The integrating capacitor should be selected to give the max imum
voltage swing that ensures tolerance buildup will not saturate the
integrator swing (approximately. 0.3V from either supply). In the
ICL7106 or the ICL7107, when the analog COMMON is used as a
reference, a nominal +2V full scale integrator swing is fine. For
the ICL7107 with +5V supplies and analog COMMON tied to
supply ground, a ±3.5V to +4V swing is nominal. For three
readings/second (48kHz clock) nominal values for C
0.22µF and 0.10µF, respectively. Of course, if different oscillator
frequencies are used, these values should be changed in inverse
proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is that it
must have a low dielectric absorption to prevent roll-over errors.
While other types of capacitors are adequate for this application,
polypropylene capacitors give undetectable errors at reasonable
cost.
Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on the
noise of the system. For 200mV full scale where noise is very
important, a 0.47µF capacitor is recommended. On the 2V scale,
a 0.047µF capacitor increases the speed of recovery from
overload and is adequate for noise on this scale.
lNT
are
Reference Voltage
The analog input required to generate full scale output (2000
counts) is: VlN = 2V
. Thus, for the 200mV and 2V scale, V
REF
REF
should equal 100mV and 1V, respectively. However, in many
applications where the A/D is connected to a transducer, there
will exist a scale factor other than unity between the input
voltage and the digital reading. For instance, in a weighing
system, the designer might like to have a full scale reading when
the voltage from the transducer is 0.662V. Instead of dividing the
input down to 200mV, the designer should use the input voltage
directly and select V
= 0.341V. Suitable values for integrating
REF
resistor and capacitor would be 120kΩ and 0.22µF. This makes
the system slightly quieter and also avoids a divider network on
the input. The ICL7107 with ±5V supplies can accept input
signals up to ±4V. Another advantage of this system occurs when
a digital reading of zero is desired for V
0. Temperature and
IN
weighing systems with a variable fare are examples. This offset
reading can be conveniently generated by connecting the voltage
transducer between IN HI and COMMON and the variable (or
fixed) offset voltage between COMMON and IN LO.
ICL7107 Power Supplies
The ICL7107 is designed to work from ±5V supplies. However, if a
negative supply is not available, it can be generated from the
clock output with 2 diodes, 2 capacitors, and an inexpensive lC.
Figure 10
an alternative.
In fact, in selected applications no negative supply is required.
The conditions to use a single +5V supply are:
1. The input signal can be referenced to the center of the
2. The signal is less than ±1.5V.
3. An external reference is used.
shows this application. See the ICL7660 datasheet for
common mode range of the converter.
Reference Capacitor
A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e., the
REF LO pin is not at analog COMMON) and a 200mV scale is
used, a larger value is required to prevent rollover error. Generally
1µF will hold the rollover error to 0.5 count in this instance.
Oscillator Components
For all ranges of frequency a 100kΩ resistor is recommended and
the capacitor is selected as shown in Equation 2
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10
:
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
100pF
TO PIN 1
SET V
REF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
1kΩ 22kΩ
IN
+
-
9V
47kΩ
0.22µF
0.47µF
TO BACKPLANE
TO DISPLAY
Values shown are for 200mV full scale, 3 readings/sec., floating supply
voltage (9V battery).
+
-
Values shown are for 200mV full scale, 3 readings/sec. IN LO may be
tied to either COMMON for inputs floating with respect to supplies, or
GND for single ended inputs. (See discussion in “
Analog COMMON” on
page 7.)
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
100pF
TO PIN 1
SET V
REF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
1kΩ 22kΩ
IN
+
-
47kΩ
0.22µF
0.47µF
TO DISPLAY
+5V
-5V
Typical Applications
The ICL7106 and ICL7107 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of
these A/D converters.
The following application notes contain very useful information
on understanding and applying this part and are available from
Intersil Corporation.
Typical Applications
Application Notes
NOTE # DESCRIPTION
AN016 “Selecting A/D Converters”
AN017 “The Integrating A/D Converter”
AN018 “Do’s and Don’ts of Applying A/D Converters”
AN023 “Low Cost Digital Panel Meter Designs”
AN046 “Building a Battery-Operated Auto Ranging DVM with the ICL7106”
1
AN052 “Tips for Using Single Chip 3
AN9609 “Overcoming Common Mode Range Issues When Using Intersil
Integrating Converters”
/2 Digit A/D Converters”
FIGURE 11. ICL7106 USING THE INTERNAL REFERENCE FIGURE 12. ICL7107 USING THE INTERNAL REFERENCE
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11
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
28
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38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V
-
G2
C3
A3
G3
GND
100pF
TO PIN 1
SET V
REF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
1kΩ 10kΩ
IN
+
47kΩ
0.47µF
TO DISPLAY
IN LO is tied to supply COMMON establishing the correct common mode
voltage. If COMMON is not shorted to GND, the input voltage may float with
respect to the power supply and COMMON acts as a pre-regulator for the
reference. If COMMON is shorted to GND, the input is single ended
(referred to supply GND) and the preregulator is overridden.
10kΩ
1.2V (ICL8069)
V
-
V +
-
0.22µF
Since low TC zeners have breakdown voltages ~ 6.8V, diode must be
placed across the total supply (10V). As in the case of Figure 12
, IN LO
may be tied to either COMMON or GND.
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
100pF
TO PIN 1
SET V
REF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
1kΩ 100kΩ
IN
+
-
47kΩ
0.22µF
0.47µF
TO DISPLAY
+5V
-5V
6.8V
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP/GND
100pF
TO PIN 1
SET V
REF
= 1V
0.1µF
0.01µF
1MΩ
100kΩ
25kΩ 24kΩ
IN
+
-
470kΩ
0.22µF
0.047µF
TO DISPLAY
V+
V-
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
100pF
TO PIN 1
SET V
REF
= 100mV
0.1µF
0.01µF
1MΩ
100kΩ
1kΩ 10kΩ
IN
+
-
47kΩ
0.22µF
0.47µF
TO DISPLAY
An external reference must be used in this application, since the voltage
between V+ and V- is insufficient for correct operation of the internal
reference.
15kΩ
1.2V (ICL8069)
+5V
Typical Applications (Continued)
FIGURE 13. ICL7107 WITH AN EXTERNAL BAND-GAP
REFERENCE (1.2V TYPE)
FIGURE 15. ICL7106 AND ICL7107: RECOMMENDED COMPONENT
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VALUES FOR 2V FULL SCALE
12
FIGURE 14. ICL7107 WITH ZENER DIODE REFERENCE
FIGURE 16. ICL7107 OPERATED FROM SINGLE +5V
October 24, 2014
FN3082.9
ICL7106, ICL7107, ICL7107S
28
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32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
GND
100pF
TO PIN 1
0.1µF
100kΩ
0.47µF
TO DISPLAY
The resistor values within the bridge are determined by the desired
sensitivity.
V+
0.22µF
47kΩ
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V -
G2
C3
A3
G3
BP
100pF
TO PIN 1
0.1µF
0.01µF
100kΩ
100kΩ 1MΩ
9V
47kΩ
0.22µF
0.47µF
TO BACKPLANE
TO DISPLAY
A silicon diode-connected transistor has a temperature coefficient of
about -2mV/°C. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a
000.0 reading. The sensor should then be placed in boiling water and
the scale-factor potentiometer adjusted for a 100.0 reading.
SCALE
FAC TOR
ADJUST
100kΩ 220kΩ
22kΩ
SILICON NPN
MPS 3704 OR
SIMILAR
ZERO
ADJUST
Typical Applications (Continued)
FIGURE 17. ICL7107 MEASURING RATIOMETRIC VALUES OF QUAD
LOAD CELL
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13
FIGURE 18. ICL7106 USED AS A DIGITAL CENTIGRADE
THERMOMETER
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
O/RANGE
U/RANGE
CD4023 OR
74C10
CD4077
TO LOGIC
V
CC
V+
TO
LOGIC
V-
GND
O/RANGE
U/RANGE
CD4023 OR
74C10
TO LOGIC
V
CC
+5V
V-
33kΩ
The LM339 is required to
ensure logic compatibility
with heavy display loading.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3
AB4
POL
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V-
G2
C3
A3
G3
BP
12kΩ
+
-
+
-
+
-
+
-
LM339
28
40
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38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C
REF
C
REF
COMMON
IN HI
IN LO
A-Z
BUFF
INT
V
-
G2
C3
A3
G3
BP
100pF
TO PIN 1
0.1µF
100kΩ
1kΩ 22kΩ
47kΩ
0.22µF
0.47µF
TO BACKPLANE
TO DISPLAY
Test is used as a common-mode reference level to ensure compatibility with most op amps.
10µF
9V
10µF
470kΩ
1µF
4.3kΩ
100pF
(FOR OPTIMUM BANDWIDTH)
1µF
10kΩ
10kΩ
1N914
1µF
0.22µF
5µF
CA3140
2.2MΩ
+
-
100kΩ
AC IN
SCALE FACTOR ADJUST
(V
REF
= 100mV FOR AC TO RMS)
+
-
Typical Applications (Continued)
FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND
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FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND
OVERRANGE SIGNAL FROM ICL7106 OUTPUTS
FIGURE 21. AC TO DC CONVERTER WITH ICL7106
14
OVERRANGE SIGNALS FROM ICL7107 OUTPUT
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
ICL7107
130Ω
130Ω
130Ω
LED
SEGMENTS
+5V
DM7407
Typical Applications (Continued)
FIGURE 22. DISPLAY BUFFERING FOR INCREASED DRIVE CURRENT
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
October 24, 2014 FN3082.9 Updated to the newest template.
Page 1:
Updated copyright area.
Ordering Information table - removed all non Pb-free parts (all obsolete: ICL7106CPL, ICL7106CM44, ICL7107CPL,
ICL7107RCPL, ICL7107RCPLZ, ICL7107SCPL, ICL7107CM44, ICL7107CM44T) and removed ICL7107RCPLZ (obsolete).
Page 2, Removed the PDIP pinout for the ICL7107R, as it is obsolete.
Page 4, Reworded Electrical Spec Note 9 (formerly note 5) from: "Not tested, guaranteed by design." to: "Limit is not
production tested. The maximum was established via characterization and/or design simulations."
Page 15, Added Revision History and About Intersil verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
For information regarding Intersil Corporation and its products, see www.intersil.com
15
.
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendicular to datum .
7. e
B
and eC are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)
40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC e
A
e
B
0.600 BSC 15.24 BSC 6
- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N40 409
NOTESMIN MAX MIN MAX
Rev. 0 12/93
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16
FN3082.9
October 24, 2014
ICL7106, ICL7107, ICL7107S
D
D1
E
E1
-A-
PIN 1
A2
A1
A
12o-16
o
12o-16
o
0o-7
o
0.40
0.016
MIN
L
0o MIN
PLANE
b
0.005/0.009
0.13/0.23
WITH PLATING
BASE METAL
SEATING
0.005/0.007
0.13/0.17
b1
-B-
e
0.008
0.20
A-B SD SCM
0.076
0.003
-C-
-D-
-H-
-C-
-H-
Metric Plastic Quad Flatpack Packages (MQFP)
Q44.10x10 (JEDEC MS-022AB ISSUE B)
44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.096 - 2.45 A1 0.004 0.010 0.10 0.25 A2 0.077 0.083 1.95 2.10 -
b 0.012 0.018 0.30 0.45 6
b1 0.012 0.016 0.30 0.40 -
D 0.515 0.524 13.08 13.32 3
D1 0.389 0.399 9.88 10.12 4, 5
E 0.516 0.523 13.10 13.30 3
E1 0.390 0.398 9.90 10.10 4, 5
L 0.029 0.040 0.73 1.03 -
N44 447
e 0.032 BSC 0.80 BSC -
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane .
4. Dimensions D1 and E1 to be determined at datum plane
.
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.
7. “N” is the number of terminal positions.
NOTESMIN MAX MIN MAX
Rev. 2 4/99
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17
October 24, 2014
FN3082.9
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