Intersil ICL7106CM44Z, ICL7106CPLZ, ICL7107CM44Z, ICL7107CPLZ, ICL7107SCPLZ Schematics

31/2 Digit, LCD/LED Display, A/D Converters

DATASHEET

ICL7106, ICL7107, ICL7107S

The Intersil ICL7106 and ICL7107 are high performance, low power, 3 decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED)

/2 digit A/D converters. Included are seven segment

Features

• Guaranteed zero reading for 0V input on all scales

• True polarity at zero for precise null detection

• 1pA typical input current

• True differential input and reference, direct display drive

- LCD ICL7106, LED lCL7107

display.

The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features auto zero to less than 10µV, zero drift of less than 1µV/°C, input bias current of 10pA (max) and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge

• Low noise - less than 15µV

• On-chip clock and reference

• Low power dissipation - typically less than 10mW

• No additional active circuits required

• Enhanced display stability

• Pb-free (RoHS compliant)

P-P

type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display.

Ordering Information

PART NUMBE R

(Note 2

)PART MARKING

ICL7106CPLZ ICL7106CPLZ 0 to 70 40 Ld PDIP (Note 3

ICL7106CM44Z (Note 4) ICL7106 CM44Z 0 to 70 44 Ld MQFP Q44.10x10

ICL7106CM44ZT (Notes 4

ICL7107CPLZ ICL7107CPLZ 0 to 70 40 Ld PDIP (Note 3

ICL7107SCPLZ ICL7107SCPLZ 0 to 70 40 Ld PDIP (Notes 1, 3) E40.6

ICL7107CM44Z (Note 4

ICL7107CM44ZT (Notes 4

NOTES:

1. “S” indicates enhanced stability.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

4. For Moisture Sensitivity Level (MSL), please see product information page for ICL7106 tech brief TB363

5. Please refer to TB347

, 5) ICL7106 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10

) ICL7107 CM44Z 0 to 70 44 Ld MQFP Q44.10x10

, 5) ICL7107 CM44Z 0 to 70 44 Ld MQFP Tape and Reel Q44.10x10

for details on reel specifications.

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free) PKG. DWG. #

) E40.6

, ICL7107, ICL7107S. For more information on MSL, please see

October 24, 2014 FN3082.9

1-888-INTERSIL or 1-888-468-3774

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

Pin Configurations

V+

(1000) AB4

POL

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V-

G2 (10’s)

BP/GND

(1’s)

(10’s)

(100’s)

(MINUS)

(100’s)

OSC 2

OSC 3

TEST

12 13 14 15 16 17

OSC 1

V+

A1 F1 G1 E1 D2 C2

2221201918

B2 A2 F2 E2 D3

AB4

POL

BP/GND

39 38 37 36 35 34

44 43 42 41 40

IN HI

IN LO

A-Z

BUFF

INT

V-

REF HI

REF LO

REF

COMMON

ICL7106, ICL7107, ICL7107S (PDIP)

TOP VIEW

ICL7106, ICL7107, ICL7107S

ICL7106, ICL7107 (MQFP)

TOP VIEW

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ICL7106, ICL7107, ICL7107S

Absolute Maximum Ratings Thermal Information

Supply Voltage

ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

ICL7107, V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

ICL7107, V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V

Analog Input Voltage (Either Input) (Note 6

Reference Input Voltage (Either Input). . . . . . . . . . . . . . . . . . . . . . . . V+ to V-

Clock Input

ICL7106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+

ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V+

) . . . . . . . . . . . . . . . . . . . V+ to V-

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

NOTES:

6. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

7. 

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications (Note 8)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SYSTEM PERFORMANCE

Zero Input Reading V

Stability (Last Digit) (ICL7107S Only) Fixed input voltage (Note 11

Ratiometric Reading V

Rollover Error -V

Linearity Full scale = 200mV or full scale = 2V maximum deviation

Common Mode Rejection Ratio V

Noise V

Leakage Current Input V

Zero Reading Drift V

Scale Factor Temperature Coefficient V

End Power Supply Character V+ Supply Current V

End Power Supply Character V- Supply Current ICL7107 Only - 0.6 1.8 mA

COMMON Pin Analog Common Voltage 25kΩ between common and positive supply (with respect

Temperature Coefficient of Analog Common 25kΩ between common and positive supply (with respect

DISPLAY DRIVER ICL7106 ONLY

Peak-to-Peak Segment Drive Voltage Peak-to-Peak Backplane Drive Voltage

= 0.0V, full scale = 200mV -000.0 000.0 +000.0 Digital

= V

Difference in reading for equal positive and negative inputs near full scale

from best straight line fit (Note 10

(peak-to-peak value not exceeded 95% of time)

(ext. ref. 0ppm/× °C) (Note 10)

to + supply)

V+ = to V- = 9V (Note 9

, V

REF

= +VlN  200mV

= 1V, VIN = 0V, full scale = 200mV (Note 10) - 50 - µV/V

= 0V, full scale = 200mV

= 0 (Note 10)-110pA

= 0, 0°C to +70°C (Note 10) - 0.2 1 µV/°C

= 199mV, 0°C to +70°C,

= 0 (does not include LED current for ICL7107) - 1.0 1.8 mA

Thermal Resistance (Typical) 

PDIP Package (Note 7

MQFP Package (Note 7

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile (MQFP Package only) . . . . . . . . . . . . . . . see TB493

NO TE: Pb-f ree PDI Ps c an be use d fo r th rou gh h ole wave sold er p roc ess ing only. They are not intended for use in Reflow solder processing applications.

) -000.0 000.0 +000.0 Digital

= 100mV 999 999/1000 1000 Digital

)

) 4 5.5 6 V

) . . . . . . . . . . . . . . . . . . . . . . . . . . 50

) . . . . . . . . . . . . . . . . . . . . . . . . . 75

- ±0.2 ±1 Counts

-15 -µV

-15ppm/°C

2.4 3.0 3.2 V

-80 -ppm/°C

(oC/W)

Reading

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ICL7106, ICL7107, ICL7107S

123456789

101112

14151617181920

4039383736353433323130

27262524232221

V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3

AB4

POL

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

REF

COM

IN HI

IN LO

A-Z

BUFF

INT

V-

DISPLAY

+ -

ICL7106

C1 = 0.1µF C

= 0.47µF

= 0.22µF C4 = 100pF C

= 0.02µF R1 = 24kΩ R

= 47kΩ R3 = 100kΩ R

= 1kΩ R5 = 1MΩ

123456789

101112

14151617181920

4039383736353433323130

27262524232221

V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3

AB4

POL

OSC 1

OSC 2

OSC 3

TEST

REF HI

REF LO

REF

COM

IN HI

IN LO

A-Z

BUFF

INT

V-

GND

DISPLAY

+ -

ICL7107

+5V -5V

C1 = 0.1µF C

= 0.47µF C3 = 0.22µF C

= 100pF C5 = 0.02µF R

= 24kΩ R

= 47kΩ R

= 100kΩ R

= 1kΩ R5 = 1MΩ

Electrical Specifications (Note 8) (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DISPLAY DRIVER ICL7107 ONLY

Segment Sinking Current V+ = 5V, segment voltage = 3V

Except Pins AB4 and POL 5 8 - mA

Pin AB4 Only 10 16 - mA

Pin POL Only 47 -mA

NOTES:

8. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at T

Figure 1

. ICL7107 is tested in the circuit of Figure 2.

9. Back plane drive is in phase with segment drive for “off” segment, 180 degrees out of phase for “on” segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV.

10. Limit is not production tested. The maximum was established via characterization and/or design simulations.

11. Sample tested.

= +25°C, f

= 48kHz. ICL7106 is tested in the circuit of

CLOCK

Typical Applications and Test Circuits

FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

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ICL7106, ICL7107, ICL7107S

INT

INFS

INT

-----------------=

INT

I

INT



INT

--------------------------------=

INT

I

INT



INT

--------------------------------=

COUNT 1000

REF

---------------=

AUTO ZERO PHASE

(COUNTS) 2999 - 1000

SIGNAL INTEGRATE

PHASE FIXED 1000 COUNTS

DEINTEGRATE PHASE

0 - 1999 COUNTS

TOTAL CONVERSION TIME = 4000 x t

CLOCK

= 16,000 x t

OSC

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

= 0.45/RC

OSC

> 50pF; R

OSC

(Typ) = 48kHz

OSC

• OSCILLATOR PERIOD

= RC/0.45

OSC

• INTEGRATION CLOCK FREQUENCY

= f

CLOCK

OSC

• INTEGRATION PERIOD

= 1000 x (4/f

INT

• 60/50Hz REJECTION CRITERION

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 4µA

INT

• FULL SCALE ANALOG INPUT VOLTAGE

(Typ) = 200mV or 2V

lNFS

• INTEGRATE RESISTOR

• INTEGRATE CAPACITOR

• INTEGRATOR OUTPUT VOLTAGE SWING

MAXIMUM SWING:

•V

INT

(V- + 0.5V) < V

> 50kΩ

OSC

)

OSC

lNT/t60Hz

< (V+ - 0.5V), V

INT

= Integer

(Typ) = 2V

INT

• DISPLAY COUNT

•CONVERSION CYCLE

= t

CYC

= t

CYC

when f

CL0CK

x 16,000

OSC

= 48kHz; t

OSC

x 4000

= 333ms

CYC

• COMMON MODE INPUT VOLTAGE

(V- + 1V) < VlN < (V+ - 0.5V)

•AUTO-ZERO CAPACITOR

0.01µF < C

< 1µF

• REFERENCE CAPACITOR

0.1µF < C

•V

COM

REF

< 1µF

Biased between Vi and V-.

•V

 V+ - 2.8V

COM

Regulation lost when V+ to V- < 6.8V If V

is externally pulled down to (V+ to V-)/2,

COM

the V

circuit will turn off.

COM

• ICL7106 POWER SUPPLY: SINGLE 9V

V+ - V- = 9V Digital supply is generated internally

 V+ - 4.5V

GND

• ICL7106 DISPLAY: LCD

Type: Direct drive with digital logic supply amplitude.

• ICL7107 POWER SUPPLY: DUAL ±5.0V

V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND

Typical Integrator Amplifier Output Waveform (INT Pin)

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• ICL7107 DISPLAY: LED

Type: Nonmultiplexed Common Anode

FN3082.9

October 24, 2014

ICL7106, ICL7107, ICL7107S

DISPLAY COUNT = 1000

REF

---------------







(EQ. 1)

FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107

DE-DE+

INT

BUFFER

A-Z INT

A-Z

COMPARATOR

IN HI

COMMON

IN LO

DE- DE+

INT

A-Z

REF

REF HI

REF

REF LO

A-Z A-Z

REF

28 29 27

TO DIGITAL SECTION

A-Z AND DE(±)

INTEGRATOR

INT

STRAY STRAY

V+

10A

V-

INPUT

HIGH

2.8V

6.2V

V+

INPUT LOW

Detailed Description

Analog Section

Figure 3 shows the analog section for the ICL7106 and ICL7107.

Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) deintegrate (DE).

Auto-Zero Phase

During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor C offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.

Deintegrate Phase

The final phase is deintegrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output

to compensate for

to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is:

Differential Input

The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from

0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.

Differential Reference

The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to deintegrate a positive signal but lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (see “

page 10.)

Component Value Selection” on

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