intersil HI9P0546-9Z DATA SHEET

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®

HI-546, HI-547, HI-548, HI-549

Data Sheet September 21, 2005

Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection

The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed r exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers.

Analog inputs can withstand constant 70V ±15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1kΩ of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521.

matching. Analog input levels may greatly

ON

levels with

P-P

FN3150.5

Features

• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70V

• No Channel Interaction During Overvoltage

• Guaranteed r

• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V

• Break-Before-Make Switching

• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V

• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns

• Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW

• Pb-Free Plus Anneal Available (RoHS Compliant)

Matching

ON

P-P

Applications

• Data Acquisition

• Industrial Controls

• Telemetry

For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HI-546, HI-547, HI-548, HI-549

Ordering Information

TEMP.

PART

NUMBER

PART

MARKING

HI1-0546-5 HI1-546-5 0 to 75 28 Ld CERDIP F28.6 HI1-0546-2 HI1-546-2 -55 to 125 28 Ld CERDIP F28.6 HI3-0546-5 HI3-546-5 0 to 75 28 Ld PDIP E28.6 HI4P0546-5 HI4P546-5 0 to 75 28 Ld PLCC N28.45 HI4P0546-5Z

HI4P546-5Z 0 to 75 28 Ld PLCC

(Note) HI9P0546-9** HI9P546-9 -40 to 85 28 Ld SOIC M28.3 HI9P0546-9Z**

HI9P546-9Z -40 to 85 28 Ld SOIC

(Note) HI1-0547-5 HI1-547-5 0 to 75 28 Ld CERDIP F28.6 HI3-0547-5 HI3-547-5 0 to 75 28 Ld PDIP E28.6 HI3-0547-5Z

HI3-0547-5Z 0 to 75 28 Ld PDIP*

(Note) HI4P0547-5 HI4P547-5 0 to 75 28 Ld PLCC N28.45 HI4P0547-5Z

HI4P547-5Z 0 to 75 28 Ld PLCC

(Note) HI9P0547-9 HI9P547-9 -40 to 85 28 Ld SOIC M28.3 HI9P0547-9Z

HI9P547-9Z -40 to 85 28 Ld SOIC

(Note) HI1-0548-2 HI1-548-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0548-5 HI1-548-5 0 to 75 16 Ld CERDIP F16.3 HI3-0548-5 HI3-548-5 0 to 75 16 Ld PDIP E16.3 HI4P0548-5 HI4P548-5 0 to 75 20 Ld PLCC N20.35

RANGE

o

(

C) PACKAGE

(Pb-free)

PKG.

DWG. #

N28.45

M28.3

E28.6

N28.45

M28.3

Ordering Information (Continued)

TEMP.

PART

NUMBER

PART

MARKING

RANGE

o

(

C) PACKAGE

HI9P0548-5** HI9P548-5 0 to 75 16 Ld SOIC M16.15 HI9P0548-5Z**

(Note)

HI9P548-5Z 0 to 75 16 Ld SOIC

(Pb-free) HI9P0548-9 HI9P548-9 -40 to 85 16 Ld SOIC M16.15 HI9P0548-9Z

(Note)

HI9P548-9Z -40 to 85 16 Ld SOIC

(Pb-free) HI1-0549-2 HI1-549-2 -55 to 125 16 Ld CERDIP F16.3 HI3-0549-5 HI3-549-5 0 to 75 16 Ld PDIP E16.3 HI4P0549-5 HI4P549-5 0 to 75 20 Ld PLCC N20.35 HI4P0549-5Z

(Note)

HI4P549-5Z 0 to 75 20 Ld PLCC

(Pb-free) HI9P0549-9 HI9P549-9 -40 to 85 16 Ld SOIC M16.15 HI9P0549-9Z

(Note)

HI9P549-9Z -40 to 85 16 Ld SOIC

(Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing applications.

**Add “96” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PKG.

DWG. #

M16.15

N20.35

M16.15

Pinouts

ADDRESS A

HI-546 (CERDIP, PDIP, SOIC)

TOP VIEW

+V

SUPPLY

NC

NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10

IN 9

GND

V

REF

1 2 3 4 5 6 7 8

9 10 11 12 13 14

3

HI-547 (CERDIP, PDIP, SOIC)

TOP VIEW

OUT A

OUT

28

-V

27

SUPPLY

26

IN 8

25

IN 7

24

IN 6 IN 5

23

IN 4

22

IN 3

21 20

IN 2 IN 1

19

ENABLE

18

ADDRESS A

17 16

ADDRESS A ADDRESS A

15

+V

SUPPLY

0 1 2

OUT B

NC IN 8B IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B

GND

V

REF

NC

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28

-V

27

SUPPLY

IN 8A

26

IN 7A

25

IN 6A

24 23

IN 5A IN 4A

22 21

IN 3A

20

IN 2A

19

IN 1A ENABLE

18

ADDRESS A

17 16

ADDRESS A ADDRESS A

15

0 1 2

2

Pinouts (Continued)

HI-546 (PLCC)

TOP VIEW

HI-546, HI-547, HI-548, HI-549

HI-547 (PLCC)

TOP VIEW

IN 15 IN 14 IN 13 IN 12 IN 11 IN 10

IN 9

IN 16NCNC

5 6 7 8

9 10 11

12 13 14 15 16 17 18

A3A2A

REF

GND

V

HI-548 (CERDIP, PDIP, SOIC)

TOP VIEW

1

A

0

IN 1 IN 2 IN 3 IN 4

OUT

2 3 4 5 6 7 8

ENABLE

-V

SUPPLY

+V

1234

OUT

1

SUPPLY

-V

IN 8

262728

5

25

IN 7

24

IN 6

23

IN 5

22

IN 4

21

IN 3

20

IN 2

19

IN 1

0

A

ENABLE

IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B

6 7 8

9 10 11

IN 8B

NC

12 13 14 15 16 17 18

GND

V

SUPPLY

OUT B

+V

1234

2A1

A

NC

REF

SUPPLY

OUT A

-V

IN 8A

262728

25

IN 7A

24

IN 6A

23

IN 5A

22

IN 4A

21

IN 3A

20

IN 2A

19

IN 1A

0

A

ENABLE

HI-549 (CERDIP, PDIP, SOIC)

TOP VIEW

A

16

1

A

15

2

14

GND +V

13

SUPPLY

12

IN 5

11

IN 6

10

IN 7

9

IN 8

ENABLE

-V

SUPPLY

A

IN 1A IN 2A IN 3A IN 4A

OUT A

1

0

2 3 4 5 6 7 8

16 15 14 13 12 11 10

9

A

1

GND +V

SUPPLY

IN 1B IN 2B IN 3B IN 4B OUT B

-V

SUPPLY

IN 1

NC IN 2 IN 3

HI-548 (PLCC)

TOP VIEW

ENABLE

A0NC

4 5 6 7 8

9

10 11 12 13

IN 4

NC

OUT

A1A

193 2 201

IN 8

2

IN 7

-V

18

GND

17

+V

SUPPLY

16

NC

15

IN 5

14

IN 6

SUPPLY

IN 1A

NC IN 2A IN 3A

4 5 6 7 8

HI-549 (PLCC)

TOP VIEW

ENABLE

A0NC

9

10 11 12 13

IN 4A

NC

OUT A

A1GND

193 2 201

IN 4B

OUT B

+V

18

SUPPLY

IN 1B

17

NC

16

IN 2B

15 14

IN 3B

3

HI-546, HI-547, HI-548, HI-549

TRUTH TABLE HI-546

A

3

A

2

A

1

EN “ON” CHANNEL

0

XXXXL None LLLLH 1 LLLHH 2 LLHLH 3 LLHHH 4 LHLLH 5 LHLHH 6 LHHLH 7 LHHHH 8 HLLLH 9 HLLHH 10 HLHLH 11 HLHHH 12 HHL LH 13 HHLHH 14 HHHLH 15 HHHHH 16

TRUTH TABLE HI-547

A

2

A

1

EN “ON” CHANNEL PAIR

0

X X X L None LLLH 1 LLHH 2 LHLH 3 LHHH 4

TRUTH TABLE HI-547 (Continued)

A

2

A

1

EN “ON” CHANNEL PAIR

0

HLLH 5 HLHH 6 HHLH 7 HHHH 8

TRUTH TABLE HI-548

A

2

A

1

EN “ON” CHANNEL

0

X X X L None LLLH 1 LLHH 2 LHLH 3 LHHH 4 HLLH 5 HLHH 6 HHLH 7 HHHH 8

TRUTH TABLE HI-549

A

1

A

0

EN “ON” CHANNEL PAIR

X X L None LLH 1 LHH 2 HLH 3 HHH 4

Functional Diagrams

HI-546 HI-547

IN 1

IN 2

IN 16

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

† DIGITAL INPUT

PROTECTION

5V

REF

V

REFA0A1A2

4

DECODER/

DRIVER

LEVEL SHIFT

† † † †

EN

OUT

A

OUT

B

†

OUT

IN 1A

IN 8A IN 1B

IN 8B

†

EN

A

3

1K

1K 1K

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

† DIGITAL INPUT

PROTECTION

5V

REF

DECODER/

DRIVER

LEVEL

SHIFT

† † †

V

REFA0A1A2

Functional Diagrams (Continued)

HI-548 HI-549

HI-546, HI-547, HI-548, HI-549

IN 1

IN 2

IN 8

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

5V

REF

† DIGITAL INPUT

PROTECTION

Schematic Diagrams

EN

OUT

A

OUT

B

†

DECODER/

DRIVER

LEVEL SHIFT

† † †

A

0A1A2

EN

OUT

IN 1A

IN 4A IN 1B

IN 4B

†

1K

1K 1K

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

† DIGITAL INPUT

PROTECTION

5V

REF

DECODER/

DRIVER

LEVEL

SHIFT

† †

A

0

A

1

ADDRESS DECODER

V+

P

PP PP P P

A3 OR A

ENABLE DELETE A

DELETE A

OR A

A

0

A1 OR A

1

A2 OR A

2

3

OR A3 INPUT FOR HI-547, HI-548, HI-549

3

OR A2 INPUT FOR HI-549

2

TO P-CHANNEL

N

0

N

NN

V-

DEVICE OF THE SWITCH

TO N-CHANNEL DEVICE OF THE SWITCH

5

Schematic Diagrams (Continued)

FROM

DECODE

OVERVOLTAGE PROTECTION

HI-546, HI-547, HI-548, HI-549

MULTIPLEX SWITCH

N

V+

IN

FROM

DECODE

R11

1K

P

D6 D7

Q6

Q5

D4 D5

N

V-

N

P

OUT

6

Schematic Diagrams (Continued)

TTL REFERENCE

CIRCUIT

V+

R10

R9

V

REF

Q1

Q4

D3

GND

HI-546, HI-547, HI-548, HI-549

ADDRESS INPUT BUFFER AND LEVEL SHIFTER

LEVEL SHIFTER

V+

OVERVOLTAGE

PROTECTION

V+

D2

R1

D1

200

Ω

V-

ADD

IN

P

N

P

R2

R3

N

R4

GND

P

N

P P

N

P

R5 R7

R6 N

R8

N

P

N

V-

P

LEVEL SHIFTED ADDRESS TO DECODE

N

7

HI-546, HI-547, HI-548, HI-549

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V

V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V

Digital Input Voltage (V Analog Signal (V

IN

, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V

EN

, V

). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V

OUT

or 20mA, Whichever Occurs First

Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max). . 40mA

Operating Conditions

Temperature Ranges

HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55

HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0

HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

JA

o

C to 125oC

o

C to 75oC

o

C to 85oC

Thermal Resistance (Typical, Note 1) θ

(oC/W) θJC (oC/W)

JA

16 Ld CERDIP Package. . . . . . . . . . . 85 32

28 Ld CERDIP Package. . . . . . . . . . . 55 18

28 Ld PDIP Package*. . . . . . . . . . . . . 60 N/A

16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A

28 Ld PLCC Package. . . . . . . . . . . . . 70 N/A

20 Ld PLCC Package. . . . . . . . . . . . . 80 N/A

28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A

16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A

Maximum Junction Temperature

Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

o

C to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

o o

o

(PLCC, SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

C C

C

Electrical Specifications Supplies = +15V, -15V; V

Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless

REF

Otherwise Specified. For Test Conditions, Consult Test Circuits Section

-2 -5, -9 UNITSMIN TYP MAX MIN TYP MAX

PARAMETER

TEST

CONDITIONS

TEMP

o

(

C)

SWITCHING CHARACTERISTICS

Access Time, t

A

25 - 0.5 - - 0.5 - µs

Full - - 1.0 - - 1.0 µs Break-Before Make Delay, t Enable Delay (ON), t

ON(EN)

OPEN

25 25 80 - 25 80 - ns 25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns Enable Delay (OFF), t

OFF(EN)

25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns Settling Time To 0.1% 25 - 1.2 - - 1.2 - µs

To 0.01% 25 - 3.5 - - 3.5 - µs Off Isolation Note 6 25 50 68 - 50 68 - dB Channel Input Capacitance, C Channel Output Capacitance C

S(OFF)

D(OFF)

25-10- -10-pF

HI-546 25 - 52 - - 52 - pF HI-547 25 - 30 - - 30 - pF HI-548 25 - 25 - - 25 - pF HI-549 25 - 12 - - 12 - pF

Input to Output Capacitance, C

DS(OFF)

25 - 0.1 - - 0.1 - pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, TTL Drive, V Input High Threshold, V MOS Drive, V

(HI-546/547 Only) V

AL

(Note 8) Full 4.0 - - 4.0 - - V

AH

AL

= 10V 25 - - 0.8 - - 0.8 V

REF

Full - - 0.8 - - 0.8 V

8