Intersil Corporation HI5905N, HI5905QML Datasheet

TM

HI5905N/QML

Data Sheet July 1999

14-Bit, 5 MSPS, Military A/D Converter

The HI5905N/QML is a monolithic, 14-bit, 5MSPS Analog­to-Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power consumption
and excellent SINAD performance are essential. With a
100MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many Military types of
communication systems employing digital IF architectures.

The HI5905N/QMLis designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). Consuming 350mW (typ)
power at 5MSPS, the HI5905N/QML has excellent dynamic
performance over the full Military temperature range.

Data output latches are provided which present valid data to
the output bus with a data latency of only 4 clock cycles.

Specifications for QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.

Detailed Electrical Specifications for the HI5905N/QML
are contained in SMD 5962-98591. That document may
be easily downloaded from our website.
http://www.Intersil.com/data/sm/index.htm

Pinout

HI5905 (MQFP) (MO-108AA-2 ISSUE A)

TOP VIEW

File Number 4718.1

Features

• QML Compliant per SMD 5962-9859101NXB

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS

• Low Power at 5MSPS. . . . . . . . . . . . . . . . . 400mW (Max)

• Internal Sample and Hold

• Fully Differential Architecture

• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz

• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . >69dB (Min)

• Internal Voltage Reference

• TTL Compatible Clock Input

• CMOS Compatible Digital Data Outputs

Applications

• Digital Communication Systems

• Undersampling Digital IF

• Asymmetric Digital Subscriber Line (ADSL)

• Document Scanners

• Reference Literature

- AN9214, Using Intersil High Speed A/D Converters

- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board

Ordering Information

D

NC
NC

GND1

NC
AV
A

GND

NC

NC

V

IN+

V

V

CC

IN-

DC

CC1

CC1

GND1

NC

DV

DV

D

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

NC

RIN

GND

V

ROUT

A

V

4-1

CLKNCD0D1D2NCNC

39 38 37 36 35 34

CC

NC

D13

AV

D12

D11

2221201918

D10

33
32
31
30
29

28
27
26
25
24
23

NC

ORDERING

NUMBER

INTERNAL INTERSIL

MKT. NUMBER

TEMP.

RANGE(oC)

5962-9859101NXB HI5905N/QML -55 to 125
HI5905EVAL2 Low Frequency Platform 25

D3
D4
D5
D6
D7
NC
DV

CC2

D

GND2

D8
D9
NC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-724-7143

| Copyright © Intersil Corporation 1999

Functional Block Diagram

V

DC

V

IN

VIN+

-

BIAS

S/H

CLOCK

REF

CLK

V

ROUT

V

RIN

STAGE 1

DV

CC2

X8

4-BIT

FLASH

+

-

∑

4-BIT

DAC

D13 (MSB)
D12
D11
D10
D9

STAGE 4

D8
D7

X8

AND

4-BIT

FLASH

4-BIT

DAC

+

-

∑

DIGITAL DELAY

DIGITAL ERROR CORRECTION

D6
D5
D4
D3
D2
D1
D0 (LSB)

STAGE 5

AV

CCAGNDDVCC1DGND1

Typical Application Schematic

+

V

IN

VIN-

CLOCK

+5V

10µF

+

0.1µF

4-BIT

FLASH

V

ROUT

V

(14)

RIN

A

(6)

GND

A

(15)

GND

D

GND1

D

GND1

D

GND2

VIN+ (9)
VDC (11)
V

- (10)

IN

(MSB) D13 (18)

CLK (40)

AVCC (5)
AV

(16)

CC

(LSB) D0 (38)

D1 (37)

(13)

D2 (36)
D3 (33)
D4 (32)
D5 (31)

(3)

D6 (30)

(42)

D7 (29)

(26)

D8 (25)

D9 (24)
D10 (21)
D11 (20)
D12 (19)

DV

CC1

DV

(43)

CC1

(27)

DV

CC2

(41)

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13

0.1µF

D

GND2

D

GND

A

GND

BNC

10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE

+5V

+

10µF

4-2

HI5905

Timing Waveforms

ANALOG

INPUT

CLOCK

INPUT

S

N - 1HN - 1SN

INPUT

S/H

1ST

STAGE

2ND

STAGE

B2,

3RD

STAGE

4TH

STAGE

B4,

5TH

STAGE

DAT A

OUTPUT

NOTES:

1. SN: N-th sampling period.

2. HN: N-th holding period.

N - 2

N - 3

B1,

B3,

B

5, N - 3

D

N - 1

N - 2

N - 4

HNS

N + 1HN + 1SN + 2HN + 2SN + 3HN + 3SN + 4HN + 4SN + 5HN + 5SN + 6HN + 6

B2,

B4,

N - 1

N - 2

B

B3,

B5,

D

1, N

N - 1

N - 2

N - 3

B2,

B4,

t

LAT

N

N - 1

B

1, N + 1

B3,

B5,

D

N

N - 1

N - 2

B2,

B4,

N + 1

N

B

B3,

B5,

3. B

B

N + 2

N + 1

1, N + 3

B3,

B5,

D

N + 2

N + 1

N

1, N + 2

B2,

N + 1

B4,

N

D

N - 1

:M-thstage digital output corresponding to N-th sampledinput.

M, N

B2,

B4,

N + 3

N + 2

B

1, N + 4

B3,

B5,

D

B2,

N + 3

B4,

N + 2

N + 1

4. DN: Final data output corresponding to N-th sampled input.

FIGURE 1. INTERNAL CIRCUIT TIMING

N + 4

N + 3

B

1, N + 5

B3,

B5,

D

N + 4

N + 3

N + 2

ANALOG

INPUT

CLOCK

INPUT

DAT A

OUTPUT

4-3

1.5V

t

AP

t

AJ

1.5V

t

OD

t

H

3.5V

DATA N-1 DATA N

1.5V

FIGURE 2. INPUT-TO-OUTPUT TIMING