Intersil Corporation HI5865 Datasheet

Semiconductor

PRELIMINARY

June 1998

HI5865

12-Bit, 65 MSPS A/D Converter

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSPS

• Low Power at 65 MSPS . . . . . . . . . . . . . . . . . . . .450mW

• Internal Sample and Hold

• Fully Differential Architecture

• Full Power Input Bandwidth . . . . . . . . . . . . . . . 250MHz

• Low Data Latency

• TTL Compatible Clock Input

• CMOS Compatible Digital Data Outputs

Applications

• Multichannel Digital Communication Receivers

• Cellular/PCS Basestation Receivers

• Undersampling Digital IF

• Digital Subscriber Line (VDSL)

• Medical Ultrasound

• Reference Literature

- AN9214, Using Harris High Speed A/D Converters

Description

The HI5865 is a monolithic, 12-bit, 65 MSPS Analog-to­Digital Converter fabricated in an advanced CMOS
process. It is designed for high speed, high resolution appli­cations where wide bandwidth, low power consumption and
excellent SINAD performance are essential. With a
250MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many types of
communication systems employing digital IF architectures.

The HI5865 is designed with a fully differential pipelined
architecture using a front end differential-in-differential-out
Sample-and-Hold amplifier (S/H). The HI5865 has excellent
dynamic performance while consuming 450mW of power at
65 MSPS.

Data output latches are provided which present valid data to
the output bus with a low data latency of 9 clock cycles.

Ordering Information

TEMP.

PART NUMBER

HI5865IN -40 to 85 44 Ld MQFP Q44.10x10
HI5865EVAL1 25 Evaluation Platform

RANGE (oC) PACKAGE PKG. NO.

Pinout

DV
D
A
AV

A
AV

AV
A

GND1

CC
GND
GND

CC
GND

CC

CC1

V

IN-

V

IN+

V

DC

HI5865 (MQFP)

TOP VIEW

GNDDGNDDGND

CLK

D

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

CC1

REF-

REF+

GND1

V

V

DV

D

CC

GNDDGND

DV

D

39 38 37 36 35 34

CC2

GND2

DV

D

NC

GND3

D

NC

CC3

DV

D0

D11

2221201918

D1

NC

33
32
31
30
29

28
27
26
25
24
23

NC

D10
D9
D8
D7
D
DV
D6

D5
D4
D3

D2

GND

CC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 4538

HI5865

Metric Plastic Quad Flatpack Packages (MQFP/PQFP)

E

E1

0.40

0.016
0o MIN

0o-7

-H-

-A-

o

MIN

D

D1

-D-

Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

SYM-

BOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.093 - 2.35 -

A1 0.004 0.010 0.10 0.25 -

-B-

A2 0.077 0.083 1.95 2.10 -

B 0.012 0.018 0.30 0.45 6

B1 0.012 0.016 0.30 0.40 -

D 0.510 0.530 12.95 13.45 3

D1 0.390 0.398 9.90 10.10 4, 5

E 0.510 0.530 12.95 13.45 3

e

PIN 1

E1 0.390 0.398 9.90 10.10 4, 5

L 0.026 0.037 0.65 0.95 ­N44 447
e 0.032 BSC 0.80 BSC -

A

SEATING

PLANE

Rev. 1 1/94

NOTES:

0.10

o

5o-16

0.20

0.008

A2

A1

o

L

5o-16

0.005/0.007

BASE METAL

A-B SD SCM

0.13/0.17

WITH PLATING

0.004

-C-

B

B1

0.13/0.23

0.005/0.009

1. Controllingdimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. DimensionsD andE to bedetermined atseating plane .

-C-

4. Dimensions D1 and E1 to be determinedat datum plane

.

-H-

5. Dimensions D1 and E1 do notinclude mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.

6. DimensionB does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.

7. “N” is the number of terminal positions.

2