Intersil Corporation HI5810 Datasheet

August 1997

HI5810

CMOS 10 Microsecond, 12-Bit, Sampling

A/D Converter with Internal Track and Hold

Features

• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . .100 KSPS

• Built-In Track and Hold

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V

• Maximum Power Consumption. . . . . . . . . . . . . . .40mW

• Internal or External Clock

• 1MHz Input Bandwidth . . . . . . . . . . . . . . . . . . . . . -3dB

Applications

• Remote Low Power Data Acquisition Systems

• Digital Audio

• DSP Modems

• General Purpose DSP Front End

• µP Controlled Measurement Systems

• Process Controls

• Industrial Controls

Description

The HI5810 is a fast, low power, 12-bit, successiveapproximation, analog-to-digital conv erter. It can operate from a single 3V to 6V supply and typically draws just 1.9mA when operating at 5V. The HI5810 features a built-in track and hold. The conversion time is as low as 10µs with a 5V supply.

The twelve data outputs feature full high speed CMOS threestate bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: [i.e., 12-bit, 8-bit (MSBs), and/or 4-bit (LSBs)]. A data ready ﬂag, and conversion-start input complete the digital interface.

An internal clock is provided and is available as an output. The clock may also be over-driven by an external source.

Ordering Information

INL (LSB)

PART

NUMBER

HI5810JIP ±2.5 -40 to 85 24 Ld PDIP E24.3 HI5810KIP ±2.0 -40 to 85 24 Ld PDIP E24.3 HI5810JIB ±2.5 -40 to 85 24 Ld SOIC M24.3 HI5810KIB ±2.0 -40 to 85 24 Ld SOIC M24.3 HI5810JIJ ±2.5 -40 to 85 24 Ld CERDIP F24.3 HI5810KIJ ±2.0 -40 to 85 24 Ld CERDIP F24.3

(MAX OVER

TEMP.)

TEMP.

RANGE

(oC) PACKAGE

PKG.

NO.

Pinout

HI5810

(PDIP, CERDIP, SOIC)

TOP VIEW

DRDY

(LSB) D0

2 3

6-1777

V OEL

CLK

STRT

VAA-

OEM

D11 (MSB)

D10

REF REF IN AA

File Number 3633.1

Functional Block Diagram

HI5810

V V

REF

VAA-

STRT

DD SS

TO INTERNAL LOGIC

50Ω SUBSTRATE

64C

32C

16C

32C

16C

CONTROL

AND

TIMING

12-BIT

SUCCESSIVE

APPROXIMATION

12-BIT EDGE

TRIGGERED

“D” LATCHED

CLOCK

CLK

DRDY

OEM

D11 (MSB)

D10

REF

D0 (LSB)

OEL

6-1778

HI5810

Absolute Maximum Ratings Thermal Information

Supply Voltage

VDD to VSS . . . . . . . . . . . . . . . . . . . .(VSS -0.5V) < VDD < +6.5V

VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)

VAA+ to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

Analog and Reference Inputs

IN,VREF+,VREF

Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD+0.3V)

-. . . . . . . . . (VSS -0.3V) < V

< (VDD +0.3V)

INA

Operating Conditions

Temperature Range

PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . 60 12

PDIP Package. . . . . . . . . . . . . . . . . . . 80 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 75 N/A

Maximum Junction Temperature

Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Hermetic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Speciﬁcations V

PARAMETER

ACCURACY

Resolution 12 - - 12 - Bits Integral Linearity Error, INL

(End Point)

Differential Linearity Error, DNL J - - ±2.0 - ±2.0 LSB

Gain Error, FSE (Adjustable to Zero)

Offset Error, V (Adjustable to Zero)

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD

Signal to Noise Ratio, SNR

Total Harmonic Distortion, THD J fS = Internal Clock, fIN = 1kHz

Spurious Free Dynamic Range, SFDR J fS = Internal Clock, fIN = 1kHz

ANALOG INPUT

Input Current, Dynamic At VIN = V

RMS Signal

RMS Noise + Distortion

RMS Signal

RMS Noise

= VAA+ = 5V, V

Unless Otherwise Speciﬁed

J--±2.5 - ±2.5 LSB K--±2.0 - ±2.0 LSB

K--±2.0 - ±2.0 LSB J--±3.5 - ±3.5 LSB K--±2.5 - ±2.5 LSB J--±2.5 - ±2.5 LSB K--±1.5 - ±1.5 LSB

JfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

JfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

KfS = Internal Clock, fIN = 1kHz

fS = 1.5MHz, fIN = 1kHz

+ = +4.608V, VSS = VAA- = V

REF

TEST CONDITIONS

+, 0V - ±125 ±150 - ±150 µA

REF

- = GND, CLK = External 1.5MHz,

REF

25oC -40oC TO 85oC

MIN TYP MAX MIN MAX

- 68.8

62.1

- 71.0

63.6

- 70.5

63.2

- 71.5

65.0

- -73.9

-68.4

- -80.3

69.7

- 75.4

69.2

- 80.9

70.7

-- -dB

- - - dBc

-- -dB

UNITS

dBc

6-1779

HI5810

Electrical Speciﬁcations V

= VAA+ = 5V, V

+ = +4.608V, VSS = VAA- = V

REF

- = GND, CLK = External 1.5MHz,

REF

Unless Otherwise Speciﬁed (Continued)

25oC -40oC TO 85oC

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN MAX

UNITS

Input Current, Static Conversion Stopped - ±0.6 ±10 - ±10 µA

Input Bandwidth -3dB - 1 - - - MHz Reference Input Current - 160 - - - µA Input Series Resistance, R Input Capacitance, C Input Capacitance, C

SAMPLE HOLD

In Series with Input C

SAMPLE

- 420 - - - Ω During Sample State - 380 - - - pF During Hold State - 20 - - - pF

DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, V Low-Level Input Voltage, V Input Leakage Current, I Input Capacitance, C

Except CLK, VIN = 0V, 5V - - ±10 - ±10 µA

2.4 - - 2.4 - V

- - 0.8 - 0.8 V

-10- - - pF

DIGITAL OUTPUTS

High-Level Output Voltage, V Low-Level Output Voltage, V Three-State Leakage, I Output Capacitance, C

OUT

SOURCE

SINK

Except DRDY, V

= -400µA 4.6 - - 4.6 - V

= 1.6mA - - 0.4 - 0.4 V

= 0V, 5V - - ±10 - ±10 µA

OUT

Except DRDY - 20 - - - pF

CLOCK

High-Level Output Voltage, V Low-Level Output Voltage, V

SOURCE

SINK

= -100µA (Note 2) 4 - - 4 - V

= 100µA (Note 2) - - 1 - 1 V

Input Current CLK Only, VIN = 0V, 5V - - ±5- ±5mA

TIMING

Conversion Time (t

CONV

+ t

ACQ

)

10 - - 10 - µs

(Includes Acquisition Time) Clock Frequency Internal Clock, (CLK = Open) 200 300 400 150 500 kHz

External CLK (Note 2) 0.05 - 2.0 - - MHz

Clock Pulse Width, t

LOW

, t

HIGH

External CLK (Note 2) 100 - - 100 - ns

Aperture Delay, tDAPR (Note 2) - 35 50 - 70 ns Clock to Data Ready Delay, tD1DRDY (Note 2) - 105 150 - 180 ns Clock to Data Ready Delay, tD2DRDY (Note 2) - 100 160 - 195 ns Start Removal Time, tRSTRT (Note 2) 75 30 - 75 - ns Start Setup Time, tSUSTRT (Note 2) 85 60 - 100 - ns Start Pulse Width, tWSTRT (Note 2) 10 4 - 15 - ns Start to Data Ready Delay, tD3DRDY (Note 2) - 65 105 - 120 ns Clock Delay from Start, tDSTRT (Note 2) - 60 - - - ns Output Enable Delay, t Output Disabled Delay, t

DIS

(Note 2) - 20 30 - 50 ns (Note 2) - 80 95 - 120 ns

POWER SUPPLY CHARACTERISTICS

Supply Current, IDD + I

- 2.6 8 - 8.5 mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

6-1780

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