Intersil Corporation HI5746 Datasheet

HI5746

Data Sheet February 1999 File Number 4129.4

10-Bit, 40 MSPS A/D Converter

The HI5746 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a CMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40 MSPS speed is
made possible by a fully differential pipelined architecture
with an internal sample and hold.

The HI5746 has excellent dynamic performance while
consuming only 225mW power at 40 MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles. It is pin-for-pin
functionally compatible with the HI5702 and the HI5703.

For internal voltage reference, please refer to the HI5767
data sheet.

Ordering Information

PART

NUMBER

HI5746KCB 0 to 70 28 Ld SOIC (W) M28.3
HI5746KCA 0 to 70 28 Ld SSOP M28.15
HI5746EVAL1 25 Evaluation Board

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS

• 8.8 Bits at f

= 10MHz

IN

• Low Power at 40 MSPS . . . . . . . . . . . . . . . . . . . . 225mW

• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz

• On-Chip Sample and Hold

• Fully Differential or Single-Ended Analog Input

• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary or Two’s Complement Output Format

Applications

• Professional Video Digitizing

• Medical Imaging

• Digital Communication Systems

• High Speed Data Acquisition

Pinout

HI5746

(SOIC, SSOP)

TOP VIEW

70

1

DV

CC1

DV

CC1

AV

AGND

V

REF

V

REF

V

V
V

AGND

AV

CC

IN

IN
DC

CC

OE

2
3
4
5
6
7

+

8

­9

+

10

-

11
12
13
14

| Copyright © Intersil Corporation 1999

DGND1

DGND1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

28
27
26
25
24
23
22
21
20
19
18
17
16
15

D0
D1
D2
D3
D4
DV

CC2

CLK
DGND2
D5
D6
D7
D8
D9
DFS

Functional Block Diagram

HI5746

V

VIN-

V

DC

+

IN

S/H

2-BIT

FLASH

+

∑

-

X2

BIAS

STAGE 1

2-BIT

DAC

CLOCK

CLK

DFS

OE

DV

CC2

D9 (MSB)

D8

D7

X2

D6

STAGE 8

2-BIT

FLASH

+

∑

-

STAGE 9

2-BIT

FLASH

2-BIT

DAC

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

D5

D4

D3

D2

D1

D0 (LSB)

DGND2

AV

CC

71

AGND DV

CC1

DGND1 V

REF

+V

REF

- (OPTIONAL)

Typical Application Schematic

HI5746

HI5746

(OPTIONAL)

V

IN

VIN-

CLOCK

2.5V

2.0V

+

V

+ (7)

REF

V

- (8)

REF

(LSB) (28) D0

AGND (12)
AGND (6)

DGND1 (2)
DGND1 (4)
DGND2 (21)

(MSB) (16) D9

+ (9)

V

IN

VDC(11)
V

- (10)

IN

CLK (22)
DFS (15)
OE (14)

(27) D1
(26) D2
(25) D3
(24) D4
(20) D5
(19) D6
(18) D7
(17) D8

(1) DV
(3) DV

(23) DV

(13) AV

(5) AV

CC1

CC1
CC2

CC

CC

D0
D1
D2
D3

DGND AGND

D4
D5
D6
D7
D8
D9

0.1µF10µF

0.1µF

BNC

10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE

+5V

+

+5V

+

10µF

Pin Descriptions

PIN NO. NAME DESCRIPTION

1DV

CC1

2 DGND1 Digital Ground.
3DV

CC1

4 DGND1 Digital Ground.
5AVCCAnalog Supply (+5.0V).
6 AGND Analog Ground.
7V

8V

9V

REF

REF

IN

10 VIN- Negative Analog Input.
11 V

DC

12 AGND Analog Ground.
13 AV

CC

14 OE Digital Output Enable Control Input.

Digital Supply (+5.0V).

Digital Supply (+5.0V).

+ +2.5V Positive Reference Voltage

Input.

- +2.0V Negative Reference Voltage
Input (Optional).

+ Positive Analog Input.

DC Bias Voltage Output.

Analog Supply (+5.0V).

PIN NO. NAME DESCRIPTION

15 DFS Data Format Select Input.
16 D9 Data Bit 9 Output (MSB).
17 D8 Data Bit 8 Output.
18 D7 Data Bit 7 Output.
19 D6 Data Bit 6 Output.
20 D5 Data Bit 5 Output.
21 DGND2 Digital Ground.
22 CLK Sample Clock Input.
23 DV

CC2

Digital Output Supply

(+3.0V or +5.0V).
24 D4 Data Bit 4 Output.
25 D3 Data Bit 3 Output.
26 D2 Data Bit 2 Output.
27 D1 Data Bit 1 Output.
28 D0 Data Bit 0 Output (LSB).

72

HI5746

Absolute Maximum Ratings T

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

Operating Conditions

Temperature Range

HI5746KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 10 - - Bits
Integral Linearity Error, INL fIN = DC - ±1.0 ±2.0 LSB
Differential Linearity Error, DNL

(Guaranteed No Missing Codes)

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

CC
CC

= DV

CC

C

= 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,

L

Unless Otherwise Specified

= 5.0V; DV

CC1

= 3.0V, V

CC2

fIN = DC - ±0.5 ±1.0 LSB

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC, SSOP - Lead Tips Only)

+ = 2.5V; V

REF

- = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

REF

Offset Error, V
Full Scale Error, FSE fIN = DC - 4 - LSB

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes - 0.5 1 MSPS
Maximum Conversion Rate No Missing Codes 40 - - MSPS
Effective Number of Bits, ENOB fIN = 10MHz 8.55 8.8 - Bits
Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz 53.2 54.9 - dB

--------------------------------------------------------------=

RMS Noise + Distortion

Signal to Noise Ratio, SNR fIN = 10MHz 53.2 55.4 - dB

RMS Signal

-------------------------------=

RMS Noise

Total Harmonic Distortion, THD fIN = 10MHz - -64.6 - dBc
2nd Harmonic Distortion fIN = 10MHz - -67.8 - dBc
3rd Harmonic Distortion fIN = 10MHz - -68.3 - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz - 67.8 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - 64 - dBc
Differential Gain Error fS = 17.72 MSPS, 6 Step, Mod Ramp - 0.8 - %

OS

RMS Signal

fIN = DC -40 12 40 LSB

Differential Phase Error fS = 17.72 MSPS, 6 Step, Mod Ramp - 0.1 - Degree
Transient Response (Note 2) - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

73

HI5746

Electrical Specifications AV

CC

= DV

= 5.0V; DV

CC1

CC2

= 3.0V, V

+ = 2.5V; V

REF

- = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

REF

CL= 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

- ±0.5 - V

Range (VIN+ - VIN-)
Maximum Peak-to-Peak Single-Ended

- 1.0 - V

Analog Input Range
Analog Input Resistance, R
Analog Input Capacitance, C

IN

IN

(Note 3) - 1 - MΩ

-10-pF
Analog Input Bias Current, IB+ or IB- (Note 3) -10 - +10 µA
Differential Analog Input Bias Current

I

= (IB+- IB-)

BDIFF

(Note 3) - ±0.5 - µA

Full Power Input Bandwidth, FPBW - 250 - MHz
Analog Input Common Mode Voltage Range

Differential Mode (Note 2) 0.25 - 4.75 V

(VIN++ VIN-)/2

REFERENCE INPUT

Total Reference Resistance, R
Positive Reference Current, I
Negative Reference Current, I

L

+ - 1.07 - mA

REF

REF

Positive Reference Voltage Input, V
Negative Reference Voltage Input, V
Reference Common Mode Voltage

(V

REF

++ V

REF

-)/2

- - 21 - µA
+ (Note 2) - 2.5 - V

REF

- (Note 2) - 2.0 - V

REF

V

+ to AGND - 2.5K - Ω

REF

(Note 2) - 2.25 - V

DC BIAS VOLTAGE

DC Bias Voltage Output, V

DC

- 3.2 - V

Maximum Output Current - - 0.4 mA

DIGITAL INPUTS

Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic High Current, I
Input Logic Low Current, I
Input Capacitance, C

IN

IH

IL

IH

IL

CLK, DFS, OE 2.0 - - V
CLK, DFS, OE - - 0.8 V
CLK, DFS, OE, VIH= 5V -10.0 - +10.0 µA
CLK, DFS, OE, VIL= 0V -10.0 - +10.0 µA

-7-pF

DIGITAL OUTPUTS

Output Logic High Voltage, V
Output Logic Low Voltage, V

OH

OL

Output Three-State Leakage Current, I
Output Logic High Voltage, V
Output Logic Low Voltage, V

OH

OL

OZ

IOH= 100µA; DV
IOL= 100µA; DV
VO = 0/5V; DV
IOH= 100µA; DV
IOL= 100µA; DV

= 5V 4.0 - - V

CC2

= 5V - - 0.5 V

CC2

= 5V - ±1 ±10 µA

CC2

= 3V 2.4 - - V

CC2

= 3V - - 0.5 V

CC2

74

HI5746

Electrical Specifications AV

CC

= DV

= 5.0V; DV

CC1

CC2

= 3.0V, V

+ = 2.5V; V

REF

- = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

REF

CL= 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,
Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Three-State Leakage Current, I
Output Capacitance, C

OUT

OZ

VO = 0/5V; DV

= 3V - ±1 ±10 µA

CC2

-10-pF

TIMING CHARACTERISTICS

Aperture Delay, t
Aperture Jitter, t
Data Output Hold, t
Data Output Delay, t

AP

AJ

H

OD

Data Output Enable Time, t
Data Output Enable Time t
Data Latency, t

LAT

EN

DIS

For a Valid Sample (Note 2) - - 7 Cycles

-5-ns

-5-ps

RMS

-7-ns

-8-ns

-5-ns

-5-ns

Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV
Digital Supply Voltage DV

CC

CC1

Digital Output Supply Voltage, DV

CC2

At 3.0V 2.7 3.0 3.3 V

4.75 5.0 5.25 V

4.75 5.0 5.25 V

At 5.0V 4.75 5.0 5.25 V

Total Supply Current, I

CC

Analog Supply Current, AI
Digital Supply Current, DI
Output Supply Current, DI

CC

CC1

CC2

fIN = 10MHz and DFS = “0” - 46 - mA
fIN = 10MHz and DFS = “0” - 30 - mA
fIN = 10MHz and DFS = “0” - 13 - mA

fIN = 10MHz and DFS = “0” - 3 - mA
Power Dissipation fIN = 10MHz and DFS = “0” - 225 275 mW
Offset Error Sensitivity, ∆V

OS

AVCCor DVCC = 5V ±5% - ±0.4 - LSB
Gain Error Sensitivity, ∆FSE AVCC or DVCC= 5V ±5% - ±0.8 - LSB

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

75