Intersil Corporation HI5628 Datasheet
HI5628
Data Sheet July 1999 File Number 4520.3
8-Bit, 165/125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728. This DAC is
a member of the CommLink™ family of communication
devices.
Ordering Information
TEMP.
PART
NUMBER
RANGE
(oC) PACKAGE PKG. NO.
HI5628/16IN† -40 to 85 48 Ld LQFP Q48.7x7A 165MHz
HI5628IN -40 to 85 48 Ld LQFP Q48.7x7A 125MHz
HI5628/6IN -40 to 85 48 Ld LQFP Q48.7x7A 60MHz
HI5628EVAL1† 25 Evaluation Platform 125MHz
† Contact factory for availability.
MAX
CLOCK
SPEED
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Channel Isolation (Typ). . . . . . . . . . . . . . . . . . . . . . . 80dB
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment
• High Resolution Imaging Systems
Pinout
ID4
ID3
ID2
ID1
ID0 (LSB)
DGND
DGND
SLEEP
DV
DD
DGND
NC
AV
DD
ID6
ID5
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
AGND
ICOMP1
HI5628 (LQFP)
DD
DV
ID7 (MSB)
REFLO
IOUTA
ICLK
DGND
AGND
IOUTB
QCLK
AGND
QOUTB
DV
DGND
QOUTA
DD
QD7 (MSB)
FSADJ
QD6
QD5
373839404142434445464748
36
35
34
33
32
31
30
29
28
27
26
25
2423222120191817
REFIO
QCOMP1
QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DV
DD
DGND
NC
AV
DD
AGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
CommLink™ is a trademark of Intersil Corporation.
| Copyright © Intersil Corporation 1999
Typical Applications Circuit
50Ω
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
DV
DD
0.1µF
AV
DD
0.1µF
AV
DD
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
AGND
ICOMP1
DV
DD
0.1µF
ID5
ID6
ID7 (MSB)
DGND
DGND
DVDD
DGND
NC (GROUND)
I
CLK/QCLK
AGND
HI5628
DV
DD
0.1µF
QD7 (MSB)
DGND
DGND
DVDD
DGND
NC (GND)
AV
DD
1.91kΩ
R
QD6
373839404142434445464748
2423222120191817
SET
QD5
36
35
34
33
32
31
30
29
28
27
26
25
REFIO
AGND
QCOMP1
0.1µF
QD4
QD3
QD2
QD1
QD0 (LSB)
AV
0.1µF
0.1µF
ANALOG GROUND
PLANE
DIGITAL GROUND
PLANE
DD
AV
DD
0.1µF
DV
DD
PLANE
50Ω
50Ω
QOUTAQOUTB
(POWER PLANE)
AV
DD
NOTE: ICOMP1 AND QCOMP1 PINS (24, 14)
MUST BE TIED TOGETHER EXTERNALLY
FERRITE
BEAD
10µH
0.1µF
+5V TO +3V (SUPPLY)
+5V TO +3V
POWER SUPPLY
10µF
FERRITE
BEAD
10µH
50Ω
0.1µF
50Ω
IOUTBIOUTA
DV
DD
(POWER PLANE)
NOTE: Recommended seperate analog and digital ground planes, connected at a single point near the device. See AN9827.
2
+
10µF
Functional Block Diagram
HI5628
IOUTA IOUTB
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
(MSB) ID7
ICLK
REFLO
REFIO
FSADJ
SLEEP
INT/EXT
REFERENCE
SELECT
LATCH
INT/EXT
VOLTAGE
REFERENCE
UPPER
5-BIT
DECODER
BIAS
GENERATION
CASCODE
CURRENT
SOURCE
34
SWITCH
MATRIX
LATCH
31
34
3 LSBs
+
31 MSB
SEGMENTS
ICOMP1
QCOMP1
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
(MSB) QD7
QCLK
AV
DD
AGND
LATCH
DV
DD
3
DGND
UPPER
5-BIT
DECODER
CASCODE
CURRENT
SOURCE
34
SWITCH
MATRIX
LATCH
31
QOUTA QOUTB
34
3 LSBs
+
31 MSB
SEGMENTS
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