HI5628
Data Sheet July 1999 File Number 4520.3
8-Bit, 165/125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728. This DAC is
a member of the CommLink™ family of communication
devices.
Ordering Information
TEMP.
PART
NUMBER
RANGE
(oC) PACKAGE PKG. NO.
HI5628/16IN† -40 to 85 48 Ld LQFP Q48.7x7A 165MHz
HI5628IN -40 to 85 48 Ld LQFP Q48.7x7A 125MHz
HI5628/6IN -40 to 85 48 Ld LQFP Q48.7x7A 60MHz
HI5628EVAL1† 25 Evaluation Platform 125MHz
† Contact factory for availability.
MAX
CLOCK
SPEED
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Channel Isolation (Typ). . . . . . . . . . . . . . . . . . . . . . . 80dB
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment
• High Resolution Imaging Systems
Pinout
ID4
ID3
ID2
ID1
ID0 (LSB)
DGND
DGND
SLEEP
DV
DD
DGND
NC
AV
DD
ID6
ID5
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
AGND
ICOMP1
HI5628 (LQFP)
DD
DV
ID7 (MSB)
REFLO
IOUTA
ICLK
DGND
AGND
IOUTB
QCLK
AGND
QOUTB
DV
DGND
QOUTA
DD
QD7 (MSB)
FSADJ
QD6
QD5
373839404142434445464748
36
35
34
33
32
31
30
29
28
27
26
25
2423222120191817
REFIO
QCOMP1
QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DV
DD
DGND
NC
AV
DD
AGND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
CommLink™ is a trademark of Intersil Corporation.
| Copyright © Intersil Corporation 1999
Typical Applications Circuit
50Ω
ID4
ID3
ID2
ID1
ID0 (LSB)
SLEEP
DV
DD
0.1µF
AV
DD
0.1µF
AV
DD
0.1µF
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16
AGND
ICOMP1
DV
DD
0.1µF
ID5
ID6
ID7 (MSB)
DGND
DGND
DVDD
DGND
NC (GROUND)
I
CLK/QCLK
AGND
HI5628
DV
DD
0.1µF
QD7 (MSB)
DGND
DGND
DVDD
DGND
NC (GND)
AV
DD
1.91kΩ
R
QD6
373839404142434445464748
2423222120191817
SET
QD5
36
35
34
33
32
31
30
29
28
27
26
25
REFIO
AGND
QCOMP1
0.1µF
QD4
QD3
QD2
QD1
QD0 (LSB)
AV
0.1µF
0.1µF
ANALOG GROUND
PLANE
DIGITAL GROUND
PLANE
DD
AV
DD
0.1µF
DV
DD
PLANE
50Ω
50Ω
QOUTAQOUTB
(POWER PLANE)
AV
DD
NOTE: ICOMP1 AND QCOMP1 PINS (24, 14)
MUST BE TIED TOGETHER EXTERNALLY
FERRITE
BEAD
10µH
0.1µF
+5V TO +3V (SUPPLY)
+5V TO +3V
POWER SUPPLY
10µF
FERRITE
BEAD
10µH
50Ω
0.1µF
50Ω
IOUTBIOUTA
DV
DD
(POWER PLANE)
NOTE: Recommended seperate analog and digital ground planes, connected at a single point near the device. See AN9827.
2
+
10µF
Functional Block Diagram
HI5628
IOUTA IOUTB
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
(MSB) ID7
ICLK
REFLO
REFIO
FSADJ
SLEEP
INT/EXT
REFERENCE
SELECT
LATCH
INT/EXT
VOLTAGE
REFERENCE
UPPER
5-BIT
DECODER
BIAS
GENERATION
CASCODE
CURRENT
SOURCE
34
SWITCH
MATRIX
LATCH
31
34
3 LSBs
+
31 MSB
SEGMENTS
ICOMP1
QCOMP1
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
(MSB) QD7
QCLK
AV
DD
AGND
LATCH
DV
DD
3
DGND
UPPER
5-BIT
DECODER
CASCODE
CURRENT
SOURCE
34
SWITCH
MATRIX
LATCH
31
QOUTA QOUTB
34
3 LSBs
+
31 MSB
SEGMENTS
HI5628
Absolute Maximum Ratings Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . +5.5V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D7-D0, CLK, SLEEP). . . . . . . . DVDD+ 0.3V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD+ 0.3V
Analog Output Current (I
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
OUT
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θJA(oC/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Electrical Specifications AV
= +5V, DVDD= +5V, V
DD
= Internal 1.2V, IOUTFS = 20mA, TA=25oC for All TypicalValues. Data given
REF
is per channel except for ‘Power Supply Characteristics.’
HI5628IN
TA = -40oC TO 85oC
PARAMETER TEST CONDITIONS
UNITSMIN TYP MAX
SYSTEM PERFORMANCE (Per Channel)
Resolution 8 - - Bits
Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -0.5 ±0.25 +0.5 LSB
Differential Linearity Error, DNL (Note 7) -0.5 ±0.25 +0.5 LSB
Offset Error, I
OS
(Note 7)
-0.025
Offset Drift Coefficient (Note 7) - 0.1 -
+0.025
-
% FSR
ppm
o
FSR/
C
Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -10 ±2 +10 % FSR
With Internal Reference (Notes 2, 7) -10 ±1 +10 % FSR
Full Scale Gain Drifta With External Reference (Note 7) - ±50 -
With Internal Reference (Note 7) - ±100 -
ppm
FSR/
ppm
FSR/
o
C
o
C
Gain Matching Between Channels -0.5 0.1 0.5 dB
I/Q Channel Isolation F
= 10MHz - 80 - dB
OUT
Output Voltage Compliance Range (Note 3) -0.3 - 1.25 V
Full Scale Output Current, I
FS
2 - 20 mA
DYNAMIC CHARACTERISTICS (Per Channel)
Clock Rate, f
CLK
Output Settling Time, (t
) 0.8% (±1 LSB, equivalent to 7 Bits) (Note 7) - 5 - ns
SETT
(Note 3, 9) 125 - - MHz
0.4% (±1/2 LSB, equivalent to 8 Bits) (Note 7) - 15 - ns
Singlet Glitch Area (Peak Glitch) RL = 25Ω (Note 7) - 5 - pV•s
Output Rise Time Full Scale Step - 1.5 - ns
Output Fall Time Full Scale Step - 1.5 - ns
Output Capacitance -10- pF
Output Noise IOUTFS = 20mA - 50 -
IOUTFS = 2mA - 30 -
pA/√Hz
pA/√Hz
4
HI5628
Electrical Specifications AV
= +5V, DVDD= +5V, V
DD
= Internal 1.2V, IOUTFS = 20mA, TA=25oC for All TypicalValues. Data given
REF
is per channel except for ‘Power Supply Characteristics.’ (Continued)
HI5628IN
TA = -40oC TO 85oC
PARAMETER TEST CONDITIONS
UNITSMIN TYP MAX
AC CHARACTERISTICS - HI5628/16IN - 165MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 165MSPS, f
CLK
f
= 165MSPS, f
CLK
f
= 125MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 165MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 165MSPS, f
CLK
f
= 165MSPS, f
CLK
f
= 125MSPS, f
CLK
f
= 125MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
= 66.7MHz, 50MHz Span (Notes 4, 7, 9) - 60 - dBc
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7, 9) - 69 - dBc
OUT
= 32.9MHz, 10MHz Span (Notes 4, 7) - 70 - dBc
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7) - 73 - dBc
OUT
= 8.2MHz (Notes 4, 7) - 64 - dBc
OUT
= 2.00MHz (Notes 4, 7) - 67 - dBc
OUT
= 66.7MHz, 82.5MHz Span (Notes 4, 7, 9) - 46 - dBc
OUT
= 20.2MHz, 82.5MHz Span (Notes 4, 7, 9) - 54 - dBc
OUT
= 32.9MHz, 62.5MHz Span (Notes 4, 7) - 51 - dBc
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7) - 61 - dBc
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7) - 48 - dBc
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7) - 56 - dBc
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
OUT
AC CHARACTERISTICS - HI5628IN - 125MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
Total Harmonic Distortion (THD) to
f
= 125MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
= 32.9MHz, 10MHz Span (Notes 4, 7) - 70 - dBc
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7) - 73 - dBc
OUT
= 2.00MHz (Notes 4, 7) - 67 - dBc
OUT
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 125MSPS, f
CLK
f
= 125MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
f
= 100MSPS, f
CLK
= 32.9MHz, 62.5MHz Span (Notes 4, 7) - 51 - dBc
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7) - 61 - dBc
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7) - 48 - dBc
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7) - 56 - dBc
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
OUT
= 2.51MHz, 50MHz Span (Notes 4, 7) - 68 - dBc
OUT
AC CHARACTERISTICS - HI5628/6IN - 60MHz (Per Channel)
Spurious Free Dynamic Range,
SFDR Within a Window
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
= 60MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 60MSPS, f
CLK
f
= 60MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 50MSPS, f
CLK
f
= 25MSPS, f
CLK
= 10.1MHz, 10MHz Span (Notes 4, 7) - 70 - dBc
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7) - 73 - dBc
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7) - 74 - dBc
OUT
= 2.00MHz (Notes 4, 7) - 67 - dBc
OUT
= 1.00MHz (Notes 4, 7) - 68 - dBc
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7) - 54 - dBc
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7) - 60 - dBc
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7) - 53 - dBc
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7) - 67 - dBc
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7) - 68 - dBc
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7) - 68 - dBc
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7) - 71 - dBc
OUT
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Voltage at Pin 22 with Internal Reference 1.04 1.16 1.28 V
Internal Reference Voltage Drift - ±60 - ppm/oC
Internal Reference Output Current
- 0.1 - µA
Sink/Source Capability
Reference Input Impedance -1-MΩ
5
HI5628
Electrical Specifications AV
= +5V, DVDD= +5V, V
DD
= Internal 1.2V, IOUTFS = 20mA, TA=25oC for All TypicalValues. Data given
REF
is per channel except for ‘Power Supply Characteristics.’ (Continued)
HI5628IN
TA = -40oC TO 85oC
PARAMETER TEST CONDITIONS
UNITSMIN TYP MAX
Reference Input Multiplying Bandwidth (Note 7) - 1.4 - MHz
DIGITAL INPUTS D7-D0, CLK (Per Channel)
Input Logic High Voltage with
5V Supply, V
IH
Input Logic High Voltage with
3V Supply, V
IH
Input Logic Low Voltage with
5V Supply, V
IL
Input Logic Low Voltage with
3V Supply, V
Input Logic Current, I
Input Logic Current, I
IL
IH
IL
Digital Input Capacitance, C
IN
(Note 3) 3.5 5 - V
(Note 3) 2.1 3 - V
(Note 3) - 0 1.3 V
(Note 3) - 0 0.9 V
-10 - +10 µA
-10 - +10 µA
-5-pF
TIMING CHARACTERISTICS (Per Channel)
Data Setup Time, t
Data Hold Time, t
SU
HLD
Propagation Delay Time, t
CLK Pulse Width, t
PW1
, t
PD
PW2
See Figure 3 (Note 3) 3 - - ns
See Figure 3 (Note 3) 3 - - ns
See Figure 3 - 1 - ns
See Figure 3 (Note 3) 4 - - ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
DVDD Power Supply (Note 8, 9) 2.7 5.0 5.5 V
Analog Supply Current (I
) 5V or 3V, IOUTFS = 20mA - 46 60 mA
AVDD
5V or 3V, IOUTFS = 2mA - 8 - mA
Digital Supply Current (I
) 5V, IOUTFS = Don’t Care (Note 5) - 6 10 mA
DVDD
3V, IOUTFS = Don’t Care (Note 5) - 3 - mA
Supply Current (I
) Sleep Mode 5V or 3V, IOUTFS = Don’t Care) - 3.2 6 mA
AVDD
Power Dissipation (Both Channels) 5V, IOUTFS = 20mA (Note 6) - 330 - mW
5V, IOUTFS = 2mA (Notes 6) - 140 - mW
3V, IOUTFS = 20mA (Note 6) - 170 - mW
3V, IOUTFS = 2mA (Note 6) - 54 - mW
5V, IOUTFS = 20mA (Note 10) - 300 - mW
3.3V, IOUTFS = 20mA (Note 10) - 150 - mW
3V, IOUTFS = 20mA (Note 10) - 135 - mW
Power Supply Rejection Single Supply (Note 7) -0.2 - +0.2 %
FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
(typically 625µA). Ideally the
SET
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
7. See ‘Definition of Specifications’.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDDand
AVDD do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3Vorgreater.Thepartisfunctionalwiththeclockabove 125MSPS
and the power supply below 3.3V, but performance is degraded. (Valid for 165MHz version only).
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
6
Timing Diagrams
HI5628
CLK
D7-D0
I
OUT
t
SETT
t
PD
FIGURE 1. OUTPUT SETTLING TIME DIAGRAM
CLK
50%
1
/2 LSB ERROR BAND
t
PW1
t
PW2
V
GLITCH AREA =
WIDTH (W)
1
/2 (H x W)
HEIGHT (H)
t(ps)
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
50%
t
SU
t
HLD
D7-D0
I
OUT
t
t
PD
SETT
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
t
SU
t
HLD
t
t
PD
SETT
t
SU
t
HLD
t
t
PD
SETT
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement was done by switching from code 0 to 64, or
quarter scale. Termination impedance was 25
Ω due to the
7
HI5628
parallel resistance of the output 50
50
Ω input. This also aids the ability to resolve the specified
Ω and the oscilloscope’s
error band without overdriving the oscilloscope.
Singlet Glitch Area, is the switching transient appearing on
the output during a code transition. It is measured as the
area under the overshoot portion of the curve and is
expressed as a Volt-Time specification.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
SET
).
Full Scale Gain Drift, is measured by setting the data inputs
to all ones and measuring the output voltage through a
known resistance as the temperature is varied from T
T
. It is defined as the maximum deviation from the value
MAX
MIN
to
measured at room temperature to the value measured at
either T
MIN
or T
. The units are ppm of FSR (Full Scale
MAX
Range) per degree C.
T otalHarmonicDistortion, THD,istheratio of the DACoutput
fundamental to the RMS sum of the first five harmonics.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental to the largest harmonically
or non-harmonically related spur within the specified
window.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance load should
be chosen such that the voltage developed does not violate
the compliance range.
Offset Error, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance. Offset error is defined as the maximum deviation
of the output current from a value of 0mA.
Offset Drift, is measured by setting the data inputs to all
zeros and measuring the output voltage through a known
resistance as the temperature is varied from T
MIN
to T
MAX
It is defined as the maximum deviation from the value
measured at room temperature to the value measured at
either T
MIN
or T
. The units are ppm of FSR (Full Scale
MAX
Range) per degree C.
PowerSupply Rejection, is measured using a single power
supply. Its nominal +5V is varied
±10% and the change in the
DAC full scale output is noted.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveformis 0.707
of its original value.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either T
MIN
or T
MAX
.
The units are ppm per degree C.
Detailed Description
The HI5628 is a dual, 8-bit, current out, CMOS, digital to
analog converter. Its maximum update rate is 165MSPS and
can be powered by either single or dual power supplies in
the recommended range of +3V to +5V. It consumes less
than 330mW of power when using a +5V supply with the
data switching at 100MSPS. The architecture is based on a
segmented current source arrangement that reduces glitch
by reducing the amount of current switching at any one time.
The five MSBs are represented by 31 major current sources
of equivalent current. The three LSBs are comprised of
binary weighted current sources. Consider an input pattern
to the converter which ramps through all the codes from 0 to
255. The three LSB current sources would begin to count up.
When they reached the all high state (decimal value of 7)
and needed to count to the next code, they would all turn off
and the first major current source would turn on. Tocontinue
counting upward, the 3 LSBs would count up another 7
codes, and then the next major current source would turn on
and the three LSBs would all turn off. The process of the
single, equivalent, major current source turning on and the
three LSBs turning off each time the converter reaches
another 7 codes greatly reduces the glitch at any one
switching point. In previous architectures that contained all
binary weighted current sources or a binary weighted
resistor ladder, the converter might have a substantially
larger amount of current turning on and off at certain, worstcase transition points such as midscale and quarter scale
transitions. By greatly reducing the amount of current
switching at certain ‘major’ transitions, the overall glitch of
the converter is dramatically reduced, improving settling
times and transient problems.
Digital Inputs and Termination
.
The HI5628 digital inputs are guaranteed to CMOS levels .
Howev er, TTL compatibility can be achiev ed by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being appro ximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are 50Ω lines, then 50Ω termination resistors should be
placed as close to the converter inputs as possible,connected
to the digital ground plane (if separate grounds are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then all
of the digital functions of the device and their corresponding
components should be over the digital ground plane and
terminated to the digital ground plane. The same is true for
the analog components and the analog ground plane. The
converter will function properly with a single ground plane, as
the Evaluation Board is configured in this matter .
8
HI5628
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
and DVDD. Also, should the layout be designed
DD
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
DV
and to the analog ground for AVDD. Additional filtering
DD
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ±60 ppm/
temperature range of the converter . It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO , pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of R
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, V
approximately 1.16V (pin 22). If an external reference is used,
V
I
I
will equal the external reference. The calculation f or
FSADJ
(Full Scale) is:
OUT
(Full Scale) = (V
OUT
FSADJ/RSET
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
resistor, then the input coding to output current will resemble
the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D7-D0) IOUTA (mA) IOUTB (mA)
111 11111 20 0
100 00000 10 10
000 00000 0 20
o
C drift coefficient over the full
. I
SET
FSADJ
should be within
OUT
will equal
)x 32.
SET
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. R
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
V
= I
OUT
X R
OUT
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mV
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
PIN 17 (20)
PIN 16 (21)
V
OUT
= 2 x I
IOUTB (QOUTB)
IOUTA (QOUTA)
OUT
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
should be chosen so that the desired
LOAD
.
LOAD
P-P
V
= (2 x I
OUT
50Ω
x R
50Ω
100Ω
50Ω
FIGURE 4.
where REQ is ~12.5Ω.
EQ ,
amplitude
x REQ)V
OUT
9
HI5628
Pin Descriptions
PIN NO. PIN NAME PIN DESCRIPTION
39-32 QD7 (MSB) Through
QD0 (LSB)
1-5, 48-46 ID7 (MSB) Through
ID0 (LSB)
8 SLEEP Control Pin for Power-DownMode. Sleep Mode is active high; connect to ground for Normal Mode. Sleep
15 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
23 REFIO Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
22 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
14, 24 ICOMP1, QCOMP1 Reduces noise. Connect each to AVDDwith 0.1µF capacitor. The ICOMP1 and QCOMP1 pins MUST be
13, 18, 19, 25 AGND Analog Ground Connections.
17 IOUTB The complementary current output of the I channel. Bits set to all 0s gives full scale current.
16 IOUTA Current output of the I channel. Bits set to all 1s gives full scale current.
20 QOUTB The complementary current output of the Q channel. Bits set to all 0s gives full scale current.
21 QOUTA Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27 NC No Connect. Recommended: Connect to ground.
12, 26 AV
6, 7, 10, 28, 30,
31, 41, 44
9, 29, 40, 45 DV
43 ICLK Clock input for I channel. Positive edge of clock latches data.
42 QCLK Clock input for Q channel. Positive edge of clock latches data.
DD
DGND Digital Ground.
DD
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
Digital Data Bit 7, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
pin has internal 20µA active pulldown current.
enabled. Use 0.1µF cap to ground when internal reference is enabled.
Current Per Channel = 32 x I
tied together externally.
Analog Supply (+2.7V to +5.5V).
Supply voltage for digital circuitry (+2.7V to +5.5V).
FSADJ
.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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10
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