Intersil Corporation HI3338 Datasheet

HI3338

August 1997

Features

• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . .100mW

• R2R Output, Segmented for Low “Glitch”

• CMOS/TTL Compatible Inputs

• Fast Settling (Typ) . . . . . . . . . . . . . . . . .20ns to

1

• Feedthrough Latch for Clocked or Unclocked Use

• Accuracy (Typ). . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Data Complement Control

• High Update Rate (Typ). . . . . . . . . . . . . . . . . . . . 50MHz

• Unipolar or Bipolar Operation

• Linearity (INL):

- HI3338KIP . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.75 LSB

- HI3338KIB . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.75 LSB

Applications

• TV/Video Display

• High Speed Oscilloscope Display

• Digital Waveform Generator

• Direct Digital Frequency Synthesis

• Wireless Communication

/2 LSB

8-Bit, CMOS R2R D/A Converter

Description

The HI3338 family are CMOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground.

The data complement control allows the inversion of input
data while the latch enable control provides either
feedthrough or latched operation. Both ends of the R2R lad­der network are available externally and may be modulated
for gain or offset adjustments. In addition, “glitch” energy has
been kept very low by segmenting and thermometer encod­ing of the upper 3 bits.

The HI3338 is manufactured to give low dynamic power
dissipation, low output capacitance, and inherent latch-up
resistance.

Ordering Information

TEMP.

PART NUMBER

HI3338KIP -40 to 85 16 Ld PDIP E16.3
HI3338KIB -40 to 85 16 Ld SOIC M16.3

RANGE (oC) PACKAGE PKG. NO.

Pinout

HI3338

(PDIP, SOIC)

TOP VIEW

V

1

D7

2

D6

3

D5

4

D4

5

D3

6

D2

7

D1

8

V

SS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

10-1464

16
15
14
13
12
11
10

9

DD

LE
COMP
V

REF

V

OUT

V

REF

V

EE

D0

+

-

File Number 4134.1

Functional Diagram

HI3338

V

DD

LE

COMP

D7

D6

D5

D4

D3

D2

D1

D0

V

SS

16

8R

15

3-BIT

14

1

2

3

4

5

6

7

9

8

LEVEL

SHIFTERS

TO 7-LINE

THERMOMETER

ENCODER

FEEDTHROUGH

LATCHES

8R

8R

8R

4R

4R

2R

2R

2R

2R

2R

2R

R ≅160Ω

R

R

R

R

R

R

R

2R

13

V

+

REF

12

V

OUT

11

V

-

REF

10

V

EE

Die Characteristics

DIE DIMENSIONS:

2,740µm x 3,310µm x 530 ±50µm

METALLIZATION:

Type: Al with 0.8% Si
Thickness: 11k

GLASSIVATION:

Type: 3% PSG
Thickness: 13k

Å ±1kÅ

Å ±2.6kÅ

10-1465

HI3338

Absolute Maximum Ratings Thermal Information

DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V

(VDD - VSS or VDD - VEE, Whichever Is Greater)

Input Voltage Range

Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V

Analog Pins (V

REF

+, V

REF

-, V

). . . . VDD - 8V to VDD + 0.5V

OUT

DC Input Current

Digital Inputs (LE, COMP, D0 - D7). . . . . . . . . . . . . . . . . . ±20mA

Recommended Supply Voltage Range. . . . . . . . . . . . . .4.5V to 7.5V

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range, T

. . . . .-65oC to 150oC

STG

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

= 25oC, VDD = 5V, V

A

+ = 4.608V, VSS = VEE = V

REF

- = GND, LE clocked at 20MHz, RL≥ 1MΩ,

REF

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits
Integral Linearity Error See Figure 4 - - ±0.75 LSB
Differential Linearity Error See Figure 4 - - ±0.5 LSB
Gain Error Input Code = FF
Offset Error Input Code = 00

, See Figure 3 - - ±0.5 LSB

HEX

, See Figure 3 - - ±0.25 LSB

HEX

DIGITAL INPUT TIMING

Update Rate To Maintain1/2 LSB Settling DC 50 - MHz
Update Rate V
Set Up Time t
Set Up Time t
Hold Time t
Latch Pulse Width t
Latch Pulse Width t

SU1

SU2

H

W

W

OUTPUT PARAMETERS RL Adjusted for 1V
Output Delay t
Output Delay t
Rise Time t
Settling Time t

D1

D2

r

S

Output Impedance V

- = VEE = -2.5V, V

REF

+ = +2.5V DC 20 - MHz

REF

For Low Glitch - -2 - ns
For Data Store - 8 - ns
For Data Store - 5 - ns
For Data Store - 5 - ns
V

- = VEE = -2.5V, V

REF

P-P

+ = +2.5V - 25 - ns

REF

Output
From LE Edge - 25 - ns
From Data Changing - 22 - ns
10% to 90% of Output - 4 - ns
10% to Settling to1/2 LSB - 20 - ns

+ = 6V, VDD = 6V 120 160 200 Ω

REF

Glitch Area - 150 - pV-s
Glitch Area V

- = VEE = -2.5V, V

REF

+ = +2.5V - 250 - pV-s

REF

REFERENCE VOLTAGE

V

+ Range (+) Full Scale (Note 1) V

REF

V

- Range (-) Full Scale (Note 1) V

REF

10-1466

- + 3 - V

REF

EE

-V

DD

+ - 3 V

REF

V