Intersil Corporation HI3318JIP, HI3318JIB, HI3318 Datasheet

HI3318

August 1997

Features

• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . 150mW

• Parallel Conversion Technique

• Sampling Rate at 5V Supply . . . . . . . . . . . . . . . . 15MHz

• 8-Bit Latched Three-State Output with Overﬂow Bit

• Accuracy (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . ±1 LSB

• Single Supply Voltage . . . . . . . . . . . . . . . . . . 4V to 7.5V

• Linearity (INL):

- HI3318JIP . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5 LSB

- HI3318JIB . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.5 LSB

• Sampling Rate:

- HI3318JIP . . . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)

- HI3318JIB . . . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)

• Video Digitizing

• High-Speed A/D Conversion

• Medical Imaging

• Radar Signal Processing

• Digital Communications Systems

8-Bit, 15 MSPS, Flash A/D Converter

Description

The HI3318 is a CMOS parallel (FLASH) analog-to-digital converter designed for applications demanding both low power consumption and high speed digitization.

The HI3318 operates over a wide full scale input voltage range of 4V up to 7.5V with maximum power consumption depending upon the clock frequency selected. When operated from a 5V supply at a clock frequency of 15MHz, the typical power consumption of the HI3318 is 150mW.

256 paralleled auto balanced voltage comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the HI3318. 255 comparators are required to quantize all input voltage levels in this 8-bit converter, and the additional comparator is required for the overﬂow bit.

Ordering Information

TEMP.

PART NUMBER

HI3318JIP -40 to 85 24 Ld PDIP E24.6

HI3318JIB -40 to 85 24 Ld SOIC M24.3

RANGE (oC) PACKAGE

PKG.

NO.

Pinout

(LSB) B1

(MSB) B8

OVERFLOW

(DIG. GND) V (DIG. SUP.) V

B2 B3 B4 B5 B6 B7

1/4R

SS DD

1 2 3 4 5 6 7 8

9 10 11 12

HI3318

(PDIP, SOIC)

TOP VIEW

VAA+ (ANA. SUP.) 3/4R

23 22 21 20 19 18 17 16 15 14 13

REF

p PHASE CLK

- (ANA. GND)

REF

CE1 CE2

4-1452

File Number 4135.1

Functional Block Diagram

HI3318

VAA+

REF

/4 REF

/2 REF

/4REF

REF

CLOCK

PHASE

/2 R

R = 2Ω

= 7Ω

= 30Ω

= 4Ω

≅2K

/2 R

ANALOG SUPPLY

≅50K

ANALOG GND

φ2 φ1 φ1 φ1 φ1 φ2 φ1

COUNT

256

COUNT

193

COUNT

129

COUNT

ENCODER

LOGIC

ARRAY

CAB

# 256

CAB

# 193

CAB

# 129

CAB

# 65

CAB

(NOTE 1)

COMPARATOR #1

LATCH

256

LATCH

256

LATCH

φ1 (AUTO BALANCE)

φ2 (SAMPLE UNKNOWN)

DIGITAL SUPPLY

OUTPUT

DQ CLK

THREE-

STATE

DRIVERS

OVER-

FLOW

BIT 8

(MSB)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

(LSB)

CE1

CE2

NOTE:

1. Cascaded Auto Balance (CAB).

4-1453

DIGITAL

GND

HI3318

Absolute Maximum Ratings T

DC Supply Voltage Range (VDD or VAA+) . . . . . . . . . . -0.5V to +8V

(Referenced to VSS or VAA- Terminal, Whichever is More Negative)

Input Voltage Range

CE2 and CE1 . . . . . . . . . . . . . . . . . . . . VAA- -0.5V to VDD + 0.5V

Clock, Phase, V Clock, Phase, V VIN,3/4 REF, V

-,1/2 Ref. . . . . . . VAA- -0.5V to VAA+ + 0.5V

REF

-,1/4 Ref. . . . . . . . VSS- -0.5V to VDD + 0.5V

REF

+. . . . . . . . . . . . . . .VAA- -0.5V to VAA- + 7.5V

REF

=25oC Thermal Information

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Output Voltage Range, . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V

Bits 1-8, Overﬂow (Outputs Off)

DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Clock, Phase, CE1, CE2, VIN, Bits 1-8, Overﬂow

Recommended VAA+ Operating Range. . . . . . . . . . . . . . . VDD±1V

Recommended VAA- Operating Range . . . . . . . . . . . . . . . VSS±1V

Operating Conditions

Operating Voltage Range (VDD or VAA+). . . 4V (Min) to 7.5V (Max)

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations At 25

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 8 - - Bits Integral Linearity Error - - ± 1.5 LSB Differential Linearity Error - - +1, -0.8 LSB Offset Error, Unadjusted V Gain Error, Unadjusted VIN = V

DYNAMIC CHARACTERISTICS

Maximum Input Bandwidth (Note 1) HI3318 2.5 5.0 - MHz Maximum Conversion Speed CLK = Square Wave 15 17 - MSPS Signal to Noise Ratio, SNR fS = 15MHz, fIN = 100kHz - 47 - dB

RMS Signal

----------------------------------

RMS Noise

Signal to Noise Ratio, SINAD fS = 15MHz, fIN = 100kHz - 45 - dB

RMS Signal

--------------------------------------------------------------- -

RMSNoise + Distortion

C, VAA+ = VDD = 5V, V

+ = 6.4V, V

REF

- = VAA- = VSS, CLK = 15MHz,

REF

All Reference Points Adjusted, Unless Otherwise Speciﬁed

= V

- +1/2 LSB -0.5 4.5 6.4 LSB

REF

+ -1/2 LSB -1.5 0 1.5 LSB

REF

fS = 15MHz, fIN = 4MHz - 43 - dB

fS = 15MHz, fIN = 4MHz - 35 - dB

Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - -46 - dBc

fS = 15MHz, fIN = 4MHz - -36 - dBc

Effective Number of Bits, ENOB fS = 15MHz, fIN = 100kHz - 7.2 - Bits

fS = 15MHz, fIN = 4MHz - 5.5 - Bits Differential Gain Error Unadjusted - 2 - % Differential Phase Error Unadjusted - 1 - %

ANALOG INPUTS

Full Scale Range, VIN and (V Input Capacitance, V

Input Current, VIN, (See Text) VIN = 5.0V, V

REF

+) - (V

-) Notes 2, 4 4 - 7 V

REF

-30- pF

+ = 5.0V - - 3.5 mA

REF

REFERENCE INPUTS

Ladder Impedance 270 500 800 Ω

4-1454

HI3318

Electrical Speciﬁcations At 25

C, VAA+ = VDD = 5V, V

+ = 6.4V, V

REF

- = VAA- = VSS, CLK = 15MHz,

REF

All Reference Points Adjusted, Unless Otherwise Speciﬁed (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DIGITAL INPUTS

Low Level Input Voltage, V

CE1, CE2 Note 4 - - 0.2V Phase, CLK Note 4 - - 0.2V

High Level Input Voltage, V

CE1, CE2 Note 4 0.7V Phase, CLK Note 4 0.7V

DD AA

--V

V V

Input Leakage Current, II (Except CLK Input) Note 3 - ±0.2 ±5 µA Input Capacitance, C

-3-pF

DIGITAL OUTPUTS

Output Low (Sink) Current VO = 0.4V 4 10 - mA Output High (Source) Current VO = 4.5V -4 -6 - mA Three-State Output Off-State Leakage Current, I Output Capacitance, C

- ±0.2 ±5 µA

-4-pF

TIMING CHARACTERISTICS

Auto Balance Time, φ133-

∞

Sample Time, φ2 Note 4 25 - 500 ns Aperture Delay -15- ns Aperture Jitter - 100 - ps Data Valid Time, t Data Hold Time, t

Output Enable Time, t Output Disable Time, t

DIS

Note 4 - 50 65 ns

Note 4 25 40 - ns

-18- ns

POWER SUPPLY CHARACTERISTICS

Device Current (IDD + IA) (Excludes I

) Continuous Conversion (Note 4) - 30 60 mA

REF

Auto Balance (φ1) - 30 60 mA

NOTES:

1. A full scale sine wa ve input of greater than f

/2 or the speciﬁed input bandwidth (whichever is less) ma y cause an erroneous code. The

CLK

-3dB bandwidth for frequency response purposes is greater than 30MHz.

2. VIN (Full Scale) or V

3. The clock input is a CMOS inverter with a 50kΩ feedback resistor and may be AC coupled with 1V

+ should not exceed VAA+ + 1.5V for accuracy.

REF

minimum source.

P-P

4. Parameter not tested, but guaranteed by design or characterization.

Timing Waveforms

COMPARATOR DATA IS LATCHED

CLOCK (PIN 18)

IF PHASE (PIN 19)

IS LOW

CLOCK IF

PHASE IS HIGH

DECODED DATA IS SHIFTED TO OUTPUT REGISTERS

φ2

SAMPLE

DAT A

N - 2

AUTO

BALANCE

φ2 φ1φ1 φ2

SAMPLE

N + 1

DAT A

N - 1

FIGURE 1. INPUT TO OUTPUT TIMING DIAGRAM

4-1455

AUTO

BALANCE

SAMPLE

N + 2

DAT A

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