Intersil Corporation HI3306 Datasheet

HI3306

December 1997

Features

• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .55mW

• Parallel Conversion Technique

• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V

• Sampling Rate with Single 5V Supply . . . . . . . . 15MHz

• 6-Bit Latched Three-State Output with Overflow Bit

• Linearity (INL, DNL):

- HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

- HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

- HI3306JIB/15. . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

- HI3306JIB/10. . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Sampling Rate:

- HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)

- HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . 10MHz (100ns)

- HI3306JIB/15. . . . . . . . . . . . . . . . . . . . . 15MHz (67ns)

- HI3306JIB/10. . . . . . . . . . . . . . . . . . . . 10MHz (100ns)

Applications

• Video Digitizing

• Digital Communication Systems

• High Speed Data Acquisition

• Radar Signal Processing

6-Bit, 15 MSPS, Flash A/D Converter

Description

The HI3306 family are CMOS parallel (FLASH) analog-to­digital converters designed for applications demanding
both low power consumption and high speed digitization.
Digitizing at 15MHz, for example, requires only about
55mW.

The HI3306 family operates ov er a wide , full scale signal input
voltage range of 1V up to the supply voltage. Power consump­tion is as low as 15mW, depending upon the clock frequency
selected. The HI3306 offers improved linearity at a lower ref­erence voltage and high operating speed with a 5V supply.

The overflow bit makes possible the connection of two or
more HI3306s in series to increase the resolution of the
conversion system.

Sixty-four paralleled auto balanced comparators measure
the input voltage with respect to a known reference to pro­duce the parallel bit outputs in the HI3306. Sixty-three com­parators are required to quantize all input voltage levels in
this 6-bit converter, and the additional comparator is
required for the overflow bit.

Ordering Information

TEMP.

PART NUMBER

HI3306JIP/15 -40 to 85 18 Ld PDIP E18.3
HI3306JIP/10 -40 to 85 18 Ld PDIP E18.3
HI3306JIB/15 -40 to 85 20 Ld SOIC M20.3

RANGE (oC) PACKAGE PKG. NO.

HI3306JIB/10 -40 to 85 20 Ld SOIC M20.3

Pinouts

HI3306 (PDIP)

TOP VIEW

(MSB) B6

OVERFLO W

PHASE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1
2

V

3

SS

V

4

Z

CE2

5

CE2

6

CLK

7
8
9

+

V

REF

18
17
16
15
14
13
12
11
10

B5
B4

REF
CENTER

B3
B2
B1 (LSB)
V

DD

V

IN

V

-

REF

OVERFLO W

1

(MSB) B6

V

SS

NC

V
CE2
CE1

CLK

PHASE

V

REF

HI3306 (SOIC)

TOP VIEW

1
2
3
4
5

Z

6
7
8
9

+

10

B5

20

B4

19

REF

18

CENTER
B3

17

B2

16

B1 (LSB)

15

V

14

DD

NC

13
12

V

IN

V

-

11

REF

File Number 4136.2

Functional Block Diagram

V

IN

R/2

V

+

REF

R

φ1

φ2

φ1 φ1

HI3306HI3306

COMP

64

φ2

DQ
CL

THREE-STATE

OVERFLO W

≅

REF

CENTER

V

REF

CLOCK

PHASE

ZENER

DIODE

R

R

120Ω

R

R

R

-

R/2

≅

50kΩ

6.2V NOMINAL

COMP

63

COMP

32

COMP

2

COMP

1

COMP ARATOR

LATCHES

AND

ENCODER

LOGIC

DQ
CL

DQ
CL

DQ
CL

DQ
CL

DQ
CL

DQ
CL

B6 (MSB)

B5

B4

B3

B2

B1 (LSB)

CE1

φ2 (SAMPLE UNKNOWN)

φ1 (AUTO BALANCE)

V

V

SS

V

DD

SS

CE2

Typical Application Circuit

+12V

+12V

5kΩ

+

-

CA741CE

560Ω

CLOCK

6.2V

0.1µF

+5V

OF

B6

1

2

3

4

5

6

7

8

9

OF

V

SS

V

Z

CE2

CE1

CLK

PH

V

REF+

HI3306

V

B5

B4

RC

B3

B2

B1

V

DD

V

REF-

18

17

0.1µF

16

15

14

13

12

11

IN

10

B6
B5
B4

B3
B2
B1

(LSB)

0.2µF

SIGNAL
INPUT

DAT A
OUTPUT

+5V

10µF

2

HI3306

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range, V

Voltage Referenced to VSS Terminal . . . . . . . . . . .-0.5V to +8.5V

Input Voltage Range

All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V

DC Input Current

CLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

DD

Operating Conditions

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 6 - - Bits
Integral Linearity Error, INL - ±0.25 ±0.5 LSB
Differential Linearity Error, DNL - ±0.25 ±0.5 LSB
Offset Error (Unadjusted) (Note 2) - ±0.5 ±1 LSB
Gain Error (Unadjusted) (Note 3) - ±0.5 ±1 LSB
Gain Temperature Coefficient - +0.1 - mV/oC
Offset Temperature Coefficient - -0.1 - mV/oC
DYNAMIC CHARACTERISTICS Input Signal Level 0.5dB Below Full Scale
Maximum Conversion Speed HI3306XXX/10 10 13 - MSPS

Maximum Conversion Speed HI3306XXX/10 (Note 5)

Allowable Input Bandwidth (Note 5) DC - f

-3dB Input Bandwidth - 30 - MHz
Signal to Noise Ratio, SNR fS = 15MHz, fIN = 100kHz - 34.6 - dB

RMS Signal

----------------------------------

=

RMS Noise

Signal to Noise Ratio, SINAD fS = 15MHz, fIN = 100kHz - 34.2 - dB

RMS Signal

----------------------------------------------------------------- -

=

RMS Noise + Distortion

Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - -46.0 - dBc

Effective Number of Bits, ENOB fS = 15MHz, fIN = 100kHz - 5.5 - Bits

ANALOG INPUTS

Positive Full Scale Input Range (Notes 4, 5) 1 4, 8 VDD + 0.5 V
Negative Full Scale Input Range (Notes 4, 5) -0.5 0 VDD - 1 V
Input Capacitance -15- pF
Input Current VIN = 4.92V, VDD = 5V - - ±500 µA

INTERNAL VOLTAGE REFERENCE

Zener Voltage IZ = 10mA 5.4 6.2 7.4 V
Zener Dynamic Impedance IZ = 10mA, 20mA - 12 25 Ω

= 25oC, VDD = 5V, V

A

HI3306XXX/15, 10MHz for HI3306XXX/10

HI3306XXX/15 15 20 - MSPS

HI3306XXX/15 18 - - MSPS

φ1, φ2 ≥ Minimum

fS = 15MHz, fIN = 5MHz - 33.4 - dB

fS = 15MHz, fIN = 5MHz - 29.0 - dB

fS = 15MHz, fIN = 5MHz - -30.0 - dBc

fS = 15MHz, fIN = 5MHz - 4.5 - Bits

+ = 4.8V, VSS = V

REF

- = GND, Clock = 15MHz Square Wave for

REF

12 - - MSPS

CLOCK/2

MHz

3

HI3306

Electrical Specifications T

= 25oC, VDD = 5V, V

A

+ = 4.8V, VSS = V

REF

- = GND, Clock = 15MHz Square Wave for

REF

HI3306XXX/15, 10MHz for HI3306XXX/10 (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Zener Temperature Coefficient - -0.5 - mV/oC

REFERENCE INPUTS

Resistor Ladder Impedance 650 1100 1550 Ω

DIGITAL INPUTS

Maximum VIN, Logic 0 All Digital Inputs (Note 5) - - 0.3 x V
Maximum VIN, Logic 1 All Digital Inputs (Note 5) 0.7 x V

DD

--V

DD

V

Digital Input Current Except CLK, VIN = 0V, 5V - ±1 ±5 µA
Digital Input Current CLK Only - ±100 ±200 µA

DIGITAL OUTPUTS

Digital Output Three-State Leakage V
Digital Output Source Current V
Digital Output Sink Current V

= 0V, 5V - ±1 ±5 µA

OUT

= 4.6V -1.6 - - mA

OUT

= 0.4V 3.2 - - mA

OUT

TIMING CHARACTERISTICS

Auto Balance Time (φ1) HI3306XXX/10 50 -

HI3306XXX/15 33 -

∞
∞

ns

Sample Time (φ2) HI3306XXX/10 (Note 5) 33 - 5000 ns

HI3306XXX/15 22 - 5000 ns
Aperture Delay -8-ns
Aperture Jitter - 100 - ps

P-P

Output Data Valid Delay, tDHI3306XXX/10 - 35 50 ns

HI3306XXX/15 - 30 40 ns
Output Data Hold Time, t
Output Enable Time, t
Output Disable Time, t

EN

DIS

H

(Note 5) 15 25 - ns

-20- ns

-15- ns

POWER SUPPLY CHARACTERISTICS

IDD Current, Refer to Figure 4 HI3306XXX/10 Continuous Conversion (Note 5) - 11 20 mA

HI3306XXX/15 - 14 25 mA
IDD Current Continuous φ1 - 7.5 15 mA

NOTES:

2. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (V

3. GAIN ERROR is the difference the input voltage that causes the 3F16 to overflow output code transition and (V

4. The total input voltage range, set by V

REF

+ and V

-, may be in the range of 1 to (VDD + 1) V.

REF

REF

REF

+ - V

+ - V

-) x 127/128.

REF

REF

-)/128.

5. Parameter not tested, but guaranteed by design or characterization.

Timing Waveforms

COMPARATOR DATA IS LATCHED DECODED DATA IS SHIFTED TO OUTPUT REGISTERS

CLOCK IF

PHASE IS HIGH

CLOCK IF

PHASE IS LOW

φ2 φ2 φ2φ1φ1

DAT A

N - 2

AUTO

BALANCE

DAT A

N - 1

SAMPLE

N + 1

t

t

H

D

FIGURE 1. INPUT-TO-OUTPUT

4

AUTO

BALANCE

DAT A

N

SAMPLE

N + 2

Timing Waveforms

CE1

HI3306

CLOCK

OUTPUT

BITS 1-6

SAMPLE ENDS

φ2

OLD DATA

CE2

OF

t

DIS

HIGH

IMPEDANCE

DAT A

t

EN

t

DIS

IMPEDANCE

IMPEDANCE

HIGH

HIGH

t

DIS

FIGURE 2. OUTPUT ENABLE

SAMPLE ENDS

φ1

φ2

t

D

NEW DATA

CLOCK

OUTPUT

OLD

DAT A

FIGURE 3A. FIGURE 3B.

SAMPLE ENDS

CLOCK

φ2

φ2φ1φ2φ1

t

D

DAT ADAT ADAT A

DAT A

OLD

DATA +1

φ2 φ1φ1φ2φ1

t

D

NEW

DAT A

OUTPUT

OLD DATA

Typical Performance Curves

50

TA = 25oC, V
VIN = 0 TO V

40

30

VDD = 8V

= 7V

V

(mA)

DD

I

DD

= 6V

V

DD

20

10

= 5V

V

DD

0.1 1 10

FIGURE 4. TYPICAL IDD AS A FUNCTION OF V

+ = V

REF

DD

+ SINE WAVE AT f

REF

DISSIPATION LIMITED

CLOCK FREQUENCY (MHz)

CLK/2

FIGURE 3C.

FIGURE 3. PULSE MODE

C)

o

AMBIENT TEMPERATURE (

VDD = 3V

DD

FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE AS

INVALID

DAT A

125

f

= 3MHz

CLK

f

= 10MHz

CLK

= 15MHz

f

100

75

50

25

CLK

= 20MHz

f

CLK

MAXIMUM AMBIENT

TEMPERATURE - PLASTIC

V

+ = V

REF

VIN = 0 TO V
ZENER NOT CONNECTED

DD

+ SINE WAVE AT f

REF

A FUNCTION OF SUPPLY VOLTAGE

NEW

DAT A

V

DD

(V)

CLK/2

f

CLK

= 1MHz

876543

5