®
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HA-2510/883
Data Sheet FN3697.4January 3, 2006
High Slew Rate Operational Amplifier
The HA-2510/883 is a high performance operational
amplifier which sets the standards for maximum slew rate
and wide bandwidth operation in moderately powered,
internally compensated, monolithic devices. In addition to
excellent dynamic characteristics, this dielectrically isolated
amplifier also offers low offset current and high input
impedance.
The ±50V/µs minimum slew rate and fast settling time of
the HA-2510/883 are ideally suited for high speed D/A,
A/D, and pulse amplification designs. The HA-2510/883’s
superior bandwidth and 750kHz minimum full power
bandwidth are extremely useful in RF and video
applications. To insure compliance with slew rate and
transient response specifications, all devices are 100%
tested for AC performance characteristics over full
temperature limits. To improve signal conditioning accuracy,
the HA-2510/883 provides a maximum offset current of 25nA
and a minimum input impedance of 50MΩ, both at 25
o
C, as
well as offset voltage adjust capability.
Ordering Information
TEMP.
PART
NUMBER
HA2-2510/883 HA2-2510/883 -55 to 125 8 Pin Can T8.C
PAR T
MARKING
RANGE
o
C) PACKAGE
(
PKG.
DWG.
#
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• High Slew Rate . . . . . . . . . . . . . . . . . . . . . . .50V/µs (Min)
65V/µs (Typ)
• Wide Power Bandwidth . . . . . . . . . . . . . . . . 750kHz (Min)
• Low Offset Current . . . . . . . . . . . . . . . . . . . . . . 25nA (Min)
10nA (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . 50MΩ (Min)
100MΩ (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . . .12MHz (Typ)
• Fast Settling Time (0.1% of 10V Step) . . . . . . 250ns (Typ)
• Low Quiescent Supply Current . . . . . . . . . . . . 6mA (Max)
• Internally Compensated For Unity Gain Stability
Applications
• Data Acquisition Systems
•RF Amplifiers
• Video Amplifiers
• Signal Generators
• Pulse Amplification
HA7-2510/883 HA7-2510/883 -55 to 125 8 Ld CERDIP F8.3A
Pinouts
HA-2510/883
(CERDIP)
TOP VIEW
BAL
-IN
+IN
1
2
+
3
V-
4
8
7
6
5
COMP
V+
OUT
BAL
-IN
BAL
2
+IN
HA-2510/883
(METAL CAN)
TOP VIEW
COMP
8
1
-
+
3
4
V-
V+
7
OUT
6
BAL
5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HA-2510/883
www.BDTIC.com/Intersil
Absolute Maximum Ratings Thermal Information
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to V-
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
≤ 1/2 (V+ - V-)
V
INCM
R
≥ 2kΩ
L
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379
JA
for details.
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
PARAMETER SYMBOL CONDITIONS
SUPPLY
= ±15V, R
SOURCE
= 100Ω, R
LOAD
= 500kΩ, V
Thermal Resistance (Typical, Note 1) θ
Metal Can Package . . . . . . . . . . . . . . . . . 160oC/W 75oC/W
CERDIP Package. . . . . . . . . . . . . . . . . . . 120
Package Power Dissipation Limit at 75
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .625mW
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .870mW
Package Power Dissipation Derating Factor Above 75
Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3mW/
CERDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .175
Maximum Storage Temperature Range . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300
= 0V, Unless Otherwise Specified.
OUT
GROUP A
SUBGROUPS TEMP (
o
o
C) MIN MAX UNITS
JA
o
C/W 30oC/W
C for TJ ≤ 175oC
θ
o
C
o
C to 150oC
JC
o
o
o
o
C
C
C
C
Input Offset
Voltage
Input Bias Current +I
Input Offset
Current
Common Mode
Range
Large Signal
Voltage Gain
Common Mode
Rejection Ratio
+CMR V+ = 5V, V- = -25V 1 25 +10 - V
-CMR V+ = 25V, V- = -5V 1 25 - -10 V
+A
-A
+CMRR ∆V
V
-I
I
VOL
IO
B
B
IO
VOL
VCM = 0V 1 25 -8 8 mV
2, 3 125, -55 -18 10 mV
VCM = 0V, +RS = 100kΩ, -RS = 100Ω 1 25 -200 200 nA
2, 3 125, -55 -400 400 nA
VCM = 0V, +RS = 100Ω, -RS = 100kΩ 1 25 -200 200 nA
2, 3 125, -55 -400 400 nA
VCM = 0V, +RS = 100kΩ, -RS = 100kΩ 1 25 -25 25 nA
2, 3 125, -55 -50 50 nA
2, 3 125, -55 +10 - V
2, 3 125, -55 - -10 V
V
= 0V and +10V, RL = 2kΩ 42510-kV/V
OUT
5, 6 125, -55 7.5 - kV/V
V
= 0V and -10V, RL = 2kΩ 42510-kV/V
OUT
5, 6 125, -55 7.5 - kV/V
= +10V, V+ = +5V, V- = -25V, V
CM
= -10V
OUT
12580-dB
2, 3 125, -55 80 - dB
-CMRR ∆V
+10V
= -10V, V+ = +25V, V- = -5V, V
CM
OUT
=
12580-dB
2, 3 125, -55 80 - dB
2
FN3697.4
January 3, 2006
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
www.BDTIC.com/Intersil
Device Tested at: V
PARAMETER SYMBOL CONDITIONS
SUPPLY
= ±15V, R
SOURCE
= 100Ω, R
HA-2510/883
= 500kΩ, V
LOAD
= 0V, Unless Otherwise Specified.
OUT
GROUP A
SUBGROUPS TEMP (
o
C) MIN MAX UNITS
Output Voltage
Swing
Output Current +I
Quiescent Power
Supply Current
Power Supply
Rejection Ratio
Offset Voltage
Adjustment
NOTE:
2. Offset adjustment range is [V
+V
OUT
-V
OUT
OUT
-I
OUT
+I
-I
CC
+PSRR ∆V
-PSRR ∆V
+V
IO
-V
IO
RL = 2kΩ 42510-V
5, 6 125, -55 10 - V
RL = 2kΩ 425--10V
5, 6 125, -55 - -10 V
V
= -10V 4 25 10 - mA
OUT
5, 6 125, -55 7.5 - mA
V
= +10V 4 25 - -10 mA
OUT
5, 6 125, -55 - -7.5 mA
V
CC
Adj Note 2 1 25 VIO-1 - mV
Adj Note 2 1 25 VIO+1 - mV
IO
= 0V,
OUT
I
= 0mA
OUT
V
= 0V,
OUT
I
= 0mA
OUT
= 10V, V+ = +20V, V- = -15V,
SUP
V+ = +10V, V- = -15V
= 10V, V+ = +15V, V- = -20V,
SUP
V+ = +15V, V- = -10V
(Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V.
125-6mA
2, 3 125, -55 - 6.5 mA
125-6-mA
2, 3 125, -55 -6.5 - mA
12580-dB
2, 3 125, -55 80 - dB
12580-dB
2, 3 125, -55 80 - dB
2, 3 125, -55 V
2, 3 125, -55 V
-1 - mV
IO
+1 - mV
IO
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
PARAMETER SYMBOL CONDITIONS
Slew Rate +SR V
Rise and Fall Time t
SUPPLY
= ±15V, R
-SR V
r
t
f
SOURCE
OUT
OUT
V
OUT
V
OUT
= 50Ω, R
= -5V to +5V, 25% ≤ +SR ≤ 75% 7 25 50 - V/µs
= +5V to -5V, 75% ≥ -SR ≥ 25% 7 25 50 - V/µs
= 0 to +200mV, 10% ≤ tr ≤ 90% 7 25 - 50 ns
= 0 to -200mV, 10% ≤ tf ≤ 90% 7 25 - 50 ns
LOAD
= 2kΩ, C
LOAD
= 50pF, A
GROUP A
SUBGROUPS TEMP (
= +1V/V, Unless Otherwise Specified.
VCL
8A, 8B 125, -55 45 - V/µs
8A, 8B 125, -55 45 - V/µs
8A, 8B 125, -55 - 60 ns
8A, 8B 125, -55 - 60 ns
3
o
C) MIN MAX UNITS
FN3697.4
January 3, 2006
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
www.BDTIC.com/Intersil
Device Tested at: V
PARAMETER SYMBOL CONDITIONS
SUPPLY
= ±15V, R
SOURCE
= 50Ω, R
HA-2510/883
= 2kΩ, C
LOAD
LOAD
= 50pF, A
GROUP A
SUBGROUPS TEMP (
= +1V/V, Unless Otherwise Specified.
VCL
o
C) MIN MAX UNITS
Overshoot +OS V
-OS V
Device Characterized at: V
PARAMETER SYMBOL CONDITIONS NOTES TEMP (
Differential Input
Resistance
Full Power
Bandwidth
Minimum Closed Loop
Stable Gain
Quiescent Power
Consumption
NOTES:
3. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters
are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon
data from multiple production runs which reflect lot to lot and within lot variation.
4. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πV
5. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.)
SUPPLY
R
IN
FPBW V
CLSG R
PC V
= 0 to +200mV 7 25 - 40 %
OUT
8A, 8B 125, -55 - 50 %
= 0 to -200mV 7 25 - 40 %
OUT
8A, 8B 125, -55 - 50 %
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
= ±15V, R
VCM = 0V 3 25 50 - MΩ
PEAK
= 2kΩ, CL = 50pF 3 -55 to 125 1 - V/V
L
OUT
= 2kΩ, C
LOAD
= 10V 3, 4 25 750 - kHz
= 0V, I
= 0mA 3, 5 -55 to 125 - 195 mW
OUT
= 50pF, Unless Otherwise Specified.
LOAD
o
C) MIN MAX UNITS
).
PEAK
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2)
Interim Electrical Parameters (Pre Burn-In) 1
Final Electrical Test Parameters 1 (Note 6), 2, 3, 4, 5, 6, 7, 8A, 8B
Group A Test Requirements 1, 2, 3, 4, 5, 6, 7, 8A, 8B
Groups C and D Endpoints 1
NOTE:
6. PDA applies to Subgroup 1 only.
4
FN3697.4
January 3, 2006
Die Characteristics
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SUBSTRATE POTENTIAL (Powered Up):
Unbiased
TRANSISTOR COUNT:
40
PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-2510/883HA-2510/883
HA-2510/883
Burn-In Circuit
+IN
V-
BAL
HA7-2510/883
OUT
BAL-IN
COMP
V+
V-
D
2
= 1MΩ, ±5%, 1/4W (Min)
R
1
= C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
C
1
= 0.01µF/Socket (10%)
C
3
D
= D2 = 1N4002 or Equivalent/Board
1
|(V+) - (V-)| = 30V
1
2
R
1
-
+
3
4
C
2
8
7
C
6
5
3
5
V+
C
D
1
1
FN3697.4
January 3, 2006
Metal Can Packages (Can)
www.BDTIC.com/Intersil
HA-2510/883
REFERENCE PLANE
A
ØD ØD1
F
Q
Øb1
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
α is the basic spacing from the centerline of the tab to terminal 1
3.
and β is the basic spacing of each lead or lead position (N -1
places) from
4. N is the maximum number of terminal positions.
5. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
6. Controlling dimension: INCH.
α, looking at the bottom of the package.
L
L2
L1
A
A
Øe
Øb1
Øb
BASE AND
SEATING PLANE
BASE METAL LEAD FINISH
SECTION A-A
Øb2
e1
ØD2
2
β
N
1
α
k
T8.C MIL-STD-1835 MACY1-X8 (A1)
8 LEAD METAL CAN PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.165 0.185 4.19 4.70 -
Øb 0.016 0.019 0.41 0.48 1
k1
C
L
Øb1 0.016 0.021 0.41 0.53 1
Øb2 0.016 0.024 0.41 0.61 -
ØD 0.335 0.375 8.51 9.40 ØD1 0.305 0.335 7.75 8.51 ØD2 0.110 0.160 2.79 4.06 -
e 0.200 BSC 5.08 BSC -
e1 0.100 BSC 2.54 BSC -
F-0.040 - 1.02 -
k 0.027 0.034 0.69 0.86 -
k1 0.027 0.045 0.69 1.14 2
L 0.500 0.750 12.70 19.05 1
L1 - 0.050 - 1.27 1
L2 0.250 - 6.35 -1
Q 0.010 0.045 0.25 1.14 -
α
β 45
N8 84
45o BSC 45o BSC 3
o
BSC 45o BSC 3
NOTESMIN MAX MIN MAX
Rev. 0 5/18/94
6
FN3697.4
January 3, 2006
HA-2510/883
www.BDTIC.com/Intersil
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1
LEAD FINISH
-D-
BASE
M
SECTION A-A
METAL
b1
M
(b)
α
E
S
S
D
Q
A
-C-
L
eA
eA/2
M
aaa CA - B
c
S
bbb C A - B
BASE
PLANE
SEATING
PLANE
S1
b2
b
ccc C A - BMD
-A-
-B-
S
D
A
A
e
S
S
NOTES:
1. Index area: A notch or a pin one identification mark shall be
located adjacent to pin one and shall be located within the
shaded area shown. The manufacturer’s identification shall not
be used as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
D
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
(c)
SYMBOL
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 b3 0.023 0.045 0.58 1.14 4
c1 0.008 0.015 0.20 0.38 3
S
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
S1 0.005 - 0.13 -7
aaa - 0.015 - 0.38 bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
c 0.008 0.018 0.20 0.46 2
D-0.405 - 10.29 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
L 0.125 0.200 3.18 5.08 Q 0.015 0.060 0.38 1.52 6
o
α
90
105
o
90
o
105
o
-
M-0.0015 - 0.038 2, 3
N8 88
Rev. 0 4/94
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
FN3697.4
January 3, 2006
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