intersil EL4583 DATA SHEET

®

EL4583

Data Sheet May 5, 2006

Sync Separator, 50% Slice, S-H, Filter,
H

OUT

The EL4583 extracts timing from video sync in NTSC, PAL,
and SECAM systems, and non standard formats, or from
computer graphics operating at higher scan rates. Timing
adjustment is via an external resistor. Input without valid
vertical interval (no serration pulses) produces a default
vertical output.

Outputs are: composite sync, vertical sync, filter, burst/back
porch, horizontal, no signal detect, level, and odd/even
output (in interlaced scan formats only).

The EL4583 sync slice level is set to the mid-point between
sync tip and the blanking level. This 50% point is determined
by two internal sample and hold circuits that track sync tip
and back porch levels. It provides hum and noise rejection
and compensates for input levels of 0.5V to 2.0V

P-P

.

A built in filter attenuates the chroma signal to prevent color
burst from disturbing the 50% sync slice. Cut off frequency is
set by a resistor to ground from the Filter Cut Off pin.
Additionally, the filter can be by-passed and video signal fed
directly to the Video Input.

The level output pin provides a signal with twice the sync
amplitude which may be used to control an external AGC
function. A TTL/CMOS compatible No Signal Detect Output
flags a loss or reduction in input signal level. A resistor sets
the Set Detect Level.

The EL4583 is manufactured using Intersil’s high
performance analog CMOS process.

Ordering Information

PART

PART NUMBER

EL4583CN EL4583CN - 16 Ld PDIP MDP0031
EL4583CS EL4583CS - 16 Ld SO (0.150”) MDP0027
EL4583CS-T7 EL4583CS 7” 16 Ld SO (0.150”) MDP0027
EL4583CS-T13 EL4583CS 13” 16 Ld SO (0.150”) MDP0027
EL4583CSZ

(Note)
EL4583CSZ-T7

(Note)
EL4583CSZ-T13

(Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

MARKING

EL4583CSZ - 16 Ld SO (0.150”)

EL4583CSZ 7” 16 Ld SO (0.150”)

EL4583CSZ 13” 16 Ld SO (0.150”)

TAPE &

REEL PACKAGE

(Pb-free)

(Pb-free)

(Pb-free)

PKG.

DWG. #

MDP0027

MDP0027

MDP0027

FN7173.2

Features

• NTSC, PAL, and SECAM sync separation

• Single supply, +5V operation

• Precision 50% slicing

• Built-in programmable color burst filter

• Decodes non-standard vertical

• Horizontal sync output

• Sync. pulse amplitude output

• Same socket can be used for 8 Ld EL4581

• Low-power CMOS

• Detects loss of signal

• Resistor programmable scan rate

• Few external components

• Available in 16 Ld PDIP and 16 Ld SO (0.150”) packages

• Pb-free plus anneal available (RoHS compliant)

Applications

• Video special effects

• Video test equipment

• Video distribution

•Multimedia

• Displays

•Imaging

• Video data capture

• Video triggers

Pinout

EL4583

(16 LD SO, PDIP)

TOP VIEW

FILTER CUT OFF

SET DETECT LEVEL

COMPOSITE SYNC OUT

FILTER INPUT

VERTICAL SYNC OUT

DIGITAL GND

FILTER OUTPUT

COMPOSITE VIDEO INPUT

*NOTE: R

1

2

3

4

5

6

7

8 9

must be a 1% register

SET

ANALOG GND

16

HORIZONTAL SYNC OUT

15

VDD

14

ODD/EVEN OUTPUT

13

RSET*

12

BURST/BACK PORCH OUTPUT

11

NO SIGNAL DETECT OUTPUT

10

LEVEL OUTPUT

1

All other trademarks mentioned are the property of their respective owners.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2002, 2003, 2005, 2006. All Rights Reserved

Manufactured under License, U.S. Patents 5,486,869; 5,754,250.

Manufactured under U.S. Patent 5,528,303.

EL4583

Absolute Maximum Ratings (T

V

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V

CC

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pin Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = T

DC Electrical Specifications V

= 25°C)

A

= 5V, TA = 25°C, R

DD

CC

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

+0.5V

A

= 681kΩ, RF = 22kΩ, RLV = 82kΩ

SET

Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

PARAMETER DESCRIPTION MIN TYP MAX UNIT

I

DD

VDD = 5V (Note 1) 2.5 4 mA
Clamp Voltage Pins 4, 8, unloaded 1.3 1.55 1.8 V
Discharge Current Pins 4, 8, with signal (V

= 2V) 3 6 12 µA

IN

Discharge Current Pins 4, 8, no signal (Note 2) 10 µA
Clamp Charge Current Pins 4, 8, V
Ref. Voltage V

REF

Pin 12, VDD = 5V (Note 3) 1.5 1.75 2 V

= 1V 234mA

IN

Filter Reference Voltage, VRF Pin 1 0.35 0.5 0.65 V
Level Reference Current Pin 2 (Note 4) 1.5 2.5 3.5 µA
V

Output Low Voltage IOL = 1.6mA 350 800 mV

OL

V

Output High Voltage IOH = -40µA 4 V

OH

I

= -1.6mA 2.4 4 V

OH

NOTES:

1. No video signal, outputs unloaded.

2. At loss of signal (pin 10 high) the pull down current source switches to a value of 10µA.

3. Tested for V

4. Current sourced from pin 2 is V

5V ±5%.

DD

REF/RSET

.

Dynamic Specifications R

= 22kΩ, R

F

= 681kΩ, VDD = 5V, Video Input = 1V

SET

, TA = 25°C, CL = 15pF, IOH = -1.6mA, IOL=1.6mA

P-P

PARAMETER DESCRIPTION MIN TYP MAX UNIT

Horizontal Pulse Width, Pin 15, t
Vertical Sync Width, Pin 5, t
Burst/Back Porch Width, Pin 11, t

H

VS

B

Filter Attenuation F
Comp. Sync Prop. Delay, t

CS

(Note 1) 3.8 5 6.2 µs

(Note 2) 195 µs

(Note 1) 2.7 3.7 4.7 µs

= 3.6MHz (Note 3) 12 dB

IN

VIN (Pin 4) - comp sync 250 400 ns
Input Dynamic Range p-p NTSC signal 0.4 2 V
Slice Level Input voltage = 1V

V

SLICE/VBLANK

Level Out, Pin 9 Input voltage = 1V
Vertical Sync Default Time, t

VSD

(Note 4) 27 36 57 µs

P-P

pin 4 500 600 700 mV

P-P,

40 50 60 %
40 50 60

Loss of Signal Time-Out Pin 10 400 600 800 µs
Burst/Back Porch Delay, t

BD

(See Figure 4) 250 400 ns

NOTES:

1. Width is a function of R

2. C/S, vertical, back porch and H are all active low, V

3. Attenuation is a function of R

.

SET

. See filter typical characteristics.

F

= 0.8V; vertical is 3H lines wide of NTSC signal.

OH

4. Vertical pulse width in absence of serrations on input signal.

2

FN7173.2

May 5, 2006

EL4583

Pin Descriptions

PIN

NUMBER PIN NAME PIN FUNCTION

1 Filter Cut-Off A resistor R

increases the filter 3.58MHz color burst attenuation. See the typical performance characteristics.

2 Set Detect

Level

A resistor R
loss of signal output on pin 10. The relationship is V
sync pulse amplitude applied to pin 4. See the typical performance characteristics.

3 Composite

This output replicates all the sync inputs on the input video.

Sync Output

4 Filter Input The filter is a 3 pole active filter with a gain of 2, designed to produce a constant phase delay of nominally 260ns with

signal amplitude. Resistor RF on pin 1 controls the filter cut-off. An internal clamp sets the minimum voltage on pin
4 at 1.55V when the input becomes low impedance. Above the clamp voltage, an input current of 1µA charges the
input coupling capacitor. With loss of signal, the current source switches to a value of 10µA, for faster signal recovery .

5 Vertical Sync

Output

The vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the input
signal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore be
slightly more than 3H lines wide.

6Digital

This is the ground return for digital buffer outputs.

Ground
7 Filter Output Output of the active 3 pole filter which has its input on pin 4. It is recommended to ac couple the output to pin 8.
8 Video Input This input can be directly driven by the signal if it is desired to bypass the filter, for example, in the case of strong

clean signals. This input is 6dB less sensitive than the filter input.

9 Level Output This pin provides an analog voltage which is nominally equal to twice the sync pulse amplitude of the video input

signal applied to pin 4. It therefore provides an indication of signal strength.

10 No Signal

Detect

Output

11 Burst/Back

Porch Output

This is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below a
predetermined amplitude as set by R
initiated.

The start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of serration
pulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse width is a
function of R

12 R

SET

The current through the resistor R
the sampling of the sync pulse 50% point, back porch output and the 2H eliminator. For faster scan rates, the resistor
needs to be reduced inversely. For NTSC 15.7kHz scan rate R

13 Odd/Even

Output

14 V

DD

15 Horizontal

Sync Output

Odd-even output is low for even field and high for odd field. The operation of this circuit has been improved for
rejecting spurious noise pulses such as those present in VCR signals.

5V The internal circuits are designed to have a high immunity to supply variations, although as with most I.C.s a 0.1µF

decoupling capacitor is advisable.
This output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading edge

of the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signal
during vertical blanking are eliminated with an internal 2H eliminator circuit.

16 Analog

This is the ground return for the signal paths in the chips, R

Ground

connected between this input and ground determines the input filter characteristic. Increasing RF

F

connected between pin 2 and ground determines the value of the minimum signal which triggers the

LV

on pin 2. There will be several horizontal lines delay before the output is

LV

. This output can be used for d.c. restore functions where the back porch level is a known reference.

SET

determines the timing of the functions within the I.C. These functions include

SET

MIN = 0.75RLV/R

P

SET

, RF and RLV.

SET

, where VPMIN is the minimum detected

SET

is 681k 1%. R

must be a 1% resistor.

SET

3

FN7173.2

May 5, 2006